MAXIM MAX5888 Technical data
General Description
The MAX5888 is an advanced, 16-bit, 500Msps digitalto-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthesis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic
range (SFDR) at f
OUT
= 40MHz. The DAC supports
update rates of 500Msps and a power dissipation of
only 250mW.
The MAX5888 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1V
P-P
and 1V
P-P
.
The MAX5888 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an external reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5888 are
designed for differential low-voltage differential signal
(LVDS)-compatible voltage levels. The MAX5888 is
available in a 68-lead QFN package with an exposed
paddle (EP) and is specified for the extended industrial
temperature range (-40°C to +85°C).
Refer to the MAX5887 and MAX5886 data sheets for
pin-compatible 14- and 12-bit versions of the MAX5888.
Applications
Base Stations: Single-/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features
♦ 500Msps Output Update Rate
♦ Single 3.3V Supply Operation
♦ Excellent SFDR and IMD Performance
SFDR = 76dBc at f
OUT
= 40MHz (to Nyquist)
IMD = -85dBc at f
OUT
= 10MHz
ACLR = 73dB at f
OUT
= 61MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ Differential, LVDS-Compatible Digital and Clock
Inputs
♦ On-Chip 1.2V Bandgap Reference
♦ Low 130mW Power Dissipation
♦ 68-Lead QFN-EP Package
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2726; Rev 3; 12/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configuration
*EP = Exposed paddle.
PART TEMP RANGE
MAX5888AEGK -40°C to +85°C 68 QFN-EP*
MAX5888EGK -40°C to +85°C 68 QFN-EP*
PINPACKAGE
TOP VIEW
B3P
B3N
B2P
B2N
B1P
B1N
B0P
B0N
DGND
DV
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
DD
PD 17
B4P
B5N
B4N
656667
68
EP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
B5P
DGND
DVDDDGND
B7N
B7P
B8N
B8P
B9N
B9P
B6N
B6P
64
MAX5888
5859606162 5455565763
B10N
B10P
5253
51 B11N
50
49
48 B12P
47
46
45
44
43
42
41
40
39
38
37
36
35
B11P
B12N
B13N
B13P
B14N
B14P
B15N
B15P
DGND
DV
SEL0
N.C.
N.C.
N.C.
N.C.
DD
2322212019 2726252418 2928 323130
DD
AV
REFIO
AGND
FSADJ
DACREF
N.C.
DD
AV
AGND
QFN
IOUTN
IOUTP
AGND
DD
AV
DDAVDD
AV
AGND
3433
AGND
N.C.
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AVDD, DVDD, VCLK to DGND ...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AV
DD
+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AV
DD
+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0P/B0N–B15P/B15N, SEL0,
PD to DGND...........................................-0.3V to DV
DD
+ 0.3V
Continuous Power Dissipation (T
A
= +70°C)
68-Lead QFN-EP (derate 41.7mW/°C above +70°C) ...3333mW
Thermal Resistance (θJA) ..............................................+24°C/W
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
STATIC PERFORMANCE
Resolution 16 Bits
Integral Nonlinearity INL
Differential
Nonlinearity
Offset Error OS -0.025 ±0.003 +0.025 %FS
Offset Drift ±50 ppm/°C
Full-Scale Gain Error GE
Gain Drift
Full-Scale Output Current I
Min Output Voltage Single ended -0.5 V
Max Output Voltage Single ended 1.1 V
Output Resistance R
Output Capacitance C
DYNAMIC PERFORMANCE
Output Update Rate f
Noise Spectral Density
Spurious-Free Dynamic Range to
Nyquist
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DNL
FS
OUT
OUT
OUT
CLK
SFDR f
MAX5888A___, measured differentially,
T
≥ +25°C
A
MAX5888___, measured differentially,
T
≥ +25°C
A
MAX5888A___, measured differentially,
T
≥ +25°C
A
MAX5888___, measured differentially,
T
≥ +25°C
A
External reference, TA ≥ +25°C -3.1 +1.1 %FS
Internal reference ±100
External reference ±50
(Note 1) 2 20 mA
f
= 300MHz f
CLK
= 500MHz f
f
CLK
= 100MHz
CLK
= 16MHz, -12dB FS -165
OUT
= 16MHz, -12dB FS -164
OUT
f
= 1MHz, 0dB FS 88
OUT
f
= 1MHz, -6dB FS 89
OUT
= 1MHz, -12dB FS 85
f
OUT
-0.008 ±0.004 +0.008
±0.006
-0.006 ±0.002 +0.006
±0.003
1MΩ
5pF
1 500 Msps
% FS
% FS
ppm/°C
dB FS/
Hz
dBc
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
Spurious-Free Dynamic Range to
Nyquist
Spurious-Free Dynamic Range,
25MHz Bandwidth
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SFDR
SFDR f
2-Tone IMD TTIMD
4-Tone IMD, 1MHz Frequency
Spacing, GSM Model
FTIMD f
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
ACLR
WCDMA Model
Output Bandwidth BW
-1dB
f
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 500MHz
CLK
= 150MHz f
CLK
f
= 100MHz
CLK
= 300MHz
f
CLK
= 300MHz f
CLK
f
=
CLK
184.32MHz
OUT
f
OUT
f
OUT
f
OUT
T
A
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
OUT
f
OUT1
f
OUT2
f
OU T 1
f
OU T 2
OUT
f
OUT
(Note 2) 450 MHz
= 10MHz, -12dB FS 82
= 30MHz, -12dB FS 79
= 10MHz, -12dB FS 73
= 16MHz, -12dB FS,
≥ +25°C
= 50MHz, -12dB FS 72
= 80MHz, -12dB FS 66
= 10MHz, -12dB FS 67
= 30MHz, -12dB FS 65
= 50MHz, -12dB FS 65
= 80MHz, -12dB FS 63
= 20MHz, -12dB FS 82 dBc
= 9MHz, -6dB FS,
= 10MHz, -6dB FS
= 49M H z, - 12d B FS ,
= 50M H z, - 12d B FS
= 32MHz, -12dB FS -78 dBc
= 61.44MHz 73 dB
REFERENCE
Internal Reference Voltage Range V
Reference Voltage Drift TCO
Reference Input Compliance
Range
Reference Input Resistance R
REFIO
V
REFIOCR
REFIO
REF
ANALOG OUTPUT TIMING
Output Fall Time t
Output Rise Time t
Output Voltage Settling Time t
Output Propagation Delay t
FALL
RISE
SETTLE
PD
90% to 10% (Note 3) 375 ps
10% to 90% (Note 3) 375 ps
Output settles to 0.025% FS (Note 3) 11 ns
(Note 3) 1.8 ns
Glitch Energy 1 pV-s
I
= 2mA 30
Output Noise N
OUT
OUT
I
= 20mA 30
OUT
69 77
-85
-83
1.13 1.22 1.3 V
±50 ppm/°C
0.125 1.250 V
10 kΩ
dBc
dBc
pA/√Hz
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
TIMING CHARACTERISTICS
Data to Clock Setup Time t
SETUP
ns
Data to Clock Hold Time t
HOLD
1.8 ns
Data Latency 3.5
Clock
cycles
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN 0.9 ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN 0.9 ns
LVDS LOGIC INPUTS (B0N–B15N, B0P–B15P)
Differential Input Logic High V
IH
mV
Differential Input Logic Low V
IL
mV
Common-Mode Voltage Range V
COM
V
Differential Input Resistance R
IN
85
125 Ω
Input Capacitance C
IN
5pF
CMOS LOGIC INPUTS (PD, SEL0)
Input Logic High V
IH
0.7 ✕
V
Input Logic Low V
IL
0.3 ✕
V
Input Leakage Current I
IN
-15 +15 µA
Input Capacitance C
IN
5pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
Differential Input Voltage Swing V
CLK
Square wave
V
P-P
Differential Input Slew Rate SR
CLK
(Note 5)
V/µs
Common-Mode Voltage Range V
COM
1.5
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
5pF
POWER SUPPLIES
Analog Supply Voltage Range AV
DD
3.3
V
Digital Supply Voltage Range DV
DD
3.3
V
Clock Supply Voltage Range V
CLK
3.3
V
f
CLK
= 100Msps, f
OUT
= 1MHz 27
Analog Supply Current I
AVDD
Power-down 0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz 7 mA
Digital Supply Current I
DVDD
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz 5.6 mA
Clock Supply Current I
VCLK
Power-down 10 µA
SYMBOL
Referenced to rising edge of clock (Note 4) -0.8
Referenced to rising edge of clock (Note 4)
MIN TYP MAX
100
-100
1.125 1.375
100
DV
DD
DV
DD
≥1.5
≥0.5
>100
±20%
3.135
3.135
3.135
3.465
3.465
3.465
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________ 5
Note 1: Nominal full-scale current I
OUT
= 32 ✕ I
REF
.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5888.
Note 3: Parameter measured single ended into a 50Ω termination resistor.
Note 4: Parameter guaranteed by design.
Note 5: A differential clock input slew rate of >100V/ms is required to achieve the specified dynamic performance.
Note 6: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETER
CONDITIONS
UNITS
f
CLK
= 100Msps, f
OUT
= 1MHz
Power Dissipation P
DISS
Power-down 1
mW
Power-Supply Rejection Ratio PSRR
-1 +1
%FS/V
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V
REFIO
= 1.25V, differential transformer-coupled
analog output, 50Ω double terminated (Figure 7), I
OUT
= 20mA, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by
production test, <+25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
Typical Operating Characteristics
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
0
30
20
10
40
50
60
70
80
90
100
02010 30 40 50
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5888 toc01
f
OUT
(MHz)
SFDR (dBc)
-12dB FS
0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
040
20
30
50 70 90
10
60
80 100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5888 toc02
f
OUT
(MHz)
SFDR (dBc)
-6dB FS
-12dB FS
0dB FS
0
30
20
10
40
50
60
70
80
90
100
010050 150 200 250
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 500MHz)
MAX5888 toc03
f
OUT
(MHz)
SFDR (dBc)
-6dB FS
0dB FS
-12dB FS
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
798101112
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
MAX5888 toc04
f
OUT
(MHz)
2-TONE IMD (dBm)
2 x fT1 - f
T2
2 x fT2 - f
T1
fT2 fT1
A
OUT
= -6dB FS
BW = 5MHz
f
T1
= 9.0252MHz
f
T2
= 10.0417MHz
-40
-60
-50
-80
-70
-90
-100
0
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 300MHz)
MAX5888 toc05
f
OUT
(MHz)
TWO-TONE IMD (dBc)
5025 75 100
-6dB FS
-12dB FS
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
77 7978 80 81 82
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 450MHz)
MAX5888 toc06
f
OUT
(MHz)
2-TONE IMD (dBm)
2 x fT1 - f
T2
2 x fT2 - f
T1
fT2 fT1
A
OUT
= -6dB FS
BW = 5MHz
f
T1
= 79.2114MHz
f
T2
= 80.0903MHz
SYMBOL
AVDD = VCLK = DVDD = 3.3V ±5% (Note 6)
MIN TYP MAX
130
MAX5888
3.3V, 16-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
50
58
66
74
82
90
SFDR vs. TEMPERATURE
(f
CLK
= 300MHz, A
OUT
= -6dB FS, I
OUT
= 20mA)
MAX5888toc08
TEMPERATURE (°C)
SFDR (dBc)
-40 10-15 6035 85
f
OUT
= 80MHz
f
OUT
= 120MHz
f
OUT
= 10MHz
f
OUT
= 40MHz
0
20
40
60
80
100
SFDR vs. OUTPUT FREQUENCY
(f
CLK
= 200MHz, A
OUT
= -6dB FS)
MAX5888toc07
f
OUT
(MHz)
SFDR (dBc)
04020
10
30 50
70
90
8060 100
I
OUT
= 20mA
I
OUT
= 5mA
I
OUT
= 10mA
-4.5
-3.0
-1.5
0
1.5
3.0
4.5
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5888toc9
DIGITAL INPUT CODE
INL (LSB)
0 300002000010000 5000040000 7000060000
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
26 3028 3432 36 38
8-TONE MULTITONE POWER RATIO PLOT
(f
CLK
= 300MHz, f
CENTER
= 31.9702MHz)
MAX5888 toc11
f
OUT
(MHz)
8-TONE MTPR (dBm)
fT2 f
T6
fT3 f
T7
fT4 f
T8
f
T1
f
T5
A
OUT
= -18dB FS
BW = 12MHz
f
T1
= 28.0151MHz
f
T2
= 29.0405MHz
f
T3
= 30.0659MHz
f
T4
= 31.0181MHz
f
T5
= 33.06881MHz
f
T6
= 34.0209MHz
f
T7
= 35.0464MHz
f
T8
= 36.0718MHz
80
120
160
200
240
280
POWER DISSIPATION vs. CLOCK FREQUENCY
(f
OUT
= 10MHz, A
OUT
= 0dB FS, I
OUT
= 20mA)
MAX5888toc12
f
CLK
(MHz)
POWER DISSIPATION (mW)
100 300200 400 500
116
120
124
128
132
136
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 100MHz, f
OUT
= 10MHz, IFS = 20mA)
MAX5888toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.135 3.3003.2453.190 3.355 3.410 3.465
EXTERNAL REFERENCE
INTERNAL REFERENCE
DIFFERENTIAL NONLINEARTIY
vs. DIGITAL INPUT CODE
3.0
1.5
0
DNL (LSB)
-1.5
-3.0
0 300002000010000 5000040000 7000060000
DIGITAL INPUT CODE
MAX5888toc10
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