MAXIM MAX5886 Technical data

General Description

The MAX5886 is an advanced, 12-bit, 500Msps digitalto-analog converter (DAC) designed to meet the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from a single 3.3V supply, this DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic range (SFDR) at f

OUT

= 30MHz. The DAC supports update rates of 500Msps and a power dissipation of only 230mW.

The MAX5886 utilizes a current-steering architecture, which supports a full-scale output current range of 2mA to 20mA, and allows a differential output voltage swing between 0.1V

P-P

and 1V

P-P

.

The MAX5886 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low noise performance. Additionally, a separate reference input pin enables the user to apply an external reference source for optimum flexibility and to improve gain accuracy.

The digital and clock inputs of the MAX5886 are designed for differential low-voltage differential signal (LVDS)-compatible voltage levels. The MAX5886 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40°C to +85°C).

Refer to the MAX5887 and MAX5888 data sheets for pin-compatible 14- and 16-bit versions of the MAX5886.

Applications

Base Stations: Single/Multicarrier UMTS, CDMA, GSM

Communications: LMDS, MMDS, Point-to-Point Microwave

Digital Signal Synthesis

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 500Msps Output Update Rate

♦ Single 3.3V Supply Operation

♦ Excellent SFDR and IMD Performance

SFDR = 76dBc at f

OUT

= 30MHz (to Nyquist)

IMD = -85dBc at f

OUT

= 10MHz

ACLR = 70dB at f

OUT

= 61MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ Differential, LVDS-Compatible Digital and Clock

Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low 130mW Power Dissipation

♦ 68-Pin QFN-EP Package

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic

Performance DAC with Differential LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2776; Rev 2; 12/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5886EGK -40°C to +85°C 68 QFN-EP*

5859606162 5455565763

38

39

40

41

42

43

44

45

46

47

VCLK

AGND

B2P

QFN

TOP VIEW

DGND

DVDDDGND

B3N

B3P

B4N

B4P

B5N

B5P

5253

B6N

B6P

AV

DD

FSADJ

REFIO

N.C.

DACREF

AGND

AV

DD

IOUTP

IOUTN

AV

DD

AGND

AV

DDAVDD

B9N

B9P

B10N

B10P

B11N

B11P

DGND

DV

DD

SEL0

N.C.

35

36

37 N.C.

N.C.

DV

DD

DGND

N.C.

VCLK

CLKGND

CLKN

CLKP

CLKGND

N.C.

48 B8P

N.C.

64

B2N

656667

B0P

B1N

B1P

68

B0N

2322212019 2726252418 2928 323130

AGND

N.C.

3433

49

50

B7P

B8N

51 B7N

11

10

9

8

7

6

5

4

3

2

16

15

14

13

12

1

PD 17

MAX5886

EP

Pin Configuration

*EP = Exposed paddle.

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V

REFIO

= 1.25V, differential transformer-coupled

analog output, 50Ω double terminated (Figure 7), I

OUT

= 20mA, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by

production test, <+25°C guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V

AV

DD

, DVDD, VCLK to DGND ...............................-0.3V to +3.9V

AV

DD

, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V

AGND, CLKGND to DGND....................................-0.3V to +0.3V

DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V

IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V

CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V

B0P/B0N–B11P/B11N, SEL0,

PD to DGND...........................................-0.3V to DVDD+ 0.3V

Continuous Power Dissipation (TA= +70°C)

68-Pin QFN-EP (derate 41.7mW/°C above +70°C) ......3333mW

Thermal Resistance (θJA) ..............................................+24°C/W

Operating Temperature Range ..........................-40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range ............................-60°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

PARAMETER

CONDITIONS

UNITS

STATIC PERFORMANCE

Resolution 12 Bits

Integral Nonlinearity INL Measured differentially

LSB

Differential Nonlinearity DNL Measured differentially

LSB

Offset Error OS

%FS

Offset Drift

ppm/°C

Full-Scale Gain Error GE

FS

External reference, TA ≥ +25°C

%FS

Internal reference

Gain Drift

External reference

ppm/°C

Full-Scale Output Current I

OUT

(Note 1) 2 20 mA

Min Output Voltage Single ended

V

Max Output Voltage Single ended 1.1 V

Output Resistance R

OUT

1MΩ

Output Capacitance C

OUT

5pF

DYNAMIC PERFORMANCE

Output Update Rate f

CLK

1 500

Msps

Noise Spectral Density

dB FS/

Hz

f

OUT

= 1MHz, 0dB FS 88

f

OUT

= 1MHz, -6dB FS 86

Nyquist

SFDR

f

OUT

= 1MHz, -12dB FS 80

dBc

SYMBOL

MIN TYP MAX

±0.2

±0.15

-0.025 ±0.01 +0.025 ±50

-3.5 +1.5

±100

±50

-0.5

Spurious-Free Dynamic Range to

f

= 100MHz f

CLK

f

= 200MHz f

CLK

f

= 100MHz

CLK

= 16MHz, -12dB FS -151

OUT

= 80MHz, -12dB FS -154

OUT

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic

Performance DAC with Differential LVDS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V

REFIO

= 1.25V, differential transformer-coupled

analog output, 50Ω double terminated (Figure 7), I

OUT

= 20mA, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by

production test, <+25°C guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

CONDITIONS

UNITS

81

76

71

TA ≥ +25°C

69 76

72

64

66

63

65

Nyquist

SFDR

58

dBc

-85

2-Tone IMD TTIMD

-61

dBc

4-Tone IMD, 1MHz Frequency Spacing, GSM Model

FTIMD

-78 dBc

Adjacent Channel Leakage

WCDMA Model

ACLR

f

CLK

=

184.32MHz

f

OUT

= 61.44MHz 70 dB

Output Bandwidth

(Note 2)

MHz

REFERENCE

V

REFIO

V

Reference Voltage Drift

ppm/°C

Reference Input Compliance Range

0.1

V

Reference Input Resistance R

REFIO

10 kΩ

ANALOG OUTPUT TIMING

Output Fall Time t

FALL

90% to 10% (Note 3)

ps

Output Rise Time t

RISE

10% to 90% (Note 3)

ps

Output Voltage Settling Time

Output settles to 0.025% FS (Note 3) 11 ns

Output Propagation Delay t

PD

(Note 3) 1.8 ns

Glitch Energy 1

pV-s

I

OUT

= 2mA 30

Output Noise N

OUT

I

OUT

= 20mA 30

pA/√Hz

TIMING CHARACTERISTICS

Data to Clock Setup Time t

SETUP

ns

Data to Clock Hold Time t

HOLD

1.8 ns

SYMBOL

Spurious-Free Dynamic Range to

f

= 100MHz

CLK

f

= 200MHz

CLK

f

= 500MHz

CLK

f

= 200MHz

CLK

f

= 200MHz

CLK

f

= 300MHz f

CLK

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT

f

OUT1

f

OUT2

f

OU T 1

f

OU T 2

OUT

= 10MHz, -12dB FS

= 30MHz, -12dB FS

= 10MHz, -12dB FS

= 16MHz, -12dB FS,

= 50MHz, -12dB FS

= 80MHz, -12dB FS

= 10MHz, -12dB FS

= 30MHz, -12dB FS

= 50MHz, -12dB FS

= 80MHz, -12dB FS

= 9MHz, -6dB FS, = 10MHz, -6dB FS

= 79M H z, - 6d B FS , = 80M H z, - 6d B FS

= 32MHz, -12dB FS

Power Ratio, 4.1MHz Bandwidth,

BW

-1dB

Internal Reference Voltage Range

TCO

REF

V

REFIOCR

t

SETTLE

Referenced to rising edge of clock (Note 4) -0.8

Referenced to rising edge of clock (Note 4)

MIN TYP MAX

450

1.12 1.22 1.32

±50

375

1.25

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V

REFIO

= 1.25V, differential transformer-coupled

analog output, 50Ω double terminated (Figure 7), I

OUT

= 20mA, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by

production test, <+25°C guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

CONDITIONS

UNITS

Data Latency 3.5

Clock

cycles

Minimum Clock Pulse Width High

t

CH

CLKP, CLKN 0.9 ns

Minimum Clock Pulse Width Low

t

CL

CLKP, CLKN 0.9 ns

LVDS LOGIC INPUTS (B0N–B11N, B0P–B11P)

Differential Input Logic High V

IH

mV

Differential Input Logic Low V

IL

mV

Common-Mode Voltage Range V

COM

V

Differential Input Resistance R

IN

85

125 Ω

Input Capacitance C

IN

5pF

CMOS LOGIC INPUTS (PD, SEL0)

Input Logic High V

IH

0.7 x V

Input Logic Low V

IL

0.3 x V

Input Leakage Current I

IN

-15 +15 µA

Input Capacitance C

IN

5pF

CLOCK INPUTS (CLKP, CLKN)

Sine wave

Differential Input Voltage Swing V

CLK

Square wave

V

P-P

Differential Input Slew Rate SR

CLK

(Note 5)

V/µs

Common-Mode Voltage Range V

COM

1.5 V

Input Resistance R

CLK

5kΩ

Input Capacitance C

CLK

5pF

POWER SUPPLIES

Analog Supply Voltage Range AV

DD

3.3

V

Digital Supply Voltage Range DV

DD

3.3

V

Clock Supply Voltage Range V

CLK

3.3

V

f

CLK

= 100Msps, f

OUT

= 1MHz 27

Analog Supply Current I

AVDD

Power-down 0.3

mA

f

CLK

= 100Msps, f

OUT

= 1MHz 6.4 mA

Digital Supply Current I

DVDD

Power-down 10 µA

f

CLK

= 100Msps, f

OUT

= 1MHz 5.6 mA

Clock Supply Current I

VCLK

Power-down 10 µA

SYMBOL

MIN TYP MAX

100

-100

1.125 1.375

100

DV

DD

3.135

≥1.5 ≥0.5

>100

±20%

DV

DD

3.465

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic

Performance DAC with Differential LVDS Inputs

_______________________________________________________________________________________ 5

Note 1: Nominal full-scale current I

OUT

= 32 ✕ I

REF

.

Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5886. Note 3: Parameter measured single ended into a 50Ω termination resistor. Note 4: Parameter guaranteed by design. Note 5: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance. Note 6: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

PARAMETER

CONDITIONS

UNITS

f

CLK

= 100Msps, f

OUT

= 1MHz

.

Power Dissipation P

DISS

Power-down 1

mW

Power-Supply Rejection Ratio PSRR

-1 +1

% FS/V

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0, external reference, V

REFIO

= 1.25V, differential transformer-coupled

analog output, 50Ω double terminated (Figure 7), I

OUT

= 20mA, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by

production test, <+25°C guaranteed by design and characterization. Typical values are at T

A

= +25°C.)

Typical Operating Characteristics

(AVDD= DVDD= VCLK = 3.3V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA, TA= +25°C, unless otherwise noted.)

0

30

20

10

40

50

60

70

80

90

100

02010 30 40 50

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 100MHz)

MAX5886 toc01

f

OUT

(MHz)

SFDR (dBc)

-12dB FS

0dB FS

-6dB FS

0

30

20

10

40

50

60

70

80

90

100

10 5020 80 90 100

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 200MHz)

MAX5886 toc02

f

OUT

(MHz)

SFDR (dBc)

-12dB FS

0dB FS

-6dB FS

30 40

70

60

0

30

20

10

40

50

60

70

80

90

100

5 10555 155 205 255

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 500MHz)

MAX5886 toc03

f

OUT

(MHz)

SFDR (dBc)

-6dB FS

0dB FS

-12dB FS

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

375111315

2-TONE INTERMODULATION DISTORTION

(f

CLK

= 100MHz)

MAX5886 toc04

f

OUT

(MHz)

OUTPUT POWER (dBm)

f

T1

= 8.9478MHz

f

T2

= 9.8999MHz

A

OUT

= -6dB FS

BW = 12MHz

2 x fT2 - f

T1

2 x fT1 - f

T2

9

fT2

fT1

-50

-60

-80

-70

-90

-100

10

2-TONE IMD vs. OUTPUT FREQUENCY

(1MHz CARRIER SPACING, f

CLK

= 200MHz)

MAX5886 toc05

f

OUT

(MHz)

TWO-TONE IMD (dBc)

3020 40 80

-12dB FS

-6dB FS

507060

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

74 7876 84 86

2-TONE INTERMODULATION DISTORTION

(f

CLK

= 500MHz)

MAX5886 toc06

f

OUT

(MHz)

OUTPUT POWER (dBm)

2 x fT1 - f

T2

fT1 fT2

f

T1

= 78.7964MHz

f

T2

= 79.7729MHz

2 x fT2 - f

T1

80

82

A

OUT

= -6dB FS

BW = 12MHz

SYMBOL

AVDD = VCLK = DVDD = 3.3V ±5% (Note 6)

MIN TYP MAX

130

MAX5886

3.3V, 12-Bit, 500Msps High Dynamic Performance DAC with Differential LVDS Inputs

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= VCLK = 3.3V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA, TA= +25°C, unless otherwise noted.)

45

53

61

69

77

85

SFDR vs. TEMPERATURE

(f

CLK

= 300MHz, A

OUT

= -6dB FS, I

OUT

= 20mA)

MAX5886 toc08

TEMPERATURE (°C)

SFDR (dBc)

-40 10-15 6035 85

f

OUT

= 80MHz

f

OUT

= 120MHz

f

OUT

= 10MHz

f

OUT

= 40MHz

0

20

40

60

80

100

SFDR vs. OUTPUT FREQUENCY

(f

CLK

= 300MHz, A

OUT

= -6dB FS)

MAX5886 toc07

f

OUT

(MHz)

SFDR (dBc)

06030 12090 150

I

OUT

= 5mA

I

OUT

= 10mA

I

OUT

= 20mA

-0.3

-0.1

0

0.2

0.3

DIFFERENTIAL NONLINEARTIY

vs. DIGITAL INPUT CODE

MAX5886 toc10

DIGITAL INPUT CODE

DNL (LSB)

0 1500 2000500 3500

3000

4500

4000

1000

2500

-0.2

0.1

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5886 toc09

DIGITAL INPUT CODE

INL (LSB)

015001000500 25002000 45003000

3500

4000

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

26 3028 3432 36 38

8-TONE MULTITONE POWER RATIO PLOT

(f

CLK

= 300MHz, f

CENTER

= 31.6040MHz)

MAX5886 toc11

f

OUT

(MHz)

OUTPUT POWER (dBm)

fT2

f

T6f

T3

f

T7

fT4

f

T8

f

T1

f

T5

A

OUT

= -18dB FS

BW = 12MHz

f

T1

= 27.8687MHz

f

T2

= 28.8208MHz

f

T3

= 29.6997MHz

f

T4

= 30.7251MHz

f

T5

= 32.4829MHz

f

T6

= 34.0209MHz

f

T7

= 34.8999MHz

f

T8

= 35.9985MHz

80

120

160

200

240

280

POWER DISSIPATION vs. CLOCK FREQUENCY (f

OUT

= 10MHz, A

OUT

= 0dB FS, I

OUT

= 20mA)

MAX5886 toc12

f

CLK

(MHz)

POWER DISSIPATION (mW)

100 300200 400 500

120

125

135

140

145

150

POWER DISSIPATION vs. SUPPLY VOLTAGE

(f

CLK

= 100MHz, f

OUT

= 10MHz, IFS = 20mA)

MAX5886 toc13

SUPPLY VOLTAGE (V)

POWER DISSIPATION (mW)

3.135 3.3003.2453.190 3.355 3.410 3.465

130

EXTERNAL REFERENCE

INTERNAL REFERENCE

MAXIM MAX5886 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual