General Description
The MAX5885 is an advanced, 16-bit, 200Msps digitalto-analog converter (DAC) designed to meet the
demanding performance requirements of signal synthesis applications found in wireless base stations and
other communications applications. Operating from a
single 3.3V supply, this DAC offers exceptional dynamic performance such as 77dBc spurious-free dynamic
range (SFDR) at f
OUT
= 10MHz. The DAC supports
update rates of 200Msps at a power dissipation of less
than 200mW.
The MAX5885 utilizes a current-steering architecture,
which supports a full-scale output current range of 2mA
to 20mA, and allows a differential output voltage swing
between 0.1V
P-P
and 1V
P-P
.
The MAX5885 features an integrated 1.2V bandgap
reference and control amplifier to ensure high accuracy
and low noise performance. Additionally, a separate
reference input pin enables the user to apply an external reference source for optimum flexibility and to
improve gain accuracy.
The digital and clock inputs of the MAX5885 are
designed for CMOS-compatible voltage levels. The
MAX5885 is available in a 48-pin QFN package with an
exposed paddle (EP) and is specified for the extended
industrial temperature range (-40°C to +85°C).
Refer to the MAX5883 and MAX5884 data sheets for
pin-compatible 12- and 14-bit versions of the MAX5885.
For LVDS high-speed versions, refer to the MAX5886/
MAX5887/MAX5888 data sheet.
Applications
Base Stations: Single/Multicarrier UMTS,
CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point
Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features
♦ 200Msps Output Update Rate
♦ Single 3.3V Supply Operation
♦ Excellent SFDR and IMD Performance
SFDR = 77dBc at f
OUT
= 10MHz (to Nyquist)
IMD = -88dBc at f
OUT
= 10MHz
ACLR = 74dB at f
OUT
= 30.72MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ CMOS-Compatible Digital and Clock Inputs
♦ On-Chip 1.2V Bandgap Reference
♦ Low Power Dissipation
♦ 48-Pin QFN-EP Package
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2786; Rev 1; 12/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5885EGM -40°C to +85°C 48 QFN-EP*
B12
B13
B15
DGND
N.C.
N.C.
N.C.
N.C.
N.C.
DV
DD
SEL0
B14
XOR
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
PD
AV
DD
AGND
B0
B1
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
AGND
IOUTN
IOUTP
AV
DD
AGND
AV
DD
AGND
N.C.
DACREF
FSADJ
REFIO
B3B4B5B6DV
DD
DGNDB7B8
B9
B11
B10
B2
QFN
MAX5885
AGND
TOP VIEW
4847464544434241403938
37
1314151617181920212223
24
Pin Configuration
*EP = Exposed paddle.
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AV
DD
, DVDD, VCLK to DGND ...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0–B15, SEL0, PD, XOR to DGND.............-0.3V to DVDD+ 0.3V
Continuous Power Dissipation (T
A
= +70°C)
48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW
Thermal Resistance (
θJA) ..............................................+37°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
STATIC PERFORMANCE
Resolution 16 Bits
Integral Nonlinearity INL Measured differentially
%FS
Differential Nonlinearity DNL Measured differentially
%FS
Offset Error OS
%FS
Offset Drift
ppm/°C
Full-Scale Gain Error GE
FS
External reference, TA ≥ +25°C
%FS
Internal reference
Gain Drift
External reference
ppm/°C
Full-Scale Output Current I
OUT
(Note 1) 2 20 mA
Min Output Voltage Single ended
V
Max Output Voltage Single ended 1.1 V
Output Resistance R
OUT
1MΩ
Output Capacitance C
OUT
5pF
DYNAMIC PERFORMANCE
Output Update Rate f
CLK
1 200
Msps
Noise Spectral Density
dB FS/
Hz
f
OUT
= 1MHz, 0dB FS 88
f
OUT
= 1MHz, -6dB FS 83
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
OUT
= 1MHz, -12dB FS 80
dBc
SYMBOL
MIN TYP MAX
±0.006
±0.003
-0.025 ±0.003 +0.025
±50
-3.5 +1.3
±100
±50
-0.5
f
= 100MHz f
CLK
f
= 200MHz f
CLK
f
= 100MHz
CLK
= 16MHz, -12dB FS -155
OUT
= 80MHz, -12dB FS -148
OUT
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
77
73
72
f
OUT
= 16MHz, -12dB FS,
T
A
≥+25°C
68 76
71
Spurious-Free Dynamic Range to
Nyquist
SFDR
71
dBc
f
OUT1
= 9MHz, -6dB FS
-88
Two-Tone IMD TTIMD
-74
dBc
Four-Tone IMD, 1MHz Frequency
Spacing, GSM Model
FTIMD
f
OUT
= 31.99MHz,
-12dB FS
-82 dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
WCDMA Model
ACLR
f
CLK
=
184.32MHz
f
OUT
= 30.72MHz 74 dB
Output Bandwidth
(Note 2)
MHz
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.1
V
Reference Input Compliance
Range
V
Reference Input Resistance R
REFIO
10 kΩ
Reference Voltage Drift
ppm/°C
ANALOG OUTPUT TIMING
Output Fall Time t
FALL
90% to 10% (Note 3)
ps
Output Rise Time t
RISE
10% to 90% (Note 3)
ps
Output Voltage Settling Time
Output settles to 0.025% FS (Note 3) 11 ns
Output Propagation Delay t
PD
(Note 3) 1.8 ns
Glitch Energy 1
pV-s
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time t
SETUP
0.4 ns
Data to Clock Hold Time t
HOLD
ns
BW
-1dB
V
REFIOCR
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 150MHz
CLK
f
= 10MHz, -12dB FS
OUT
= 30MHz, -12dB FS
f
OUT
f
= 10MHz, -12dB FS
OUT
f
= 30MHz, -12dB FS
OUT
= 50MHz, -12dB FS
f
OUT
= 10MHz, -6dB FS
f
OUT2
f
= 29M H z, - 6d B FS
OU T 1
= 30M H z, - 6d B FS
f
OU T 2
TCO
REF
t
SETTLE
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4) 1.25
450
1.21 1.34
0.125 1.25
±50
375
375
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
4 _______________________________________________________________________________________
Note 1: Nominal full-scale current I
OUT
= 32 ✕ I
REF
.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885.
Note 3: Parameter measured single ended into a 50Ω termination resistor.
Note 4: Parameter guaranteed by design.
Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA,
f
CLK
= 200Msps, TA= T
MIN
to T
MAX
, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
UNITS
Data Latency 3.5
Clock
cycles
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN 1.5 ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN 1.5 ns
CMOS LOGIC INPUTS (B0–B15, PD, SEL0, XOR)
Input Logic High V
IH
0.7 x
V
Input Logic Low V
IL
0.3 x
V
Input Leakage Current I
IN
-15 +15 µA
Input Capacitance C
IN
5pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
Differential Input Voltage Swing V
CLK
Square wave
V
P-P
Differential Input Slew Rate SR
CLK
(Note 5)
V/µs
Common-Mode Voltage Range V
COM
1.5
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
5pF
POWER SUPPLIES
Analog Supply Voltage Range AV
DD
3.3
V
Digital Supply Voltage Range DV
DD
3.3
V
Clock Supply Voltage Range V
CLK
3.3
V
f
CLK
= 100Msps, f
OUT
= 1MHz 27
Analog Supply Current I
AVDD
Power-down 0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz 8.5 mA
Digital Supply Current I
DVDD
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz 5.5 mA
Clock Supply Current I
VCLK
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz
Power Dissipation P
DISS
Power-down 1
mW
Power-Supply Rejection Ratio PSRR
%FS/V
SYMBOL
MIN TYP MAX
DV
DD
DV
DD
AVDD = VCLK = DVDD = 3.3V ±5% (Note 5) -0.1 +0.1
3.135
3.135
3.135
≥1.5
≥0.5
>100
±20%
135
3.465
3.465
3.465
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
0
30
20
10
40
50
60
70
80
90
100
0105152025
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 50MHz)
MAX5885 toc01
f
OUT
(MHz)
SFDR (dBc)
-12dB FS
0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
02010 30 40 50
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5885 toc02
f
OUT
(MHz)
SFDR (dBc)
-6dB FS
-12dB FS
0dB FS
0
30
20
10
40
50
60
70
80
90
100
03015 45 60 75
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 150MHz)
MAX5885 toc03
f
OUT
(MHz)
SFDR (dBc)
-12dB FS
0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
04010 80 90 100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5885 toc04
f
OUT
(MHz)
SFDR (dBc)
20 30
70
6050
-12dB FS
0dB FS
-6dB FS
-40
-60
-50
-80
-70
-90
-100
0
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 100MHz)
MAX5885 toc05
f
OUT
(MHz)
TWO-TONE IMD (dBc)
10 20 50
-12dB FS
-6dB FS
30
40
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
24 28272625 3433 3635
TWO-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
MAX5885 toc06
f
OUT
(MHz)
OUTPUT POWER (dBm)
3029
3231
2 x fT1 - f
T2
fT1 fT2
f
T1
= 28.9429MHz
f
T2
= 29.8706MHz
2 x fT2 - f
T1
A
OUT
= -6dB FS
BW = 12MHz
0
20
40
60
80
100
SFDR vs. OUTPUT FREQUENCY
(f
CLK
= 200MHz, A
OUT
= -6dB FS)
MAX5885 toc08
f
OUT
(MHz)
SFDR (dBc)
0405010 20 30 8060 70 90 100
I
OUT
= 5mA
I
OUT
= 10mA
I
OUT
= 20mA
-40
-50
-60
-80
-70
-90
-100
0
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200MHz)
MAX5885 toc07
f
OUT
(MHz)
TWO-TONE IMD (dBc)
2010 30 80
-12dB FS
-6dB FS
40
60 70
50
0
30
20
10
40
50
60
70
80
90
100
04010 70 80 90 100
SFDR vs. f
OUT
AND TEMPERATURE
(f
CLK
= 200MHz, A
OUT
= -6dB FS, IFS = 20mA)
MAX5885 toc09
f
OUT
(MHz)
SFDR (dBc)
20 306050
TA = -40°C
TA = +25°C
TA = +85°C
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50Ω, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
-4
-3
-2
-1
0
1
2
3
4
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5885 toc10
DIGITAL INPUT CODE
INL (LSB)
0 10000 20000 30000 40000 50000 60000 70000
-3
-2
-1
0
1
2
3
DIFFERENTIAL NONLINEARTIY
vs. DIGITAL INPUT CODE
MAX5885 toc11
DIGITAL INPUT CODE
DNL (LSB)
0 10000 20000 30000 40000 50000 60000 70000
90
110
130
150
170
190
POWER DISSIPATION vs. CLOCK FREQUENCY
(f
OUT
= 10MHz, A
OUT
= 0dB FS, I
OUT
= 20mA)
MAX5885 toc12
f
CLK
(MHz)
POWER DISSIPATION (mW)
25 7550 100 150125 175 200
130
146
154
162
170
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 100MHz, f
OUT
= 10MHz, IFS = 20mA)
MAX5885 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.135 3.3003.2453.190 3.355 3.410 3.465
138
EXTERNAL REFERENCE
INTERNAL REFERENCE
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________ 7
Pin Description
PIN NAME FUNCTION
1 B1 Data Bit 1
2 B0 Data Bit 0 (LSB)
3XOR
XOR Input Pin.
XOR = 1 inverts the digital input data.
XOR = 0 leaves the digital input data unchanged.
XOR has an internal pulldown resistor and may be left unconnected if not used.
4, 9 VCLK
Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest CLKGND.
5, 8
Clock Ground
6 CLKP Converter Clock Input. Positive input terminal for the converter clock.
7 CLKN Complementary Converter Clock Input. Negative input terminal for the converter clock.
10 PD
Power-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC.
11, 21, 23
AV
DD
Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest AGND.
12, 17, 20,
22, 24, EP
AGND Analog Ground. Exposed paddle (EP) must be connected to AGND.
13 REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 0.1µF
capacitor to AGND. Can be driven with an external reference source.
14 FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2kΩ resistor between FSADJ and DACREF.
15 DACREF
Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF.
16, 25, 26,
27, 28, 29
N.C. No connection. Do not connect to these pins. Do not tie these pins together.
18 IOUTN
Complementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.
19 IOUTP
DAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.
30 SEL0
Mode Select Input SEL0. This pin has an internal pulldown resistor; it can be left open to disable the
segment-shuffling function (see the Segment Shuffling section).
31, 43 DV
DD
Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1µF capacitor to the nearest DGND.
32, 42 DGND Digital Ground
33 B15 Data Bit 15 (MSB)
34 B14 Data Bit 14
35 B13 Data Bit 13
36 B12 Data Bit 12
37 B11 Data Bit 11
CLKGND
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
8 _______________________________________________________________________________________
PIN NAME FUNCTION
38 B10 Data Bit 10
39 B9 Data Bit 9
40 B8 Data Bit 8
41 B7 Data Bit 7
44 B6 Data Bit 6
45 B5 Data Bit 5
46 B4 Data Bit 4
47 B3 Data Bit 3
48 B2 Data Bit 2
Pin Description (continued)
1.2V
REFERENCE
CURRENT-STEERING
DAC
FUNCTION
SELECTION
BLOCK
AGND
SEL0DGND
DV
DD
REFIO
FSADJ
CLKN
CLKP
PD
AV
DD
IOUTP
IOUTN
SEGMENT SHUFFLING/LATCH
DECODER
CMOS RECEIVER/INPUT LATCH
16
DIGITAL INPUTS B0 THROUGH B15
MAX5885
Figure 1. Simplified MAX5885 Block Diagram
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________ 9
Detailed Description
Architecture
The MAX5885 is a high-performance, 16-bit, currentsteering DAC (Figure 1) capable of operating with
clock speeds up to 200MHz. The converter consists of
separate input and DAC registers, followed by a current-steering circuit. This circuit is capable of generating differential full-scale currents in the range of 2mA to
20mA. An internal current-switching network in combination with external 50Ω termination resistors convert
the differential output currents into a differential output
voltage with a peak-to-peak output voltage range of
0.1V to 1V. An integrated 1.2V bandgap reference,
control amplifier, and user-selectable external resistor
determine the data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5885 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the
DAC is operating with the internal reference. For stable
operation with the internal reference, REFIO should be
decoupled to AGND with a 0.1µF capacitor. Due to its
limited output drive capability, REFIO must be buffered
with an external amplifier, if heavier loading is required.
The MAX5885’s reference circuit (Figure 2) employs a
control amplifier, designed to regulate the full-scale
current I
OUT
for the differential current outputs of the
DAC. Configured as a voltage-to-current amplifier, the
output current can be calculated as follows:
I
OUT
= 32 ✕ I
REFIO
- 1 LSB
I
OUT
= 32 ✕ I
REFIO
- (I
OUT
/ 216)
where I
REFIO
is the reference output current (I
REFIO
=
V
REFIO/RSET
) and I
OUT
is the full-scale output current
of the DAC. Located between FSADJ and DACREF,
R
SET
is the reference resistor, which determines the
amplifier’s output current for the DAC. See Table 1 for a
matrix of different I
OUT
and R
SET
selections.
Analog Outputs (IOUTP, IOUTN)
The MAX5885 outputs two complementary currents
(IOUTP, IOUTN) that can be operated in a singleended or differential configuration. A load resistor can
convert these two output currents into complementary
single-ended output voltages. The differential voltage
existing between IOUTP and IOUTN can also be converted to a single-ended voltage using a transformer or
a differential amplifier configuration. If no transformer is
used, the output should have a 50Ω termination to the
analog ground and a 50Ω resistor between the outputs.
0.1µF
1.2V
REFERENCE
10kΩ
I
REF
R
SET
DACREF
FSADJ
REFIO
I
REF
= V
REFIO/RSET
CURRENT-STEERING
DAC
AV
DD
IOUTP
IOUTN
Figure 2. Reference Architecture, Internal Reference
Configuration
R
SET
(kΩ)
FULL-SCALE CURRENT
I
OUT
(mA)
REFERENCE CURRENT
I
REF
(µA)
1% EIA STD
OUTPUT VOLTAGE
V
IOUTP/N
* (mV
P-P
)
2 62.5 19.2 19.1 100
5 156.26 7.68 7.5 250
10 312.5 3.84 3.83 500
15 468.75 2.56 2.55 750
20 625 1.92 1.91 1000
Table 1. I
OUT
and R
SET
Selection Matrix Based on a Typical 1.200V Reference Voltage
*Terminated into a 50Ω load.
CALCULATED
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
10 ______________________________________________________________________________________
Although not recommended because of additional
noise pickup from the ground plane, for single-ended
operation IOUTP should be selected as the output, with
IOUTN connected to AGND. Note that a single-ended
output configuration has a higher 2nd-order harmonic
distortion at high output frequencies than a differential
output configuration.
Figure 3 displays a simplified diagram of the
MAX5885’s internal output structure.
Clock Inputs (CLKP, CLKN)
The MAX5885 features a flexible differential clock input
(CLKP, CLKN) operating from separate supplies
(VCLK, CLKGND) to achieve the best possible jitter
performance. The two clock inputs can be driven from
a single-ended or a differential clock source. For single-ended operation, CLKP should be driven by a logic
source, while CLKN should be bypassed to AGND with
a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to V
CLK
/2.
This allows the user to AC-couple clock sources directly
to the device without external resistors to define the DC
level. The input resistance of CLKP and CLKN is >5kΩ.
See Figure 4 for a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband
transformer. These inputs can also be driven from a
CMOS-compatible clock source; however, it is recommended to use sinewave or AC-coupled ECL drive for
best performance.
Data Timing Relationship
Figure 5 shows the timing relationship between differential, digital CMOS data, clock, and output signals.
The MAX5885 features a 1.25ns hold, a 0.4ns setup,
and a 1.8ns propagation delay time. There is a 3.5
clock-cycle latency between CLKP/CLKN transitioning
high/low and IOUTP/IOUTN.
CMOS-Compatible Digital Inputs (B0–B15)
The MAX5885 features single-ended, CMOS-compatible
receivers on the bus input interface. These CMOS inputs
(B0–B15) allow for a voltage swing of 3.3V.
Segment Shuffling (SEL0)
Segment shuffling can improve the SFDR of the
MAX5885 at higher output frequencies and amplitudes.
Note that an improvement in SFDR can only be achieved
at the cost of a slight increase in the DAC’s noise floor.
Pin SEL0 controls the segment-shuffling function. If SEL0
is pulled low, the segment-shuffling function of the DAC is
disabled. SEL0 can also be left open, because an internal
pulldown resistor helps to deactivate the segment-shuffling feature. To activate the MAX5885 segment-shuffling
function, SEL0 must be pulled high.
XOR Function (XOR)
The MAX5885 is equipped with a single-ended, CMOScompatible XOR input, which may be left open (XOR
provides an internal pulldown resistor) or pulled down
to DGND, if not used. Input data is XORed with the bit
applied to the XOR pin. Pulling XOR high inverts the
input data. Pulling XOR low leaves the input data noninverted. By applying a pseudorandom bit stream to XOR
and applying data while XOR is high, the bit transitions
in the digital input data can be decorrelated from the
DAC output, allowing the user to troubleshoot possible
spurious or harmonic distortion degradation due to digital feedthrough on the PC board.
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
1:1
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED TO
DIFFERENTIAL CONVERSION.
TO
DAC
CLKP
0.1µF
0.1µF
CLKN
CLKGND
25Ω
25Ω
Figure 4. Differential Clock Signal Generation
I
OUT
I
OUT
IOUTN IOUTP
CURRENT
SOURCES
CURRENT
SWITCHES
AV
DD
Figure 3. Simplified Analog Output Structure
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
______________________________________________________________________________________ 11
Power-Down Operation (PD)
The MAX5885 also features an active-high power-down
mode, which allows the user to cut the DAC’s current
consumption. A single pin (PD) is used to control the
power-down mode (PD = 1) or reactivate the DAC (PD
= 0) after power-down. Enabling the power-down mode
of this 16-bit CMOS DAC allows the overall power consumption to be reduced to less than 1mW. The
MAX5885 requires 10ms to wake up from power-down
and enter a fully operational state.
Applications Information
Differential Coupling Using a
Wideband RF Transformer
The differential voltage existing between IOUTP and
IOUTN can also be converted to a single-ended voltage using a transformer (Figure 6) or a differential
amplifier configuration. Using a differential transformercoupled output, in which the output power is limited to
0dBm, can optimize the dynamic performance.
However, make sure to pay close attention to the transformer core saturation characteristics when selecting a
transformer for the MAX5885. Transformer core saturation can introduce strong 2nd-harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is also recommended to center tap the
transformer to ground. If no transformer is used, each
DAC output should be terminated to ground with a 50Ω
resistor. Additionally, a 100Ω resistor should be placed
between the outputs (Figure 7).
If a single-ended unipolar output is desirable, IOUTP
should be selected as the output, with IOUTN grounded. However, driving the MAX5885 single ended is not
recommended since additional noise is added (from
the ground plane) in such configurations.
The distortion performance of the DAC depends on the
load impedance. The MAX5885 is optimized for a 50Ω
double termination. It can be used with a transformer
output as shown in Figure 7 or just one 50Ω resistor
from each output to ground and one 50Ω resistor
between the outputs. This produces a full-scale output
power of up to 0dBm depending on the output current
setting. Higher termination impedance can be used at
the cost of degraded distortion performance and
increased output noise voltage.
Adjacent Channel Leakage Power Ratio
(ACLR) Testing for CDMA- and
W-CDMA-Based Base Station
Transceiver Systems (BTS)
The transmitter sections of BTS applications serving
CDMA and W-CDMA architectures must generate carriers with minimal coupling of carrier energy into the adjacent channels. Similar to the GSM/EDGE model (see the
Multitone Testing for GSM/EDGE Applications section), a
transmit mask (Tx mask) exists for this application. The
spread-spectrum modulation function applied to the carrier frequency generates a spectral response, which is uniform over a given bandwidth (up to 4MHz) for a W-CDMAmodulated carrier.
B0 TO B15
CLKN
CLKP
IOUT
N
DIGITAL DATA IS LATCHED ON
THE RISING EDGE OF CLKP
OUTPUT DATA IS UPDATED ON
THE FALLING EDGE OF CLKP
N + 1 N + 2
N - 5 N - 3 N - 1N - 2N - 4
t
SETUP
t
HOLD
t
PD
t
CH
t
CL
N - 1
Figure 5. Detailed Timing Relationship
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
12 ______________________________________________________________________________________
A dominant specification is ACLR, a parameter which
reflects the ratio of the power in the desired carrier
band to the power in an adjacent carrier band. The
specification covers the first two adjacent bands, and is
measured on both sides of the desired carrier.
According to the transmit mask for CDMA and W-CDMA
architectures, the power ratio of the integrated carrier
channel energy to the integrated adjacent channel
energy must be >45dB for the first adjacent carrier slot
(ACLR 1) and >50dB for the second adjacent carrier
slot (ACLR 2). This specification applies to the output of
the entire transmitter signal chain. The requirement for
only the DAC block of the transmitter must be tighter,
with a typical margin of >15dB, requiring the DAC’s
ACLR 1 to be better than 60dB.
Adjacent channel leakage is caused by a single
spread-spectrum carrier, which generates intermodulation (IM) products between the frequency components
located within the carrier band. The energy at one end
of the carrier band generates IM products with the
energy from the opposite end of the carrier band. For
single-carrier W-CDMA modulation, these IMD products
are spread 3.84MHz over the adjacent sideband. Four
contiguous W-CDMA carriers spread their IM products
over a bandwidth of 20MHz on either side of the 20MHz
total carrier bandwidth. In this four-carrier scenario,
only the energy in the first adjacent 3.84MHz sideband
is considered for ACLR 1. To measure ACLR, drive the
converter with a W-CDMA pattern. Make sure that the
signal is backed off by the peak-to-average ratio, such
that the DAC is not clipping the signal. ACLR can then
be measured with the ACLR measurement function built
into your spectrum analyzer.
Figure 8 shows the ACLR performance for a single
W-CDMA carrier (f
CLK
= 184.32MHz, f
OUT
= 30.72MHz)
applied to the MAX5885 (including measurement system
limitations*).
Figure 9 illustrates the ACLR test results for the
MAX5885 with a four-carrier W-CDMA signal at an output frequency of 30.72MHz and a sampling frequency
of 184.32MHz. Considerable care must be taken to
ensure accurate measurement of this parameter.
MAX5885
T2, 1:1
T1, 1:1
V
OUT
, SINGLE ENDED
WIDEBAND RF TRANSFORMER T2
PERFORMS THE DIFFERENTIAL TO
SINGLE-ENDED CONVERSION.
50Ω
100Ω
50Ω
IOUTP
IOUTN
B0–B15
16
AVDDDVDDVCLK
AGND DGND CLKGND
Figure 6. Differential to Single-Ended Conversion Using a Wideband RF Transformer
MAX5885
50Ω
100Ω
50Ω
IOUTP
IOUTN
B0–B15
16
AVDDDVDDVCLK
AGND DGND CLKGND
OUTP
OUTN
Figure 7. MAX5885 Differential Output Configuration
*Note that due to their own IM effects and noise limitations, spectrum analyzers introduce ACLR errors, which can falsify the measurement. For a single-carrier ACLR measurement greater than 70dB, these measurement limitations are significant, becoming even more
restricting for multicarrier measurement. Before attempting an ACLR measurement, it is recommended consulting application notes provided by major spectrum analyzer manufacturers that provide useful tips on how to use their instruments for such tests.
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
______________________________________________________________________________________ 13
Multitone Testing for GSM/EDGE
Applications
The transmitter sections of multicarrier base station
transceiver systems for GSM/EDGE usually present
communication DAC manufacturers with the difficult
task of providing devices with higher resolution, while
simultaneously reducing noise and spurious emissions
over a desired bandwidth.
To specify noise and spurious emissions from base stations, a GSM/EDGE Tx mask is used to identify the DAC
requirements for these parameters. This mask shows
that the allowable levels for noise and spurious emissions are dependent on the offset frequency from the
transmitted carrier frequency. The GSM/EDGE mask
and its specifications are based on a single active carrier with any other carriers in the transmitter being disabled. Specifications displayed in Figure 10 support
per-carrier output power levels of 20W or greater.
Lower output power levels yield less-stringent emission
requirements.
For GSM/EDGE applications, the DAC demands spurious emission levels of less than -80dBc for offset frequencies ≥6MHz. Spurious products from the DAC can
combine with both random noise and spurious products from other circuit elements. The spurious products
from the DAC should therefore be backed off by 6dB or
more to allow for these other sources and still avoid signal clipping.
The number of carriers and their signal levels with
respect to the full scale of the DAC are important as
well. Unlike a full-scale sinewave, the inherent nature of
a multitone signal contains higher peak-to-RMS ratios,
raising the prospect for potential clipping, if the signal
level is not backed off appropriately. If a transmitter
operates with four/eight in-band carriers, each individual carrier must be operated at less than
-12dB FS/-18dB FS to avoid waveform clipping.
The noise density requirements (Table 2) for a
GSM/EDGE-based system can again be derived from
the system’s Tx mask. With a worst-case noise level of
-80dBc at frequency offsets of ≥6MHz and a measurement bandwidth of 100kHz, the minimum noise density
per hertz is calculated as follows:
SNR
MIN
= -80dBc - 10 ✕ log10(100 ✕ 103Hz)
SNR
MIN
= -130dBc/Hz
Since random DAC noise adds to both the spurious tones
and to random noise from other circuit elements, it is recommended reducing the specification limits by about
10dB to allow for these additional noise contributions
while maintaining compliance with the Tx mask values.
-120
-90
-110
-100
-80
-70
-60
-50
-40
-30
ANALOG OUTPUT POWER (dBm)
-20
3.5MHz/div
f
CLK
= 184.32MHz
f
CENTER
= 30.72MHz
ACLR = 74dB
Figure 8. ACLR for W-CDMA Modulation, Single Carrier
-125
-90
-120
-100
-110
-80
-70
-60
-50
-40
-30
ANALOG OUTPUT POWER (dBm)
-25
3.5MHz/div
f
CLK
= 184.32MHz, f
CENTER
= 30.72MHz
ACLR = 67dB
Figure 9. ACLR for W-CDMA Modulation, Four Carriers
O
-30
-60
-70
-73
-75
-80
-90
0.2 0.4 0.6 1.2 1.8 6.0
IMD REQUIREMENT: < -70dBc
30kHz 100kHz
MEASUREMENT BANDWIDTH
TRANSMITTER EDGE
INBAND OUTBAND
WORST-CASE
NOISE LEVEL
AMPLITUDE (dBc)
FREQUENCY OFFSET FROM CARRIER (MHz)
Figure 10. GSM/EDGE Tx Mask Requirements
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
14 ______________________________________________________________________________________
Another key factor in selecting the appropriate DAC for
the Tx path of a multicarrier GSM/EDGE system is the
converter’s ability to offer superior IMD and MTPR performance. Multiple carriers in a designated band generate
unwanted intermodulation distortion between the individual carrier frequencies. A multitone test vector usually
consists of several equally spaced carriers, usually four,
with identical amplitudes. Each of these carriers is representative of a channel within the defined bandwidth of
interest. To verify MTPR, one or more tones are
removed such that the intermodulation distortion performance of the DAC can be evaluated. Nonlinearities
associated with the DAC create spurious tones, some
of which may fall back into the area of the removed
tone, limiting a channel’s carrier-to-noise ratio. Other
spurious components falling outside the band of interest can also be important, depending on the system’s
spectral mask and filtering requirements. Going back to
the GSM/EDGE Tx mask, the IMD specification for adjacent carriers varies somewhat among the different GSM
standards. For the PCS1800 and GSM850 standards,
the DAC must meet an average IMD of -70dBc.
Table 3 summarizes the dynamic performance requirements for the entire Tx signal chain in a four-carrier
GSM/EDGE-based system and compares the previously established converter requirements with a new-generation high dynamic performance DAC.
The four-tone MTPR plot in Figure 11 demonstrates the
MAX5885’s excellent dynamic performance. The center
frequency (f
CENTER
= 31.99MHz) has been removed to
allow detection and analysis of intermodulation or spurious components falling back into this empty spot from
adjacent channels. The four carriers are observed over
a 12MHz bandwidth and are equally spaced at 1MHz.
Each individual output amplitude is backed off to -12dB
FS. Under these conditions, the DAC yields an MTPR
performance of -82dBc.
Grounding, Bypassing, and Power-Supply
Considerations
Grounding and power-supply decoupling can strongly
influence the performance of the MAX5885. Unwanted
digital crosstalk may couple through the input, reference, power supply, and ground connections, affecting
dynamic performance. Proper grounding and powersupply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This
reduces EMI and internal crosstalk that can significantly
affect the dynamic performance of the MAX5885.
Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. High-speed signals should run on lines directly
above the ground plane. Since the MAX5885 has separate analog and digital ground buses (AGND,
CLKGND, and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two planes.
Digital signals should be run above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Digital signals should be kept as far
away from sensitive analog inputs, reference input
sense lines, common-mode input, and clock inputs as
practical. A symmetric design of clock input and analog
output lines is recommended to minimize 2nd-order
NUMBER OF
CARRIERS
CARRIER
(dB FS)
DAC NOISE DENSITY
REQUIREMENT
(dB FS/Hz)
2 -6 -146
4 -12 -152
Table 2. GSM/EDGE Noise Requirements
for Multicarrier Systems
SPECIFICATION
SYSTEM TRANSMITTER
OUTPUT LEVELS
DAC REQUIREMENTS WITH
MARGINS
MAX5885 SPECIFICATIONS
SFDR 80dBc 86dBc 85dBc*
Noise Spectral Density -130dBc/Hz -152dB FS/Hz -155dB FS/Hz
IMD -70dBc -75dBc -79dBc
Carrier Amplitude N/S -12dB FS -12dB FS
Table 3. Summary of Important AC Performance Parameters for Multicarrier GSM/EDGE
Systems
*Measured within a 15MHz window.
POWER LEVEL
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
______________________________________________________________________________________ 15
harmonic distortion components and optimize the
DAC’s dynamic performance. Digital signal paths
should be kept short and run lengths matched to avoid
propagation delay and data skew mismatches.
The MAX5885 supports three separate power-supply
inputs for analog (AV
DD
), digital (DVDD), and clock
(VCLK) circuitry. Each AVDD, DVDD, and VCLK input
should at least be decoupled with a separate 0.1µF
capacitor as close to the pin as possible and their
opposite ends with the shortest possible connection to
the corresponding ground plane (Figure 12). All three
power-supply voltages should also be decoupled at the
point they enter the PC board with tantalum or electrolytic capacitors. Ferrite beads with additional decoupling capacitors forming a pi network could also
improve performance.
The analog and digital power-supply inputs AVDD,
VCLK, and DVDDof the MAX5885 allow a supply voltage range of 3.3V ±5%.
The MAX5885 is packaged in a 48-pin QFN-EP
(package code: G4877-1), providing greater design
flexibility, increased thermal efficiency**, and optimized
AC performance of the DAC. The EP enables the user
to implement grounding techniques, which are necessary to ensure highest performance operation. The EP
must be soldered down to AGND.
In this package, the data converter die is attached to an
EP lead frame with the back of this frame exposed at the
package bottom surface, facing the PC board side of the
package. This allows a solid attachment of the package
to the PC board with standard infrared (IR) flow soldering
techniques. A specially created land pattern on the PC
board, matching the size of the EP (5mm ✕ 5mm),
ensures the proper attachment and grounding of the
DAC. Designing vias*** into the land area and implementing large ground planes in the PC board design
allow for highest performance operation of the DAC. An
array of at least 3 ✕ 3 vias (≤0.3mm diameter per via hole
and 1.2mm pitch between via holes) is recommended for
this 48-pin QFN-EP package.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer function, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset point. For a DAC, the offset point is the
step value when the digital input is at midscale. This
error affects all codes by the same amount.
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
26 3028 3432 36 38
FOUR-TONE MULTITONE POWER RATIO PLOT
(f
CLK
= 150MHz, f
CENTER
= 31.9885MHz)
f
OUT
(MHz)
OUTPUT POWER (dBm)
A
OUT
= -12dB FS
f
T1 fT2
fT3 f
T4
fT1 = 29.9744MHz
f
T2
= 30.9998MHz
fT3 = 32.9773MHz
f
T4
= 33.8196MHz
Figure 11. 4-Tone MTPR Test Results
**Thermal efficiency is not the key factor, since the MAX5885 features low-power operation. The exposed pad is the key element to
ensure a solid ground connection between the DAC and the PC board’s analog ground layer.
***Vias connect the land pattern to internal or external copper planes. It is important to connect as many vias as possible to the analog
ground plane to minimize inductance.
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
16 ______________________________________________________________________________________
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Energy
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch energy
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch-energy is usually
specified in pV-s.
Dynamic Performance Parameter
Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical maximum SNR
can be derived from the DAC’s resolution (N bits):
SNRdB= 6.02
dB
✕ N + 1.76
dB
However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading;
therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four
harmonics, and the DC offset.
FERRITE BEAD
AV
CC
1µF10µF47µF
ANALOG POWER-SUPPLY
SOURCE
FERRITE BEAD
DV
CC
1µF10µF47µF
DIGITAL POWER-SUPPLY
SOURCE
FERRITE BEAD
VCLK
1µF10µF47µF
CLOCK POWER-SUPPLY
SOURCE
AV
DD
AGND
MAX5885
B0–B15
16
0.1µF
DGND
0.1µF
VCLK
CLKGND
0.1µF
OUTP
OUTN
DV
DD
BYPASSING—DAC LEVEL BYPASSING—BOARD LEVEL
Figure 12. Recommended Power-Supply Decoupling and Bypassing Circuitry
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
______________________________________________________________________________________ 17
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR
is usually measured in dBc and with respect to the carrier frequency amplitude or in dB FS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.
Two-/Four-Tone Intermodulation
Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dB FS)
of either input tone to the worst 3rd-order (or higher) IMD
products. Note that 2nd-order IMD products usually fall at
frequencies that can be easily removed by digital filtering;
therefore, they are not as critical as 3rd-order IMDs. The
two-tone IMD performance of the MAX5885 was tested
with the two individual input tone levels set to at least
-6dB FS and the four-tone performance was tested
according to the GSM model at an output frequency of
32MHz and amplitude of -12dB FS.
Adjacent Channel Leakage
Power Ratio (ACLR)
Commonly used in combination with W-CDMA, ACLR
reflects the leakage power ratio in dB between the
measured power within a channel relative to its adjacent channel. ACLR provides a quantifiable method of
determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited
RF signal passes through a nonlinear device.
Chip Information
TRANSISTOR COUNT: 10,721
PROCESS: CMOS
MAX5885
3.3V, 16-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
32, 44, 48L QFN.EPS
H
1
2
21-0092
PACKAGE OUTLINE
32,44,48L QFN, 7x7x0.90 MM
U
H
2
2
21-0092
PACKAGE OUTLINE,
32,44,48L QFN, 7x7x0.90 MM
MAX5885 Package Code: G4877-1
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