MAXIM MAX5885 Technical data

General Description

The MAX5885 is an advanced, 16-bit, 200Msps digitalto-analog converter (DAC) designed to meet the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from a single 3.3V supply, this DAC offers exceptional dynamic performance such as 77dBc spurious-free dynamic range (SFDR) at f

OUT

= 10MHz. The DAC supports update rates of 200Msps at a power dissipation of less than 200mW.

The MAX5885 utilizes a current-steering architecture, which supports a full-scale output current range of 2mA to 20mA, and allows a differential output voltage swing between 0.1V

P-P

and 1V

P-P

.

The MAX5885 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low noise performance. Additionally, a separate reference input pin enables the user to apply an external reference source for optimum flexibility and to improve gain accuracy.

The digital and clock inputs of the MAX5885 are designed for CMOS-compatible voltage levels. The MAX5885 is available in a 48-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40°C to +85°C).

Refer to the MAX5883 and MAX5884 data sheets for pin-compatible 12- and 14-bit versions of the MAX5885. For LVDS high-speed versions, refer to the MAX5886/ MAX5887/MAX5888 data sheet.

Applications

Base Stations: Single/Multicarrier UMTS, CDMA, GSM

Communications: LMDS, MMDS, Point-to-Point Microwave

Digital Signal Synthesis

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 200Msps Output Update Rate

♦ Single 3.3V Supply Operation

♦ Excellent SFDR and IMD Performance

SFDR = 77dBc at f

OUT

= 10MHz (to Nyquist)

IMD = -88dBc at f

OUT

= 10MHz

ACLR = 74dB at f

OUT

= 30.72MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ CMOS-Compatible Digital and Clock Inputs

♦ On-Chip 1.2V Bandgap Reference

♦ Low Power Dissipation

♦ 48-Pin QFN-EP Package

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic

Performance DAC with CMOS Inputs

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2786; Rev 1; 12/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX5885EGM -40°C to +85°C 48 QFN-EP*

B12 B13

B15 DGND

N.C.

N.C. N.C.

N.C.

DV

DD

SEL0

B14

XOR

VCLK

CLKGND

CLKP

CLKN

CLKGND

VCLK

PD

AV

DD

AGND

B0

B1

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

AGND

IOUTN

IOUTP

AV

DD

AGND

AV

DD

AGND

N.C.

DACREF

FSADJ

REFIO

B3B4B5B6DV

DD

DGNDB7B8

B9

B11

B10

B2

QFN

MAX5885

AGND

TOP VIEW

4847464544434241403938

37

1314151617181920212223

24

Pin Configuration

*EP = Exposed paddle.

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA,

f

CLK

= 200Msps, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design

and characterization. Typical values are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V

AV

DD

, DVDD, VCLK to DGND ...............................-0.3V to +3.9V

AVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V

AGND, CLKGND to DGND....................................-0.3V to +0.3V

DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V

IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V

CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V

B0–B15, SEL0, PD, XOR to DGND.............-0.3V to DVDD+ 0.3V

Continuous Power Dissipation (T

A

= +70°C)

48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW

Thermal Resistance (

θJA) ..............................................+37°C/W

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

CONDITIONS

UNITS

STATIC PERFORMANCE

Resolution 16 Bits

Integral Nonlinearity INL Measured differentially

%FS

Differential Nonlinearity DNL Measured differentially

%FS

Offset Error OS

%FS

Offset Drift

ppm/°C

Full-Scale Gain Error GE

FS

External reference, TA ≥ +25°C

%FS

Internal reference

Gain Drift

External reference

ppm/°C

Full-Scale Output Current I

OUT

(Note 1) 2 20 mA

Min Output Voltage Single ended

V

Max Output Voltage Single ended 1.1 V

Output Resistance R

OUT

1MΩ

Output Capacitance C

OUT

5pF

DYNAMIC PERFORMANCE

Output Update Rate f

CLK

1 200

Msps

Noise Spectral Density

dB FS/

Hz

f

OUT

= 1MHz, 0dB FS 88

f

OUT

= 1MHz, -6dB FS 83

Spurious-Free Dynamic Range to

Nyquist

SFDR

f

OUT

= 1MHz, -12dB FS 80

dBc

SYMBOL

MIN TYP MAX

±0.006

±0.003

-0.025 ±0.003 +0.025 ±50

-3.5 +1.3

±100

±50

-0.5

f

= 100MHz f

CLK

f

= 200MHz f

CLK

f

= 100MHz

CLK

= 16MHz, -12dB FS -155

OUT

= 80MHz, -12dB FS -148

OUT

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic

Performance DAC with CMOS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA,

f

CLK

= 200Msps, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design

and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

77

73

72

f

OUT

= 16MHz, -12dB FS,

T

A

≥+25°C

68 76

71

Spurious-Free Dynamic Range to

Nyquist

SFDR

71

dBc

f

OUT1

= 9MHz, -6dB FS

-88

Two-Tone IMD TTIMD

-74

dBc

Four-Tone IMD, 1MHz Frequency Spacing, GSM Model

FTIMD

f

OUT

= 31.99MHz,

-12dB FS

-82 dBc

Adjacent Channel Leakage

Power Ratio, 4.1MHz Bandwidth,

WCDMA Model

ACLR

f

CLK

=

184.32MHz

f

OUT

= 30.72MHz 74 dB

Output Bandwidth

(Note 2)

MHz

REFERENCE

Internal Reference Voltage Range

V

REFIO

1.1

V

Reference Input Compliance Range

V

Reference Input Resistance R

REFIO

10 kΩ

Reference Voltage Drift

ppm/°C

ANALOG OUTPUT TIMING

Output Fall Time t

FALL

90% to 10% (Note 3)

ps

Output Rise Time t

RISE

10% to 90% (Note 3)

ps

Output Voltage Settling Time

Output settles to 0.025% FS (Note 3) 11 ns

Output Propagation Delay t

PD

(Note 3) 1.8 ns

Glitch Energy 1

pV-s

I

OUT

= 2mA 30

Output Noise N

OUT

I

OUT

= 20mA 30

pA/√Hz

TIMING CHARACTERISTICS

Data to Clock Setup Time t

SETUP

0.4 ns

Data to Clock Hold Time t

HOLD

ns

BW

-1dB

V

REFIOCR

f

= 100MHz

CLK

f

= 200MHz

CLK

f

= 100MHz

CLK

f

= 200MHz

CLK

f

= 150MHz

CLK

f

= 10MHz, -12dB FS

OUT

= 30MHz, -12dB FS

f

OUT

f

= 10MHz, -12dB FS

OUT

f

= 30MHz, -12dB FS

OUT

= 50MHz, -12dB FS

f

OUT

= 10MHz, -6dB FS

f

OUT2

f

= 29M H z, - 6d B FS

OU T 1

= 30M H z, - 6d B FS

f

OU T 2

TCO

REF

t

SETTLE

Referenced to rising edge of clock (Note 4)

Referenced to rising edge of clock (Note 4) 1.25

450

1.21 1.34

0.125 1.25

±50

375

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs

4 _______________________________________________________________________________________

Note 1: Nominal full-scale current I

OUT

= 32 ✕ I

REF

.

Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5885. Note 3: Parameter measured single ended into a 50Ω termination resistor. Note 4: Parameter guaranteed by design. Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA,

f

CLK

= 200Msps, TA= T

MIN

to T

MAX

, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design

and characterization. Typical values are at T

A

= +25°C.)

PARAMETER

CONDITIONS

UNITS

Data Latency 3.5

Clock

cycles

Minimum Clock Pulse Width High

t

CH

CLKP, CLKN 1.5 ns

Minimum Clock Pulse Width Low

t

CL

CLKP, CLKN 1.5 ns

CMOS LOGIC INPUTS (B0–B15, PD, SEL0, XOR)

Input Logic High V

IH

0.7 x V

Input Logic Low V

IL

0.3 x V

Input Leakage Current I

IN

-15 +15 µA

Input Capacitance C

IN

5pF

CLOCK INPUTS (CLKP, CLKN)

Sine wave

Differential Input Voltage Swing V

CLK

Square wave

V

P-P

Differential Input Slew Rate SR

CLK

(Note 5)

V/µs

Common-Mode Voltage Range V

COM

1.5 V

Input Resistance R

CLK

5kΩ

Input Capacitance C

CLK

5pF

POWER SUPPLIES

Analog Supply Voltage Range AV

DD

3.3

V

Digital Supply Voltage Range DV

DD

3.3

V

Clock Supply Voltage Range V

CLK

3.3

V

f

CLK

= 100Msps, f

OUT

= 1MHz 27

Analog Supply Current I

AVDD

Power-down 0.3

mA

f

CLK

= 100Msps, f

OUT

= 1MHz 8.5 mA

Digital Supply Current I

DVDD

Power-down 10 µA

f

CLK

= 100Msps, f

OUT

= 1MHz 5.5 mA

Clock Supply Current I

VCLK

Power-down 10 µA

f

CLK

= 100Msps, f

OUT

= 1MHz

Power Dissipation P

DISS

Power-down 1

mW

Power-Supply Rejection Ratio PSRR

%FS/V

SYMBOL

MIN TYP MAX

DV

DD

DV

DD

AVDD = VCLK = DVDD = 3.3V ±5% (Note 5) -0.1 +0.1

3.135

≥1.5 ≥0.5

>100

±20%

135

3.465

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic

Performance DAC with CMOS Inputs

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(AVDD= DVDD= VCLK = 3.3V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA, TA= +25°C, unless otherwise noted.)

0

30

20

10

40

50

60

70

80

90

100

0105152025

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 50MHz)

MAX5885 toc01

f

OUT

(MHz)

SFDR (dBc)

-12dB FS

0dB FS

-6dB FS

0

30

20

10

40

50

60

70

80

90

100

02010 30 40 50

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 100MHz)

MAX5885 toc02

f

OUT

(MHz)

SFDR (dBc)

-6dB FS

-12dB FS

0dB FS

0

30

20

10

40

50

60

70

80

90

100

03015 45 60 75

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 150MHz)

MAX5885 toc03

f

OUT

(MHz)

SFDR (dBc)

-12dB FS

0dB FS

-6dB FS

0

30

20

10

40

50

60

70

80

90

100

04010 80 90 100

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 200MHz)

MAX5885 toc04

f

OUT

(MHz)

SFDR (dBc)

20 30

70

6050

-12dB FS

0dB FS

-6dB FS

-40

-60

-50

-80

-70

-90

-100

0

TWO-TONE IMD vs. OUTPUT FREQUENCY

(1MHz CARRIER SPACING, f

CLK

= 100MHz)

MAX5885 toc05

f

OUT

(MHz)

TWO-TONE IMD (dBc)

10 20 50

-12dB FS

-6dB FS

30

40

-100

-70

-80

-90

-60

-50

-40

-30

-20

-10

0

24 28272625 3433 3635

TWO-TONE INTERMODULATION DISTORTION

(f

CLK

= 100MHz)

MAX5885 toc06

f

OUT

(MHz)

OUTPUT POWER (dBm)

3029

3231

2 x fT1 - f

T2

fT1 fT2

f

T1

= 28.9429MHz

f

T2

= 29.8706MHz

2 x fT2 - f

T1

A

OUT

= -6dB FS

BW = 12MHz

0

20

40

60

80

100

SFDR vs. OUTPUT FREQUENCY

(f

CLK

= 200MHz, A

OUT

= -6dB FS)

MAX5885 toc08

f

OUT

(MHz)

SFDR (dBc)

0405010 20 30 8060 70 90 100

I

OUT

= 5mA

I

OUT

= 10mA

I

OUT

= 20mA

-40

-50

-60

-80

-70

-90

-100

0

TWO-TONE IMD vs. OUTPUT FREQUENCY

(1MHz CARRIER SPACING, f

CLK

= 200MHz)

MAX5885 toc07

f

OUT

(MHz)

TWO-TONE IMD (dBc)

2010 30 80

-12dB FS

-6dB FS

40

60 70

50

0

30

20

10

40

50

60

70

80

90

100

04010 70 80 90 100

SFDR vs. f

OUT

AND TEMPERATURE

(f

CLK

= 200MHz, A

OUT

= -6dB FS, IFS = 20mA)

MAX5885 toc09

f

OUT

(MHz)

SFDR (dBc)

20 306050

TA = -40°C

TA = +25°C

TA = +85°C

MAX5885

3.3V, 16-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= VCLK = 3.3V, external reference, V

REFIO

= 1.25V, RL= 50Ω, I

OUT

= 20mA, TA= +25°C, unless otherwise noted.)

-4

-3

-2

-1

0

1

2

3

4

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5885 toc10

DIGITAL INPUT CODE

INL (LSB)

0 10000 20000 30000 40000 50000 60000 70000

-3

-2

-1

0

1

2

3

DIFFERENTIAL NONLINEARTIY

vs. DIGITAL INPUT CODE

MAX5885 toc11

DIGITAL INPUT CODE

DNL (LSB)

0 10000 20000 30000 40000 50000 60000 70000

90

110

130

150

170

190

POWER DISSIPATION vs. CLOCK FREQUENCY (f

OUT

= 10MHz, A

OUT

= 0dB FS, I

OUT

= 20mA)

MAX5885 toc12

f

CLK

(MHz)

POWER DISSIPATION (mW)

25 7550 100 150125 175 200

130

146

154

162

170

POWER DISSIPATION vs. SUPPLY VOLTAGE

(f

CLK

= 100MHz, f

OUT

= 10MHz, IFS = 20mA)

MAX5885 toc13

SUPPLY VOLTAGE (V)

POWER DISSIPATION (mW)

3.135 3.3003.2453.190 3.355 3.410 3.465

138

EXTERNAL REFERENCE

INTERNAL REFERENCE