MAXIM MAX5884 Technical data

General Description
The MAX5884 is an advanced, 14-bit, 200Msps digital­to-analog converter (DAC) designed to meet the demanding performance requirements of signal synthe­sis applications found in wireless base stations and other communications applications. Operating from a single 3.3V supply, this DAC offers exceptional dyna­mic performance such as 77dBc spurious-free dynamic range (SFDR) at f
OUT
= 10MHz. The DAC supports update rates of 200Msps at a power dissipation of less than 200mW.
The MAX5884 utilizes a current-steering architecture, which supports a full-scale output current range of 2mA to 20mA, and allows a differential output voltage swing between 0.1V
P-P
and 1V
P-P
.
The MAX5884 features an integrated 1.2V bandgap reference and control amplifier to ensure high accuracy and low noise performance. Additionally, a separate reference input pin enables the user to apply an exter­nal reference source for optimum flexibility and to improve gain accuracy.
The digital and clock inputs of the MAX5884 are designed for CMOS-compatible voltage levels. The MAX5884 is available in a 48-pin QFN package with an exposed paddle (EP) and is specified for the extended industrial temperature range (-40°C to +85°C).
Refer to the MAX5883 and MAX5885 data sheets for pin-compatible 12- and 16-bit versions of the MAX5884. For LVDS high-speed versions, refer to the MAX5886, MAX5887, and MAX5888 data sheets.
Applications
Base Stations: Single-/Multicarrier UMTS, CDMA, GSM
Communications: LMDS, MMDS, Point-to-Point Microwave
Digital Signal Synthesis
Automated Test Equipment (ATE)
Instrumentation
Features
200Msps Output Update Rate
Single 3.3V Supply Operation
Excellent SFDR and IMD Performance
SFDR = 77dBc at f
OUT
= 10MHz (to Nyquist)
IMD = -86dBc at f
OUT
= 10MHz
ACLR = 72dB at f
OUT
= 30.72MHz
2mA to 20mA Full-Scale Output Current
CMOS-Compatible Digital and Clock Inputs
On-Chip 1.2V Bandgap Reference
Low Power Dissipation
48-Pin QFN-EP Package
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2825; Rev 1; 12/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX5884EGM -40°C to +85°C 48 QFN-EP*
B10 B11
B13 DGND
N.C.
N.C. N.C.
N.C.
N.C.
DV
DD
SEL0
B12
XOR
VCLK
CLKGND
CLKP
CLKN
CLKGND
VCLK
PD
AV
DD
AGND
N.C.
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
AGND
IOUTN
IOUTP
AV
DD
AGND
AV
DD
AGND
N.C.
DACREF
FSADJ
REFIO
B1B2B3B4DV
DD
DGNDB5B6
B7B9B8
B0
QFN
MAX5884
AGND
TOP VIEW
4847464544434241403938
37
1314151617181920212223
24
Pin Configuration
*EP = Exposed paddle.
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, RL= 50, I
OUT
= 20mA,
f
CLK
= 200Msps, TA= T
MIN
to T
MAX
, unless otherwise noted. +25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, VCLK to AGND................................-0.3V to +3.9V
AV
DD
, DVDD, VCLK to DGND ...............................-0.3V to +3.9V
AVDD, DVDD, VCLK to CLKGND ...........................-0.3V to +3.9V
AGND, CLKGND to DGND....................................-0.3V to +0.3V
DACREF, REFIO, FSADJ to AGND.............-0.3V to AVDD+ 0.3V
IOUTP, IOUTN to AGND................................-1V to AVDD+ 0.3V
CLKP, CLKN to CLKGND...........................-0.3V to VCLK + 0.3V
B0–B13, SEL0, PD, XOR to DGND.............-0.3V to DVDD+ 0.3V
Continuous Power Dissipation (T
A
= +70°C)
48-Pin QFN (derate 27mW/°C above +70°C)............2162.2mW
Thermal Resistance (
θJA) ..............................................+37°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
STATIC PERFORMANCE
Resolution 14 Bits
Integral Nonlinearity INL Measured differentially
LSB
Differential Nonlinearity DNL Measured differentially
LSB
Offset Error OS
%FS
Offset Drift
ppm/°C
Full-Scale Gain Error GE
FS
External reference, TA +25°C
%FS
Internal reference
Gain Drift
External reference
ppm/°C
Full-Scale Output Current I
OUT
(Note 1) 2 20 mA
Min Output Voltage Single ended
V
Max Output Voltage Single ended 1.1 V
Output Resistance R
OUT
1M
Output Capacitance C
OUT
5pF
DYNAMIC PERFORMANCE
Output Update Rate f
CLK
1 200
Msps
f
OUT
= 16MHz, -12dB FS
Noise Spectral Density
f
OUT
= 80MHz, -12dB FS
dB FS/
Hz
f
OUT
= 1MHz, 0dB FS 87
f
OUT
= 1MHz, -6dB FS 82
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
OUT
= 1MHz, -12dB FS 80
dBc
SYMBOL
MIN TYP MAX
±0.8
±0.5
-0.025 ±0.003 +0.025 ±50
-3.5 +1.3
±100
±50
-0.5
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 100MHz
CLK
-153
-148
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, RL= 50, I
OUT
= 20mA,
f
CLK
= 200Msps, TA= T
MIN
to T
MAX
, unless otherwise noted. +25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
OUT
= 10MHz, -12dB FS 77
f
OUT
= 30MHz, -12dB FS 73
f
OUT
= 10MHz, -12dB FS 72
f
OUT
= 16MHz, -12dB FS,
T
A
+25°C
68 74
f
OUT
= 30MHz, -12dB FS 66
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
OUT
= 50MHz, -12dB FS 70
dBc
f
OUT1
= 9MHz, -6dB FS
f
OUT2
= 10MHz, -6dB FS
-86
f
OU T 1
= 29M H z, - 6d B FS
Two-Tone IMD TTIMD
f
OU T 2
= 30M H z, - 6d B FS
-74
dBc
Four-Tone IMD, 1MHz Frequency Spacing, GSM Model
FTIMD
-82 dBc
Adjacent Channel Leakage
Power Ratio, 4.1MHz Bandwidth,
W-CDMA Model
ACLR
f
CLK
=
184.32MHz
f
OUT
= 30.72MHz 72 dB
Output Bandwidth
(Note 2)
MHz
REFERENCE
Internal Reference Voltage Range
V
REFIO
1.1
V
Reference Input Compliance Range
V
Reference Input Resistance R
REFIO
10 k
Reference Voltage Drift
ppm/°C
ANALOG OUTPUT TIMING
Output Fall Time t
FALL
90% to 10% (Note 3)
ps
Output Rise Time t
RISE
10% to 90% (Note 3)
ps
Output Voltage Settling Time
Output settles to 0.025% FS (Note 3) 11 ns
Output Propagation Delay t
PD
(Note 3) 1.8 ns
Glitch Energy 1
pV-s
I
OUT
= 2mA 30
Output Noise N
OUT
I
OUT
= 20mA 30
pA/Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time t
SETUP
0.4 ns
Data to Clock Hold Time t
HOLD
ns
f
= 100MHz
CLK
f
= 200MHz
CLK
f
= 100MHz
CLK
f
= 200MHz
CLK
f
BW
-1dB
V
REFIOCR
TCO
REF
= 150MHz f
CLK
= 31.99MHz, -12dB FS
OUT
t
SETTLE
Referenced to rising edge of clock (Note 4)
Referenced to rising edge of clock (Note 4) 1.25
450
1.22 1.34
0.125 1.25
±50
375
375
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs
4 _______________________________________________________________________________________
Note 1: Nominal full-scale current I
OUT
= 32 I
REF
.
Note 2: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5884. Note 3: Parameter measured single ended into a 50termination resistor. Note 4: Parameter guaranteed by design. Note 5: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= VCLK = 3.3V, AGND = DGND = CLKGND = 0V, external reference, V
REFIO
= 1.25V, RL= 50, I
OUT
= 20mA,
f
CLK
= 200Msps, TA= T
MIN
to T
MAX
, unless otherwise noted. +25°C guaranteed by production test, <+25°C guaranteed by design
and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
CONDITIONS
Data Latency 3.5
Clock
Minimum Clock Pulse Width High
t
CH
CLKP, CLKN 1.5 ns
Minimum Clock Pulse Width Low
t
CL
CLKP, CLKN 1.5 ns
CMOS LOGIC INPUTS (B0–B13, PD, SEL0, XOR)
Input Logic High V
IH
0.7 x V
Input Logic Low V
IL
0.3 x V
Input Leakage Current I
IN
-15 +15 µA
Input Capacitance C
IN
5pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
Differential Input Voltage Swing V
CLK
Square wave
Differential Input Slew Rate SR
CLK
V/µs
Common-Mode Voltage Range V
COM
1.5 V
Input Resistance R
CLK
5k
Input Capacitance C
CLK
5pF
POWER SUPPLIES
Analog Supply Voltage Range AV
DD
3.3
V
Digital Supply Voltage Range DV
DD
3.3
V
Clock Supply Voltage Range V
CLK
3.3
V
f
CLK
= 100Msps, f
OUT
= 1MHz 27
Analog Supply Current I
AVDD
Power-down 0.3
mA
f
CLK
= 100Msps, f
OUT
= 1MHz 8 mA
Digital Supply Current I
DVDD
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz 5.5 mA
Clock Supply Current I
VCLK
Power-down 10 µA
f
CLK
= 100Msps, f
OUT
= 1MHz
Power Dissipation P
DISS
Power-down 1
mW
Power-Supply Rejection Ratio PSRR
SYMBOL
MIN TYP MAX UNITS
DV
DD
DV
cycles
DD
AVDD = VCLK = DVDD = 3.3V ±5% (Note 5) -0.1 +0.1 %FS/V
3.135
3.135
3.135
1.50.5
>100
±20%
134
3.465
3.465
3.465
V
P-P
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic
Performance DAC with CMOS Inputs
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
0
30
20
10
40
50
60
70
80
90
100
0105152025
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 50MHz)
MAX5884 toc01
f
OUT
(MHz)
SFDR (dBc)
-12dB FS
0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
02010 30 40 50
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 100MHz)
MAX5884 toc02
f
OUT
(MHz)
SFDR (dBc)
-6dB FS
-12dB FS
0dB FS
0
30
20
10
40
50
60
70
80
90
100
03015 45 60 75
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 150MHz)
MAX5884 toc03
f
OUT
(MHz)
SFDR (dBc)
-12dB FS 0dB FS
-6dB FS
0
30
20
10
40
50
60
70
80
90
100
04010 80 90 100
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY (f
CLK
= 200MHz)
MAX5884 toc04
f
OUT
(MHz)
SFDR (dBc)
20 30
70
6050
-12dB FS
0dB FS
-6dB FS
-40
-60
-50
-80
-70
-90
-100
0
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 100MHz)
MAX5884 toc05
f
OUT
(MHz)
2-TONE IMD (dBc)
10 20 50
-12dB FS
-6dB FS
30
40
-100
-70
-80
-90
-60
-50
-40
-30
-20
-10
0
24 28272625 3433 3635
2-TONE INTERMODULATION DISTORTION
(f
CLK
= 100MHz)
MAX5884 toc06
f
OUT
(MHz)
OUTPUT POWER (dBm)
3029
3231
2 x fT1 - f
T2
fT1 fT2
f
T1
= 28.9429MHz
f
T2
= 29.8706MHz
2 x fT2 - f
T1
A
OUT
= -6dB FS
BW = 12MHz
0
20
40
60
80
100
SFDR vs. OUTPUT FREQUENCY
(f
CLK
= 200MHz, A
OUT
= -6dB FS)
MAX5884 toc08
f
OUT
(MHz)
SFDR (dBc)
0405010 20 30 8060 70 90 100
I
OUT
= 5mA
I
OUT
= 10mA
I
OUT
= 20mA
-40
-50
-60
-80
-70
-90
-100
0
2-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200MHz)
MAX5884 toc07
f
OUT
(MHz)
2-TONE IMD (dBc)
2010 30 80
-12dB FS
-6dB FS
40
60 70
50
0
30
20
10
40
50
60
70
80
90
100
04010 70 80 90 100
SFDR vs. f
OUT
AND TEMPERATURE
(f
CLK
= 200MHz, A
OUT
= -6dB FS, IFS = 20mA)
MAX5884 toc09
f
OUT
(MHz)
SFDR (dBc)
20 306050
TA = -40°C
TA = +25°C
TA = +85°C
MAX5884
3.3V, 14-Bit, 200Msps High Dynamic Performance DAC with CMOS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= VCLK = 3.3V, external reference, V
REFIO
= 1.25V, RL= 50, I
OUT
= 20mA, TA= +25°C, unless otherwise noted.)
-1.0
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5884 toc10
DIGITAL INPUT CODE
INL (LSB)
0 2000 4000 6000 8000 1000012000140001600018000
-1.0
-0.8
-0.6
-0.4
-0.2
0.6
0.8
0.4
0.2
0
1.0
DIFFERENTIAL NONLINEARTIY
vs. DIGITAL INPUT CODE
MAX5884 toc11
DIGITAL INPUT CODE
DNL (LSB)
0 2000 4000 6000 8000 1000012000140001600018000
90
110
130
150
170
190
POWER DISSIPATION vs. CLOCK FREQUENCY
(f
OUT
= 10MHz, A
OUT
= 0dB FS, I
OUT
= 20mA)
MAX5884 toc12
f
CLK
(MHz)
POWER DISSIPATION (mW)
25 7550 100 150125 175 200
130
150
160
170
180
190
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 100MHz, f
OUT
= 10MHz, IFS = 20mA)
MAX5884 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.135 3.3003.2453.190 3.355 3.410 3.465
140
EXTERNAL REFERENCE
INTERNAL REFERENCE
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