MAXIM MAX5878 Technical data

General Description

The MAX5878 is an advanced 16-bit, 250Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 76dBc spurious-free dynamic range (SFDR) at f

OUT

= 16MHz and supports update rates of

250Msps, with a power dissipation of only 296mW. The MAX5878 utilizes a current-steering architecture

that supports a 2mA to 20mA full-scale output current range, and allows a 0.1V

P-P

to 1V

P-P

differential output voltage swing. The device features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy.

The clock inputs of the MAX5878 accept both LVDS and LVPECL-compatible voltage levels. The device features an interleaved data input that allows a single LVDS bus to support both DACs. The MAX5878 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40°C to +85°C).

Refer to the MAX5876* and MAX5877* data sheets for pin-compatible 12-bit and 14-bit versions of the MAX5878, respectively. Refer to the MAX5875 data sheet for a CMOS-compatible version of the MAX5878.

Applications

Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fixed Broadband Wireless Access,

Point-to-Point Microwave Direct Digital Synthesis (DDS) Cable Modem Termination Systems (CMTS) Automated Test Equipment (ATE) Instrumentation

Features

♦ 250Msps Output Update Rate

♦ Noise Spectral Density = -164dBFS/Hz

at f

OUT

= 16MHz

♦ Excellent SFDR and IMD

SFDR = 76dBc at f

OUT

= 16MHz (to Nyquist)

SFDR = 71dBc at f

OUT

= 80MHz (to Nyquist)

IMD = -90dBc at f

OUT

= 10MHz

IMD = -72dBc at f

OUT

= 80MHz

♦ ACLR = 75dB at f

OUT

= 61MHz

♦ 2mA to 20mA Full-Scale Output Current

♦ LVDS-Compatible Digital and Clock Inputs

♦ On-Chip +1.20V Bandgap Reference

♦ Low 296mW Power Dissipation

♦ Compact 68 QFN-EP Package (10mm x 10mm)

♦ Evaluation Kit Available (MAX5878EVKIT)

MAX5878

16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

5859606162 5455565763

38

39

40

41

42

43

44

45

46

47

DV

DD3.3

AV

DD1.8

B7N

QFN

TOP VIEW

B7P

DV

DD1.8

B8N

B8P

B9N

B9P

B10N

B10P

B11N

5253

B11P

B12N

DACREF

AV

DD3.3

GND

AV

DD3.3

OUTQP

OUTQN

GND

OUTIP

OUTIN

AV

DD3.3

GND

AV

DD3.3

B14P

B15N

B15P

SELIQN

SELIQP

XORP

XORN

PD

TORB

CLKP

35

36

37 CLKN

GND

AV

CLK

GND

B0N

B0P

B1N

B1P

REFIO

GND

AV

DD3.3

GND

B2N

B2P

B3N

B3P

48 B14N

B4N

64

B6P

656667

B5N

B5P

B6N

68

B4P

2322212019 2726252418 2928 323130

GND

AV

DD1.8

3433

49

50

B13N

B13P

51 B12P

11

10

9

8

7

6

5

4

3

2

16

15

14

13

12

1

FSADJ 17

MAX5878

Pin Configuration

Ordering Information

19-3591; Rev 0; 2/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

**EP = Exposed pad.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PKG CODE

MAX5878EGK

G6800-4

Selector Guide

PART

RESOLUTION

(BITS)

UPDATE

RATE

LOGIC

INPUTS

MAX5873 12 200Msps CMOS

MAX5874 14 200Msps CMOS

MAX5875 16 200Msps CMOS

12 250Msps LVDS

14 250Msps LVDS

MAX5878 16 250Msps LVDS

*Future product—contact factory for availability.

查询MAX5873供应商

PACKAGE

-40°C to +85°C 68 QFN-EP**

MAX5876*

MAX5877*

MAX5878

16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AV

DD1.8

, DV

DD1.8

to GND, DACREF...................-0.3V to +2.16V

AV

DD3.3

, DV

DD3.3

, AV

CLK

to GND, DACREF........-0.3V to +3.9V

REFIO, FSADJ to

GND, DACREF..................................-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF..................-1V to (AV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF.............-0.3V to (AV

CLK

+ 0.3V)

B15P/B15N–B0P/B0N, XORN, XORP, SELIQN,

SELIQP to GND, DACREF ..................-0.3V to (DV

DD1.8

+ 0.3V)

TORB, PD to GND, DACREF ..............-0.3V to (DV

DD3.3

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C) 68-Pin QFN-EP

(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW

Thermal Resistance

θJA(Note 1)...................................+24°C/W

Operating Temperature Range ......................... -40°C to +85°C

Junction Temperature .................................................... +150°C

Storage Temperature Range ........................... -60°C to +150°C

Lead Temperature (soldering, 10s) ............................... +300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution 16 Bits Integral Nonlinearity INL Measured differentially ±3

LSB

Differential Nonlinearity DNL Measured differentially ±2

LSB

Offset Error OS

%FS

Offset-Drift Tempco

ppm/°C

Full-Scale Gain Error GE

FS

External reference

%FS

Internal reference

Gain-Drift Tempco

External reference

ppm/°C

Full-Scale Output Current

(Note 3) 2 20 mA

Output Compliance Single-ended

V

Output Resistance R

OUT

1MΩ

Output Capacitance C

OUT

5pF

DYNAMIC PERFORMANCE

Clock Frequency f

CLK

2

MHz

Output Update Rate f

DAC

1

Msps

f

DAC

= 150MHz f

OUT

= 16MHz, -12dBFS

Noise Spectral Density

f

DAC

= 250MHz f

OUT

= 80MHz, -12dBFS

dBFS/

Hz

ELECTRICAL CHARACTERISTICS

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C.) (Note 2)

Note 1: Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.

-0.015 ±0.001 +0.015 ±10

-4.1 -0.6 +4.1

±100

±50

I

OUTFS

-0.5 +1.1

-164

-161

500

250

MAX5878

16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

f

OUT

= 1MHz, 0dBFS 94

f

OUT

= 1MHz, -6dBFS 87

f

OUT

= 1MHz, -12dBFS 81

f

OUT

= 10MHz, -12dBFS 81

f

DAC

= 100MHz

f

OUT

= 30MHz, -12dBFS 79

f

OUT

= 10MHz, -12dBFS 75

f

OUT

= 16MHz, -12dBFS,

T

A

≥ +25oC

69 76

f

OUT

= 16MHz, -12dBFS 67 76

f

OUT

= 50MHz, -12dBFS 73

f

DAC

= 200MHz

f

OUT

= 80MHz, -12dBFS 71

f

OUT

= 10MHz, -12dBFS 74

f

OUT

= 50MHz, -12dBFS 75

f

OUT

= 80MHz, -12dBFS 71

Spurious-Free Dynamic Range to Nyquist

SFDR

f

DAC

= 250MHz

69

dBc

Spurious-Free Dynamic Range, 25MHz Bandwidth

SFDR f

DAC

= 150MHz f

OUT

= 16MHz, -12dBFS 78

dBc

f

DAC

= 100MHz

f

OUT1

= 9MHz, -7dBFS;

f

OUT2

= 10MHz, -7dBFS

-90

Two-Tone IMD

f

DAC

= 200MHz

f

OUT1

= 79MHz, -7dBFS;

f

OUT2

= 80MHz, -7dBFS

-72

dBc

Four-Tone IMD, 1MHz

Frequency Spacing, GSM Model

f

DAC

= 150MHz f

OUT

= 16MHz, -12dBFS -80

dBc

Adjacent Channel Leakage Power Ratio 3.84MHz Bandwidth, W-CDMA Model

ACLR

f

DAC

=

184.32MHz

f

OUT

= 61.44MHz 75 dB

Output Bandwidth

(Note 4)

MHz

INTER-DAC CHARACTERISTICS

f

OUT

= DC - 80MHz

Gain Matching

f

OUT

= DC

dB

Gain-Matching Tempco

ppm/°C

Phase Matching

f

OUT

= 60MHz

D egr ees

Phase-Matching Tempco

f

OUT

= 60MHz

D eg r ees/

°C

Channel-to-Channel Crosstalk f

CLK

= 400MHz, f

OUT

= 50MHz, 0dBFS 86 dB

REFERENCE

Internal Reference Voltage Range

1.2

V

SYMBOL

MIN TYP MAX

TTIMD

FTIMD

f

= 100MHz, -12dBFS

OUT

BW

-1dB

∆Gain

∆Gain/°C ±20

-0.22 +0.01 +0.22

∆Phase

∆Phase/°C

V

REFIO

1.14

240

±0.2

±0.25

±0.002

1.26

MAX5878

16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

Reference Input Compliance Range

V

Reference Input Resistance

10 kΩ

Reference Voltage Drift

ppm/°C

ANALOG OUTPUT TIMING (See Figure 4)

Output Fall Time t

FALL

90% to 10% (Note 5) 0.7 ns

Output Rise Time t

RISE

10% to 90% (Note 5) 0.7 ns

Output Propagation Delay t

PD

Excluding data latency (Note 5) 1.1 ns

Glitch Impulse Measured differentially 1

pV•s

I

OUTFS

= 2mA 30

Output Noise n

OUT

I

OUTFS

= 20mA 30

pA/√Hz

TIMING CHARACTERISTICS

Data to Clock Setup Time

Referenced to rising edge of clock (Note 6)

ns

Data to Clock Hold Time

Referenced to rising edge of clock (Note 6) 2.0 ns

Latency to I output 9

Data Latency

Latency to Q output 8

Clock

Cycles

Minimum Clock Pulse-Width High

t

CH

CLKP, CLKN 0.9 ns

Minimum Clock Pulse-Width Low

t

CL

CLKP, CLKN 0.9 ns

LVDS LOGIC INPUTS (B15P/B15N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)

Differential Input-Logic High V

IH

mV

Differential Input-Logic Low V

IL

mV

Common-Mode Voltage Range V

CMR

V

Differential Input Resistance R

IN

(Note 7)

Ω

Input Capacitance C

IN

2.5 pF

CMOS LOGIC INPUTS (PD, TORB)

Input-Logic High V

IH

0.7 x V

Input-Logic Low V

IL

0.3 x V

Input Leakage Current I

IN

-20 1

µA

PD, TORB Internal Pulldown Resistance

V

PD

= V

TORB

= 3.3V 1.5 MΩ

Input Capacitance C

IN

2.5 pF

CLOCK INPUTS (CLKP, CLKN)

Sine wave

Differential Input Voltage Swing

Square wave

V

P-P

SYMBOL

MIN TYP MAX

V

REFIOCR

R

REFIO

TCO

REF

t

SETUP

t

HOLD

0.125 1.260

±25

-1.2

-100

1.125 1.375

110

DV

DD3.3

>1.5

>0.5

DV

100

DD3.3

+20

MAX5878

16-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

A

= +25°C.) (Note 2)

Note 2: Specifications at T

A

≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design.

Note 3: Nominal full-scale current I

OUTFS

= 32 x I

REF

.

Note 4: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5878. Note 5: Parameter measured single-ended into a 50Ω termination resistor. Note 6: Not production tested. Guaranteed by design. Note 7: No termination resistance between XORP and XORN. Note 8: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance. Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

PARAMETER

CONDITIONS

UNITS

Differential Input Slew Rate

(Note 8)

V/µs

External Common-Mode Voltage Range

V

COM

±0.3

V

Input Resistance R

CLK

5kΩ

Input Capacitance C

CLK

2.5 pF

POWER SUPPLIES

3.3

Analog Supply Voltage Range

1.8

V

3.3

Digital Supply Voltage Range

1.8

V

f

DAC

= 250Msps, f

OUT

= 16MHz 52 56 mA

Power-down 1 µA

f

DAC

= 250Msps, f

OUT

= 16MHz 32 36 mA

Analog Supply Current

Power-down 1 µA

f

DAC

= 250Msps, f

OUT

= 16MHz 0.2 1 mA

Power-down 1 µA

f

DAC

= 250Msps, f

OUT

= 16MHz 36 40 mA

Digital Supply Current

Power-down 4 µA

f

DAC

= 250Msps, f

OUT

= 16MHz

mW

Power Dissipation P

DISS

Power-down 16 µW

Power-Supply Rejection Ratio

PSRR

AV

DD3.3

= AV

CLK

= DV

DD3.3

= +3.3V ±5%

(Notes 8, 9)

%FS/V

SYMBOL

SR

CLK

AV

DD3.3

AV

DD1.8

DV

DD3.3

DV

DD1.8

I

AVDD3.3

I

AVDD1.8

I

DVDD3.3

I

DVDD1.8

MIN TYP MAX

>100

AV

CLK

3.135

1.710

3.135

1.710

/ 2

3.465

1.890

3.465

1.890

296 324

-0.1 +0.1

MAX5878

16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

6 _______________________________________________________________________________________

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 50Msps)

MAX5878 toc01

f

OUT

(MHz)

SFDR (dBc)

2015105

20

40

60

80

100

0

025

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 100Msps)

MAX5878 toc02

f

OUT

(MHz)

SFDR (dBc)

40302010

20

40

60

80

100

0

050

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 150Msps)

MAX5878 toc03

f

OUT

(MHz)

SFDR (dBc)

60453015

20

40

60

80

100

0

075

-12dBFS

-6dBFS

0dBFS

Typical Operating Characteristics

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, external reference, V

REFIO

= +1.25V, RL = 50Ω double-terminated,

I

OUTFS

= 20mA, TA= +25°C, unless otherwise noted.)

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 200Msps)

MAX5878 toc04

f

OUT

(MHz)

SFDR (dBc)

80604020

20

40

60

80

100

0

0100

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 250Msps)

MAX5878 toc05

f

OUT

(MHz)

SFDR (dBc)

100755025

20

40

60

80

100

0

0 125

-12dBFS

-6dBFS

0dBFS

TWO-TONE IMD vs. OUTPUT FREQUENCY

(1MHz CARRIER SPACING, f

CLK

= 100Msps)

MAX5878 toc06

f

OUT

(MHz)

TWO-TONE IMD (dBc)

353025201510

-90

-80

-110

-70

-60

-100

540

-6dBFS

-12dBFS

MAXIM MAX5878 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual