General Description
The MAX5878 is an advanced 16-bit, 250Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from +3.3V and
+1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 76dBc spurious-free dynamic range
(SFDR) at f
OUT
= 16MHz and supports update rates of
250Msps, with a power dissipation of only 296mW.
The MAX5878 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1V
P-P
to 1V
P-P
differential output
voltage swing. The device features an integrated +1.2V
bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an external reference source for optimum flexibility and
improved gain accuracy.
The clock inputs of the MAX5878 accept both LVDS
and LVPECL-compatible voltage levels. The device features an interleaved data input that allows a single
LVDS bus to support both DACs. The MAX5878 is available in a 68-pin QFN package with an exposed paddle
(EP) and is specified for the extended temperature
range (-40°C to +85°C).
Refer to the MAX5876* and MAX5877* data sheets for
pin-compatible 12-bit and 14-bit versions of the
MAX5878, respectively. Refer to the MAX5875 data
sheet for a CMOS-compatible version of the MAX5878.
Applications
Base Stations: Single/Multicarrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless Access,
Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination Systems (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
♦ 250Msps Output Update Rate
♦ Noise Spectral Density = -164dBFS/Hz
at f
OUT
= 16MHz
♦ Excellent SFDR and IMD
SFDR = 76dBc at f
OUT
= 16MHz (to Nyquist)
SFDR = 71dBc at f
OUT
= 80MHz (to Nyquist)
IMD = -90dBc at f
OUT
= 10MHz
IMD = -72dBc at f
OUT
= 80MHz
♦ ACLR = 75dB at f
OUT
= 61MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ LVDS-Compatible Digital and Clock Inputs
♦ On-Chip +1.20V Bandgap Reference
♦ Low 296mW Power Dissipation
♦ Compact 68 QFN-EP Package (10mm x 10mm)
♦ Evaluation Kit Available (MAX5878EVKIT)
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
________________________________________________________________ Maxim Integrated Products 1
5859606162 5455565763
38
39
40
41
42
43
44
45
46
47
DV
DD3.3
AV
DD1.8
B7N
QFN
TOP VIEW
B7P
DV
DD1.8
B8N
B8P
B9N
B9P
B10N
B10P
B11N
5253
B11P
B12N
DACREF
AV
DD3.3
GND
GND
AV
DD3.3
OUTQP
OUTQN
GND
GND
OUTIP
OUTIN
AV
DD3.3
GND
AV
DD3.3
B14P
B15N
B15P
SELIQN
SELIQP
XORP
XORN
PD
TORB
CLKP
35
36
37 CLKN
GND
AV
CLK
GND
B0N
B0P
B1N
B1P
REFIO
GND
AV
DD3.3
GND
GND
B2N
B2P
B3N
B3P
48 B14N
B4N
64
B6P
656667
B5N
B5P
B6N
68
B4P
2322212019 2726252418 2928 323130
GND
AV
DD1.8
3433
49
50
B13N
B13P
51 B12P
11
10
9
8
7
6
5
4
3
2
16
15
14
13
12
1
FSADJ 17
MAX5878
Pin Configuration
Ordering Information
19-3591; Rev 0; 2/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
**EP = Exposed pad.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PKG CODE
MAX5878EGK
G6800-4
Selector Guide
PART
RESOLUTION
(BITS)
UPDATE
RATE
LOGIC
INPUTS
MAX5873 12 200Msps CMOS
MAX5874 14 200Msps CMOS
MAX5875 16 200Msps CMOS
12 250Msps LVDS
14 250Msps LVDS
MAX5878 16 250Msps LVDS
*Future product—contact factory for availability.
查询MAX5873供应商
PACKAGE
-40°C to +85°C 68 QFN-EP**
MAX5876*
MAX5877*
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1.8
, DV
DD1.8
to GND, DACREF...................-0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to GND, DACREF........-0.3V to +3.9V
REFIO, FSADJ to
GND, DACREF..................................-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF..................-1V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF.............-0.3V to (AV
CLK
+ 0.3V)
B15P/B15N–B0P/B0N, XORN, XORP, SELIQN,
SELIQP to GND, DACREF ..................-0.3V to (DV
DD1.8
+ 0.3V)
TORB, PD to GND, DACREF ..............-0.3V to (DV
DD3.3
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW
Thermal Resistance
θJA(Note 1)...................................+24°C/W
Operating Temperature Range ......................... -40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ........................... -60°C to +150°C
Lead Temperature (soldering, 10s) ............................... +300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution 16 Bits
Integral Nonlinearity INL Measured differentially ±3
LSB
Differential Nonlinearity DNL Measured differentially ±2
LSB
Offset Error OS
%FS
Offset-Drift Tempco
ppm/°C
Full-Scale Gain Error GE
FS
External reference
%FS
Internal reference
Gain-Drift Tempco
External reference
ppm/°C
Full-Scale Output Current
(Note 3) 2 20 mA
Output Compliance Single-ended
V
Output Resistance R
OUT
1MΩ
Output Capacitance C
OUT
5pF
DYNAMIC PERFORMANCE
Clock Frequency f
CLK
2
MHz
Output Update Rate f
DAC
1
Msps
f
DAC
= 150MHz f
OUT
= 16MHz, -12dBFS
Noise Spectral Density
f
DAC
= 250MHz f
OUT
= 80MHz, -12dBFS
dBFS/
Hz
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
Note 1: Thermal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
-0.015 ±0.001 +0.015
±10
-4.1 -0.6 +4.1
±100
±50
I
OUTFS
-0.5 +1.1
-164
-161
500
250
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
CONDITIONS
UNITS
f
OUT
= 1MHz, 0dBFS 94
f
OUT
= 1MHz, -6dBFS 87
f
OUT
= 1MHz, -12dBFS 81
f
OUT
= 10MHz, -12dBFS 81
f
DAC
= 100MHz
f
OUT
= 30MHz, -12dBFS 79
f
OUT
= 10MHz, -12dBFS 75
f
OUT
= 16MHz, -12dBFS,
T
A
≥ +25oC
69 76
f
OUT
= 16MHz, -12dBFS 67 76
f
OUT
= 50MHz, -12dBFS 73
f
DAC
= 200MHz
f
OUT
= 80MHz, -12dBFS 71
f
OUT
= 10MHz, -12dBFS 74
f
OUT
= 50MHz, -12dBFS 75
f
OUT
= 80MHz, -12dBFS 71
Spurious-Free Dynamic Range
to Nyquist
SFDR
f
DAC
= 250MHz
69
dBc
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR f
DAC
= 150MHz f
OUT
= 16MHz, -12dBFS 78
dBc
f
DAC
= 100MHz
f
OUT1
= 9MHz, -7dBFS;
f
OUT2
= 10MHz, -7dBFS
-90
Two-Tone IMD
f
DAC
= 200MHz
f
OUT1
= 79MHz, -7dBFS;
f
OUT2
= 80MHz, -7dBFS
-72
dBc
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model
f
DAC
= 150MHz f
OUT
= 16MHz, -12dBFS -80
dBc
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
W-CDMA Model
ACLR
f
DAC
=
184.32MHz
f
OUT
= 61.44MHz 75 dB
Output Bandwidth
(Note 4)
MHz
INTER-DAC CHARACTERISTICS
f
OUT
= DC - 80MHz
Gain Matching
f
OUT
= DC
dB
Gain-Matching Tempco
ppm/°C
Phase Matching
f
OUT
= 60MHz
D egr ees
Phase-Matching Tempco
f
OUT
= 60MHz
D eg r ees/
°C
Channel-to-Channel Crosstalk f
CLK
= 400MHz, f
OUT
= 50MHz, 0dBFS 86 dB
REFERENCE
Internal Reference Voltage Range
1.2
V
SYMBOL
MIN TYP MAX
TTIMD
FTIMD
f
= 100MHz, -12dBFS
OUT
BW
-1dB
∆Gain
∆Gain/°C ±20
-0.22 +0.01 +0.22
∆Phase
∆Phase/°C
V
REFIO
1.14
240
±0.2
±0.25
±0.002
1.26
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
PARAMETER
CONDITIONS
UNITS
Reference Input Compliance
Range
V
Reference Input Resistance
10 kΩ
Reference Voltage Drift
ppm/°C
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time t
FALL
90% to 10% (Note 5) 0.7 ns
Output Rise Time t
RISE
10% to 90% (Note 5) 0.7 ns
Output Propagation Delay t
PD
Excluding data latency (Note 5) 1.1 ns
Glitch Impulse Measured differentially 1
pV•s
I
OUTFS
= 2mA 30
Output Noise n
OUT
I
OUTFS
= 20mA 30
pA/√Hz
TIMING CHARACTERISTICS
Data to Clock Setup Time
Referenced to rising edge of clock (Note 6)
ns
Data to Clock Hold Time
Referenced to rising edge of clock (Note 6) 2.0 ns
Latency to I output 9
Data Latency
Latency to Q output 8
Clock
Cycles
Minimum Clock Pulse-Width High
t
CH
CLKP, CLKN 0.9 ns
Minimum Clock Pulse-Width Low
t
CL
CLKP, CLKN 0.9 ns
LVDS LOGIC INPUTS (B15P/B15N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)
Differential Input-Logic High V
IH
mV
Differential Input-Logic Low V
IL
mV
Common-Mode Voltage Range V
CMR
V
Differential Input Resistance R
IN
(Note 7)
Ω
Input Capacitance C
IN
2.5 pF
CMOS LOGIC INPUTS (PD, TORB)
Input-Logic High V
IH
0.7 x
V
Input-Logic Low V
IL
0.3 x
V
Input Leakage Current I
IN
-20 1
µA
PD, TORB Internal Pulldown
Resistance
V
PD
= V
TORB
= 3.3V 1.5 MΩ
Input Capacitance C
IN
2.5 pF
CLOCK INPUTS (CLKP, CLKN)
Sine wave
Differential Input
Voltage Swing
Square wave
V
P-P
SYMBOL
MIN TYP MAX
V
REFIOCR
R
REFIO
TCO
REF
t
SETUP
t
HOLD
0.125 1.260
±25
-1.2
-100
1.125 1.375
110
DV
DD3.3
>1.5
>0.5
DV
100
DD3.3
+20
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, GND = 0, f
CLK
= 2 x f
DAC
, external reference V
REFIO
= +1.25V, out-
put load 50Ω double-terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C.) (Note 2)
Note 2: Specifications at T
A
≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design.
Note 3: Nominal full-scale current I
OUTFS
= 32 x I
REF
.
Note 4: This parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the MAX5878.
Note 5: Parameter measured single-ended into a 50Ω termination resistor.
Note 6: Not production tested. Guaranteed by design.
Note 7: No termination resistance between XORP and XORN.
Note 8: A differential clock input slew rate of >100V/µs is required to achieve the specified dynamic performance.
Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
PARAMETER
CONDITIONS
UNITS
Differential Input Slew Rate
(Note 8)
V/µs
External Common-Mode Voltage
Range
V
COM
±0.3
V
Input Resistance R
CLK
5kΩ
Input Capacitance C
CLK
2.5 pF
POWER SUPPLIES
3.3
Analog Supply Voltage Range
1.8
V
3.3
Digital Supply Voltage Range
1.8
V
f
DAC
= 250Msps, f
OUT
= 16MHz 52 56 mA
Power-down 1 µA
f
DAC
= 250Msps, f
OUT
= 16MHz 32 36 mA
Analog Supply
Current
Power-down 1 µA
f
DAC
= 250Msps, f
OUT
= 16MHz 0.2 1 mA
Power-down 1 µA
f
DAC
= 250Msps, f
OUT
= 16MHz 36 40 mA
Digital Supply
Current
Power-down 4 µA
f
DAC
= 250Msps, f
OUT
= 16MHz
mW
Power Dissipation P
DISS
Power-down 16 µW
Power-Supply
Rejection Ratio
PSRR
AV
DD3.3
= AV
CLK
= DV
DD3.3
= +3.3V ±5%
(Notes 8, 9)
%FS/V
SYMBOL
SR
CLK
AV
DD3.3
AV
DD1.8
DV
DD3.3
DV
DD1.8
I
AVDD3.3
I
AVDD1.8
I
DVDD3.3
I
DVDD1.8
MIN TYP MAX
>100
AV
CLK
3.135
1.710
3.135
1.710
/ 2
3.465
1.890
3.465
1.890
296 324
-0.1 +0.1
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
6 _______________________________________________________________________________________
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 50Msps)
MAX5878 toc01
f
OUT
(MHz)
SFDR (dBc)
2015105
20
40
60
80
100
0
025
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 100Msps)
MAX5878 toc02
f
OUT
(MHz)
SFDR (dBc)
40302010
20
40
60
80
100
0
050
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 150Msps)
MAX5878 toc03
f
OUT
(MHz)
SFDR (dBc)
60453015
20
40
60
80
100
0
075
-12dBFS
-6dBFS
0dBFS
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference, V
REFIO
= +1.25V, RL = 50Ω double-terminated,
I
OUTFS
= 20mA, TA= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 200Msps)
MAX5878 toc04
f
OUT
(MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0100
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 250Msps)
MAX5878 toc05
f
OUT
(MHz)
SFDR (dBc)
100755025
20
40
60
80
100
0
0 125
-12dBFS
-6dBFS
0dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 100Msps)
MAX5878 toc06
f
OUT
(MHz)
TWO-TONE IMD (dBc)
353025201510
-90
-80
-110
-70
-60
-100
540
-6dBFS
-12dBFS
TWO-TONE INTERMODULATION
DISTORTION (f
CLK
= 100Msps)
MAX5878 toc07
f
OUT
(MHz)
OUTPUT POWER (dBFS)
3432302826
-80
-60
-40
-20
0
-100
24 36
BW = 12MHz
2 x fT1 - f
T2
2 x fT2 - f
T1
f
T1
f
T2
fT1 = 28.9795MHz
f
T2
= 30.0049MHz
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200Msps)
MAX5878 toc08
f
OUT
(MHz)
TWO-TONE IMD (dBc)
70605040302010
-90
-80
-70
-60
-50
-40
-100
080
-12dBFS
-6dBFS
SFDR vs. FULL-SCALE OUTPUT CURRENT
(f
CLK
= 200MHz)
MAX5878 toc09
f
OUT
(MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0100
A
OUT
= -6dBFS
10mA
5mA
20mA
SFDR vs. TEMPERATURE
(f
CLK
= 250Msps)
MAX5878 toc10
f
OUT
(MHz)
SFDR (dBc)
100755025
70
75
80
85
65
0125
A
OUT
= -6dBFS
TA = +85°C
TA = +25°C
TA = -40°C
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5878 toc11
DIGITAL INPUT CODE
INL (LSB)
49,15232,76816,384
-2
-1
0
1
2
3
-3
065,536
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5878 toc12
DIGITAL INPUT CODE
DNL (LSB)
49,15232,76816,384
-3
-2
-1
0
1
2
3
4
-4
065,536
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference, V
REFIO
= +1.25V, RL = 50Ω double-terminated,
I
OUTFS
= 20mA, TA= +25°C, unless otherwise noted.)
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= +3.3V, AV
DD1.8
= DV
DD1.8
= +1.8V, external reference, V
REFIO
= +1.25V, RL = 50Ω double-terminated,
I
OUTFS
= 20mA, TA= +25°C, unless otherwise noted.)
POWER DISSIPATION vs. CLOCK
FREQUENCY (f
OUT
= 10MHz)
MAX5878 toc13
f
CLK
(Msps)
POWER DISSIPATION (mW)
200 25015010050
200
220
240
280
260
300
180
0
A
OUT
= 0dBFS
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 100Msps, f
OUT
= 10MHz)
MAX5878 toc14
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.465
3.3
215
225
230
210
3.135
A
OUT
= 0dBFS
EXTERNAL REFERENCE
INTERNAL REFERENCE
220
FOUR-TONE POWER RATIO PLOT
(f
CLK
= 150MHz)
MAX5878 toc15
f
OUT
(MHz)
OUTPUT POWER (dBFS)
3634323028
-80
-60
-40
-20
0
-100
26 38
BW = 12MHz
f
T1
f
T2
f
T3
f
T4
fT1 = 29.9433MHz
f
T2
= 30.8266MHz
f
T3
= 31.9087MHz
f
T4
= 32.9123MHz
ACLR FOR W-CDMA MODULATION,
SINGLE CARRIER ACLR
MAX5878 toc16
9.2MHz/div
ANALOG OUTPUT POWER (dBm)
-130
-110
-100
-90
-80
-70
-60
-50
-40
-30
DC 92.16MHz
f
CLK
= 184.32MHz
f
CARRIER
= 30.72MHz
ACLR = +80dB
-20
-120
ACLR FOR W-CDMA MODULATION
TWO CARRIER ACLR
MAX5878 toc17
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-120
f
CLK
= 245.76Msps
f
CENTER
= 30.72MHz
ACLR = +78dB
ACLR FOR W-CDMA MODULATION
TWO CARRIER ACLR
MAX5878 toc18
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
-130
-120
-110
-100
-90
-80
-70
-60
-50
-30
-140
f
CLK
= 184.32Msps
f
CENTER
= 30.72MHz
ACLR = +77dB
-40
W-CDMA BASEBAND ACLR
MAX5878 toc19
NUMBER OF CHANNELS
ACLR (dB)
4321
77
78
80
82
84
76
81.4
82.7
82.3
83.0
80.4
80.7
79.0
79.0
ALTERNATE
ADJACENT
79
81
83
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 B4N Complementary Data Bit 4
2 B3P Data Bit 3
3 B3N Complementary Data Bit 3
4 B2P Data Bit 2
5 B2N Complementary Data Bit 2
6 B1P Data Bit 1
7 B1N Complementary Data Bit 1
8 B0P Data Bit 0 (LSB)
9 B0N Complementary Data Bit 0 (LSB)
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GND Ground
11 DV
DD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
14, 21, 22, 31,
32
AV
DD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1µF capacitor to GND.
16 REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
17 FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table 1.
18 DACREF
Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external
ground connection.
19, 34 AV
DD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
24 OUTQN Complementary Q-DAC Output. Negative terminal for current output.
25 OUTQP Q-DAC Output. Positive terminal for current output.
28 OUTIN Complementary I-DAC Output. Negative terminal for current output.
29 OUTIP I-DAC Output. Positive terminal for current output.
35 AV
CLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
37 CLKN
Complementary Converter Clock Input. Negative input terminal for differential converter clock.
Internally biased to AV
CLK
/ 2.
38 CLKP
Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to
AV
CLK
/ 2.
39 TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’scomplement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format.
TORB has an internal pulldown resistor.
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
10 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
40 PD
Power-Down Input. Set PD to a CMOS-logic-high level to force the DAC into power-down mode.
Set PD to a CMOS-logic-low level for normal operation. PD has an internal pulldown resistor.
41 XORN
Complementary LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow
the data stream to pass unchanged to the DAC input. Set XORN low and XORP high to invert the
DAC input data. If unused, connect XORN to DV
DD1.8
.
42 XORP
LVDS DAC Exclusive-OR Select Input. Set XORN high and XORP low to allow the data stream to
pass unchanged to the DAC input. Set XORN low and XORP high to invert the DAC input data. If
unused, connect XORP to GND.
43 SELIQP
LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the I-DAC outputs.
Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.
44 SELIQN
Complementary LVDS DAC Select Input. Set SELIQN low and SELIQP high to direct data to the
I-DAC outputs. Set SELIQP low and SELIQN high to direct data to the Q-DAC outputs.
45 B15P Data Bit 15 (MSB)
46 B15N Complementary Data Bit 15 (MSB)
47 B14P Data Bit 14
48 B14N Complementary Data Bit 14
49 B13P Data Bit 13
50 B13N Complementary Data Bit 13
51 B12P Data Bit 12
52 B12N Complementary Data Bit 12
53 B11P Data Bit 11
54 B11N Complementary Data Bit 11
55 B10P Data Bit 10
56 B10N Complementary Data Bit 10
57 B9P Data Bit 9
58 B9N Complementary Data Bit 9
59 B8P Data Bit 8
60 B8N Complementary Data Bit 8
61 DV
DD1.8
Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
62 B7P Data Bit 7
63 B7N Complementary Data Bit 7
64 B6P Data Bit 6
65 B6N Complementary Data Bit 6
66 B5P Data Bit 5
67 B5N Complementary Data Bit 5
68 B4P Data Bit 4
—EPExposed Pad. Must be connected to GND through a low-impedance path.
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 11
LATCH
XOR/
DECODE
LATCH
LVDS
RECEIVER
LATCH
LATCH DAC
OUTIP
OUTIN
LATCH
XOR/
DECODE
LATCH LATCH DAC
OUTQP
OUTQN
FSADJ
TORB
SELIQN
XORP
XORN
AV
CLK
CLKN
CLKP
CLK
INTERFACE
DATA15–
DATA0
+1.2V
REFERENCE
POWER-DOWN
BLOCK
REFIO
DACREF
PD GND
DV
DD1.8
DV
DD3.3
AV
DD1.8
AV
DD3.3
SELIQP
MAX5878
Figure 1. MAX5878 High-Performance, 16-Bit, Dual Current-Steering DAC
Detailed Description
Architecture
The MAX5878 high-performance, 16-bit, dual currentsteering DAC (Figure 1) operates with DAC update rates
up to 250Msps. The converter consists of input registers
and a demultiplexer for single-port operation, followed by
a current-steering array. During operation, the input data
registers demultiplex the single-port data bus. The current-steering array generates differential full-scale currents in the 2mA to 20mA range. An internal
current-switching network, in combination with external
50Ω termination resistors, converts the differential output
currents into dual differential output voltages with a 0.1V
to 1V peak-to-peak output voltage range. An integrated
+1.2V bandgap reference, control amplifier, and userselectable external resistor determine the data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5878 supports operation with the internal
+1.2V bandgap reference or an external reference voltage source. REFIO serves as the input for an external,
low-impedance reference source. REFIO also serves as
a reference output when the DAC operates in internal
reference mode. For stable operation with the internal
reference, decouple REFIO to GND with a 1µF capacitor. Due to its limited output drive capability, buffer
REFIO with an external amplifier when driving large
external loads.
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
12 ______________________________________________________________________________________
The MAX5878’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
I
OUTFS
for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where I
OUTFS
is the full-scale output current of the
DAC. R
SET
(located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
OUTFS
and R
SET
selections.
Analog Outputs (OUTIP, OUTIN, OUTQP,
OUTQN)
Each MAX5878 DAC outputs two complementary currents (OUTIP/N, OUTQP/N) that operate in a singleended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25Ω termination resistor to ground and a
50Ω resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation
or increased output swing. Figure 3 displays a simplified diagram of the internal output structure of the
MAX5878.
Clock Inputs (CLKP, CLKN)
The MAX5878 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AV
CLK
) to achieve optimum jitter performance. Drive
the differential clock inputs from a single-ended or a
differential clock source. For single-ended operation,
drive CLKP with a logic source and bypass CLKN to
GND with a 0.1µF capacitor.
CLKP and CLKN are internally biased to AV
CLK
/ 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is 5kΩ.
I
V
R
OUTFS
REFIO
SET
=× ×
−32 1
1
2
16
Table 1. I
OUTFS
and R
SET
Selection
Matrix Based on a Typical +1.200V
Reference Voltage
R
SET
(Ω)
FULL-SCALE
CURRENT I
OUTFS
(mA)
1% EIA STD
2 19.2k 19.1k
5 7.68k 7.5k
10 3.84k 3.83k
15 2.56k 2.55k
20 1.92k 1.91k
Figure 2. Reference Architecture, Internal Reference
Configuration
I
OUT
I
OUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AV
DD
Figure 3. Simplified Analog Output Structure
CALCULATED
+1.2V
REFERENCE
10kΩ
REFIO
1µF
R
SET
/ R
FSADJ
DACREF
SET
I
REF
= V
I
REF
REFIO
GND
CURRENT-SOURCE
OUTIP
ARRAY DAC
OUTIN
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 13
SELIQP
CLKP-CLKN
DATA
IN
I0 Q2I2Q1I1 I3 Q3Q0
t
S
t
H
OUTI
OUTQ
t
PD
I0 - 5
I0 - 4 I0 - 2
I0 - 3
I0 - 6
Q0 - 6
Q0 - 5
Q0 - 4
Q0 - 3 Q0 - 2
SELIQN
Figure 4. Timing Diagram
Data Timing Relationship
Figure 4 displays the timing relationship between digital
LVDS data, clock, and output signals. The MAX5878
features a 2.0ns hold, a -1.2ns setup, and a 1.1ns propagation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN and OUTIP/OUTIN
(OUTQP/OUTQN).
LVDS-Compatible Digital Inputs
(B15P/B15N–B0P/B0N, XORP, XORN,
SELIQP, SELIQN)
The MAX5878 latches B15P/N–B0P/N, XORP/N, and
SELIQP/N data on the rising edge of the clock. A logichigh signal on SELIQP and a logic-low signal on
SELIQN directs data onto the I-DAC inputs. A logic-low
signal on SELIQP and a logic-high signal on SELIQN
directs data onto the Q-DAC inputs.
The MAX5878 features LVDS receivers on the bus input
interface with internal 110Ω termination resistors. See
Figure 5. XORP and XORN are not internally terminated.
These LVDS inputs (B15P/N–B0P/N) allow for a low differential voltage swing with low constant power consumption. A 1.25V common-mode level and 250mV differential
input swing can be applied to the B15P/N–B0P/N,
XORP/N, and SELIQP/N inputs.
The MAX5878 includes LVDS-compatible exclusive-OR
inputs (XORP, XORN). Input data (all bits) is compared
with the bits applied to XORP and XORN through exclusive-OR gates. Setting XORP high and XORN low inverts
the input data. Setting XORP low and XORN high leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input
and applying decoding to XORP/XORN, the digital input
data can be decorrelated from the DAC output, allowing
for the troubleshooting of possible spurious or harmonic
distortion degradation due to digital feedthrough on the
PC board. If XOR functionality is not required, connect
XORP to GND and XORN to DV
DD1.8
.
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
14 ______________________________________________________________________________________
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB)
The TORB input selects between two’s-complement or
offset binary digital input data. Set TORB to a CMOSlogic-high level to indicate a two’s-complement input format. Set TORB to a CMOS-logic-low level to indicate a
binary input format.
Power-Down Operation (PD)
The MAX5878 also features an active-high power-down
mode that reduces the DAC’s digital current consumption from 36.2mA to less than 5µA and the analog current consumption from 84mA to less than 2µA. Set PD
high to power down the MAX5878. Set PD low for normal operation.
When powered down, the MAX5878 reduces the overall
power consumption to less than 16µW. The MAX5878
requires 10ms to wake up from power-down and enter
a fully operational state. The PD integrated pulldown
resistor activates the MAX5878 if PD is left floating.
Applications Information
CLK Interface
The MAX5878 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
CLK
) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps
RMS
for meeting the specified noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 6 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP 8662A signal generator) and a wideband transformer. Alternatively, these inputs can be driven from a
CMOS-compatible clock source; however, it is recommended to use sinewave or AC-coupled differential
ECL/PECL or LVDS drive for best dynamic performance.
110Ω
TO
DECODE
LOGIC
D
D
Q
Q
B15P–B0P,
SELIQP
B15N–B0N,
SELIQN
CLOCK
MAX5878
Figure 5. Simplified LVDS-Compatible Digital Input Structure
DIGITAL INPUT CODE
OFFSET BINARY TWO’S COMPLEMENT
OUT_P OUT_N
0000 0000 0000 0000 1000 0000 0000 0000 0 I
OUTFS
0111 1111 1111 1111 0000 0000 0000 0000 I
OUTFS
/ 2 I
OUTFS
/ 2
1111 1111 1111 1111 0111 1111 1111 1111 I
OUTFS
0
Table 2. DAC Output Code Table
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED
CLOCK SOURCE
(e.g., HP 8662A)
GND
1:1
25Ω
25Ω
CLKP
CLKN
TO DAC
0.1µF
0.1µF
Figure 6. Differential Clock-Signal Generation
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 15
Differential-to-Single-Ended Conversion
Using a Wideband RF Transformer
Use a pair of transformers (Figure 7) or a differential
amplifier configuration to convert the differential voltage
existing between OUTIP/OUTQP and OUTIN/OUTQN to
a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output and limit the output power to <0dBm full scale. Pay
close attention to the transformer core saturation characteristics when selecting a transformer for the
MAX5878. Transformer core saturation can introduce
strong 2nd-order harmonic distortion especially at low
output frequencies and high signal amplitudes. For best
results, center tap the transformer to ground. When not
using a transformer, terminate each DAC output to
ground with a 25Ω resistor. Additionally, place a 50Ω
resistor between the outputs (Figure 8).
For a single-ended unipolar output, select OUTIP
(OUTQP) as the output and ground OUTIN (OUTQN) to
GND. Driving the MAX5878 single-ended is not recommended since additional noise and distortion will
be added.
The distortion performance of the DAC depends on the
load impedance. The MAX5878 is optimized for 50Ω
differential double termination. It can be used with a
transformer output as shown in Figure 7 or just one 25Ω
resistor from each output to ground and one 50Ω resis-
tor between the outputs (Figure 8). This produces a fullscale output power of up to -2dBm, depending on the
output current setting. Higher termination impedance
can be used at the cost of degraded distortion performance and increased output noise voltage.
Grounding, Bypassing, and Power-
Supply Considerations
Grounding and power-supply decoupling can strongly
influence the MAX5878 performance. Unwanted digital
crosstalk couples through the input, reference, power
supply, and ground connections, and affects dynamic
performance. High-speed, high-frequency applications
require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5878 dynamic performance.
Use a multilayer printed circuit (PC) board with separate ground and power-supply planes. Run high-speed
signals on lines directly above the ground plane. Keep
digital signals as far away from sensitive analog inputs
and outputs, reference input sense lines, commonmode input, and clock inputs as practical. Use a symmetric design of clock input and the analog output lines
to minimize 2nd-order harmonic distortion components,
thus optimizing the DAC’s dynamic performance. Keep
digital signal paths short and run lengths matched to
avoid propagation delay and data skew mismatches.
The MAX5878 requires five separate power-supply
inputs for analog (AV
DD1.8
and AV
DD3.3
), digital
(DV
DD1.8
and DV
DD3.3
), and clock (AV
CLK
) circuitry. All
power-supply pins must be connected to their proper
supply. Decouple each AVDD, DVDD,and AV
CLK
input
pin with a separate 0.1µF capacitor as close to the
device as possible with the shortest possible connection to the ground plane (Figure 9). Minimize the analog
and digital load capacitances for optimized operation.
Decouple all three power-supply voltages at the point
they enter the PC board with tantalum or electrolytic
MAX5878
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
T1, 1:1
T2, 1:1
GND
50Ω
100Ω
50Ω
V
OUT
, SINGLE-ENDED
Figure 7. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
16 ______________________________________________________________________________________
capacitors. Ferrite beads with additional decoupling
capacitors forming a pi-network could also improve performance.
The analog and digital power-supply inputs AV
DD3.3
,
AV
CLK
, and DV
DD3.3
allow a +3.135V to +3.465V supply voltage range. The analog and digital power-supply
inputs AV
DD1.8
and DV
DD1.8
allow a +1.71V to +1.89V
supply voltage range.
The MAX5878 is packaged in a 68-pin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and optimized DAC AC performance.
The EP enables the use of necessary grounding techniques to ensure highest performance operation.
Thermal efficiency is not the key factor, since the
MAX5878 features low-power operation. The exposed
pad ensures a solid ground connection between the
DAC and the PC board’s ground layer.
The data converter die attaches to an EP lead frame with
the back of this frame exposed at the package bottom
surface, facing the PC board side of the package. This
allows for a solid attachment of the package to the PC
board with standard infrared reflow (IR) soldering techniques. A specially created land pattern on the PC board,
matching the size of the EP (6mm x 6mm), ensures the
proper attachment and grounding of the DAC. Designing
vias into the land area and implementing large ground
planes in the PC board design allow for the highest performance operation of the DAC. Use an array of at least 4
x 4 vias (≤0.3mm diameter per via hole and 1.2mm pitch
between via holes) for this 68-pin QFN-EP package.
Connect the MAX5878 exposed paddle to GND. Vias
connect the land pattern to internal or external copper
planes. Use as many vias as possible to the ground
plane to minimize inductance.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer function, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees a
monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
MAX5878
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
GND
25Ω
50Ω
25Ω
OUTP
OUTN
Figure 8. Differential Output Configuration
MAX5878
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
0.1µF
AV
DD1.8
DV
DD1.8
0.1µF
0.1µF 0.1µF
AV
DD3.3
DV
DD3.3
0.1µF
AV
CLK
BYPASSING—DAC LEVEL
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 9. Recommended Power-Supply Decoupling and
Bypassing Circuitry
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
______________________________________________________________________________________ 17
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
SNR
dB
= 6.02dBx N + 1.76
dB
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS
value of their next-largest distortion component. SFDR
is usually measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or to
Nyquist.
Two-/Four-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone; 2nd-order IMD products usually fall at fre-
quencies that digital filtering easily removes. Therefore,
they are not as critical as 3rd-order IMDs. The two-tone
IMD performance of the MAX5878 is tested with the two
individual output tone levels set to at least -6dBFS and
the four-tone performance was tested according to the
GSM model at an output frequency of 16MHz and amplitude of -12dBFS.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband codedivision multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impulse
is usually specified in pV•s.
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
68L QFN.EPS
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
C
1
2
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
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