MAXIM MAX5877 Technical data

General Description

The MAX5877 is an advanced 14-bit, 250Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 75dBc spurious-free dynamic range (SFDR) at f

OUT

= 16MHz and supports update rates of

250Msps, with a power dissipation of only 287mW. The MAX5877 utilizes a current-steering architecture

that supports a 2mA to 20mA full-scale output current range, and allows a 0.1V

P-P

to 1V

P-P

differential output voltage swing. The device features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy.

The clock inputs of the MAX5877 accept both LVDS and LVPECL-compatible voltage levels. The device features an interleaved data input that allows a single LVDS bus to support both DACs. The MAX5877 is available in a 68-pin QFN package with an exposed pad (EP) and is specified for the extended temperature range (-40°C to +85°C).

Refer to the MAX5876 and MAX5878 data sheets for pin-compatible 12-bit and 16-bit versions of the MAX5877, respectively. Refer to the MAX5874 data sheet for a CMOS-compatible version of the MAX5877.

Applications

Base Stations: Single/Multicarrier UMTS, CDMA, GSM Communications: Fixed Broadband Wireless Access,

Point-to-Point Microwave Direct Digital Synthesis (DDS) Cable Modem Termination Systems (CMTS) Automated Test Equipment (ATE) Instrumentation

Features

♦ 250Msps Output Update Rate ♦ Noise Spectral Density = -160dBFS/Hz

at f

OUT

= 16MHz

♦ Excellent SFDR and IMD Performance

SFDR = 75dBc at f

OUT

= 16MHz (to Nyquist)

SFDR = 71dBc at f

OUT

= 80MHz (to Nyquist)

IMD = -87dBc at f

OUT

= 10MHz

IMD = -73dBc at f

OUT

= 80MHz

♦ ACLR = 75dB at f

OUT

= 61MHz

♦ 2mA to 20mA Full-Scale Output Current ♦ LVDS-Compatible Digital and Clock Inputs ♦ On-Chip +1.20V Bandgap Reference ♦ Low 287mW Power Dissipation ♦ Compact 68-Pin QFN-EP Package (10mm x 10mm) ♦ Evaluation Kit Available (MAX5878EVKIT)

MAX5877

14-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

19-3632; Rev 2; 3/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad. + = Lead-free package. D = Dry pack.

EVALUATION KIT

AVAILABLE

PART

TEMP RANGE

PIN-

PKG

CODE

MAX5877EGK-D

G6800-4

MAX5877EGK+D

G6800-4

Selector Guide

PART

RESOLUTION

(BITS)

UPDATE

LOGIC

INPUTS

MAX5873 12 200 CMOS

MAX5874 14 200 CMOS

MAX5875 16 200 CMOS

MAX5876 12 250 LVDS

MAX5877 14 250 LVDS

MAX5878 16 250 LVDS

5859606162 5455565763

DD3.3

DD1.8

B5N

QFN

TOP VIEW

B5P

DD1.8

B6N

B6P

B7N

B7P

B8N

B8P

B9N

5253

B9P

B10N

DACREF

DD3.3

GND

DD3.3

OUTQP

OUTQN

GND

OUTIP

OUTIN

DD3.3

GND

DD3.3

B12P

B13N

B13P

SELIQN

SELIQP

XORP

XORN

TORB

CLKP

37 CLKN

GND

CLK

GND

N.C.

REFIO

GND

DD3.3

GND

B0N

B0P

B1N

B1P

48 B12N

B2N

B4P

656667

B3N

B3P

B4N

B2P

2322212019 2726252418 2928 323130

GND

DD1.8

3433

B11N

B11P

51 B10P

FSADJ 17

MAX5877

PACKAGE

-40°C to +85°C 68 QFN-EP*

RATE (Msps)

MAX5877

14-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DD1.8

, DV

DD1.8

to GND, DACREF...................-0.3V to +2.16V

DD3.3

, DV

DD3.3

, AV

CLK

to GND, DACREF........-0.3V to +3.9V

REFIO, FSADJ to

GND, DACREF..................................-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP,

OUTQN to GND, DACREF...................-1V to (AV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

CLK

+ 0.3V)

B13P/B13N–B0P/B0N, XORN, XORP, SELIQN,

SELIQP to GND, DACREF ...................-0.3V to (DV

DD1.8

+ 0.3V)

TORB, PD to GND, DACREF ...............-0.3V to (DV

DD3.3

+ 0.3V)

Continuous Power Dissipation (T

= +70°C) 68-Pin QFN-EP

(derate 41.7mW/°C above +70°C) (Note 1)............3333.3mW

Thermal Resistance

θJA(Note 1)...................................+24°C/W

Operating Temperature Range ......................... -40°C to +85°C

Junction Temperature .................................................... +150°C

Storage Temperature Range ........................... -60°C to +150°C

Lead Temperature (soldering, 10s) ............................... +300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution 14 Bits

Integral Nonlinearity INL Measured differentially

LSB

Differential Nonlinearity DNL Measured differentially

LSB

Offset Error OS

%FS

Offset-Drift Tempco

ppm/°C

Full-Scale Gain Error GE

External reference

%FS

Internal reference

Gain-Drift Tempco

External reference

ppm/°C

Full-Scale Output Current

(Note 3) 2 20 mA

Output Compliance Single-ended

Output Resistance R

OUT

1MΩ

Output Capacitance C

OUT

5pF

DYNAMIC PERFORMANCE

Clock Frequency f

CLK

MHz

Output Update Rate f

DACfDAC

= f

CLK

/ 2 1

Msps

DAC

= 150MHz f

OUT

= 16MHz, -12dBFS

Noise Spectral Density

DAC

= 250MHz f

OUT

= 80MHz, -12dBFS

dBFS/

ELECTRICAL CHARACTERISTICS

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

= +25°C.) (Note 2)

Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.

±0.5

±0.2

-0.025 ±0.001 +0.025

±10

-4.6 -0.6 +4.6

±100

±50

OUTFS

-0.5 +1.1

-160

-157

500

250

MAX5877

14-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

OUT

= 1MHz, 0dBFS 98

OUT

= 1MHz, -6dBFS 86

OUT

= 1MHz, -12dBFS 78

OUT

= 10MHz, -12dBFS 77

DAC

= 100MHz

OUT

= 30MHz, -12dBFS 78

OUT

= 10MHz, -12dBFS 75

OUT

= 16MHz, -12dBFS 66 75

OUT

= 50MHz, -12dBFS 74

DAC

= 200MHz

OUT

= 80MHz, -12dBFS 71

OUT

= 10MHz, -12dBFS 74

OUT

= 50MHz, -12dBFS 72

OUT

= 80MHz, -12dBFS 71

Spurious-Free Dynamic Range to Nyquist

SFDR

DAC

= 250MHz

dBc

Spurious-Free Dynamic Range, 25MHz Bandwidth

SFDR f

DAC

= 150MHz f

OUT

= 16MHz, -12dBFS 80

dBc

DAC

= 100MHz

OUT1

= 9MHz, -7dBFS;

OUT2

= 10MHz, -7dBFS

-87

Two-Tone IMD

DAC

= 200MHz

OUT1

= 79MHz, -7dBFS;

OUT2

= 80MHz, -7dBFS

-73

dBc

Four-Tone IMD, 1MHz

Frequency Spacing, GSM Model

DAC

= 150MHz f

OUT

= 16MHz, -12dBFS -94

dBc

Adjacent Channel Leakage Power Ratio 3.84MHz Bandwidth, W-CDMA Model

ACLR

DAC

184.32MHz

OUT

= 61.44MHz 75 dB

Output Bandwidth

(Note 4)

MHz

INTER-DAC CHARACTERISTICS

OUT

= DC - 80MHz

Gain Matching

OUT

= DC

Gain-Matching Tempco

ppm/°C

Phase Matching

OUT

= 60MHz

D egr ees

Phase-Matching Tempco

OUT

= 60MHz

D eg r ees/

°C

Channel-to-Channel Crosstalk f

DAC

= 200Msps, f

OUT

= 50MHz, 0dBFS 90 dB

REFERENCE

Internal Reference Voltage Range

1.2

SYMBOL

MIN TYP MAX

TTIMD

FTIMD

= 100MHz, -12dBFS

OUT

-1dB

∆Gain

∆Gain/°C ±20

-0.25 +0.01 +0.25

∆Phase

∆Phase/°C

REFIO

1.14

240

±0.2

±0.25

±0.002

1.26

MAX5877

14-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

= +25°C.) (Note 2)

PARAMETER

CONDITIONS

UNITS

Reference Input Compliance Range

Reference Input Resistance

10 kΩ

Reference Voltage Drift

ppm/°C

ANALOG OUTPUT TIMING (See Figure 4)

Output Fall Time t

FALL

90% to 10% (Note 5) 0.7 ns

Output Rise Time t

RISE

10% to 90% (Note 5) 0.7 ns

Output-Voltage Settling Time

Output settles to 0.025% FS (Note 5) 14 ns

Output Propagation Delay t

Excluding data latency (Note 5) 1.1 ns

Glitch Impulse Measured differentially 1

pV•s

OUTFS

= 2mA 30

Output Noise n

OUT

OUTFS

= 20mA 30

pA/√Hz

TIMING CHARACTERISTICS

Data to Clock Setup Time

Referenced to rising edge of clock (Note 6)

Data to Clock Hold Time

Referenced to rising edge of clock (Note 6) 2.0 ns

Latency to I output 9

Data Latency

Latency to Q output 8

Clock

Cycles

Minimum Clock Pulse-Width High

CLKP, CLKN 0.9 ns

Minimum Clock Pulse-Width Low

CLKP, CLKN 0.9 ns

LVDS LOGIC INPUTS (B13P/B13N–B0P/B0N, XORN, XORP, SELIQN, SELIQP)

Differential Input-Logic High V

Differential Input-Logic Low V

Common-Mode Voltage Range V

CMR

Differential Input Resistance R

(Note 7)

Ω

Input Capacitance C

2.5 pF

CMOS LOGIC INPUTS (PD, TORB)

Input-Logic High V

0.7 x V

Input-Logic Low V

0.3 x V

Input Leakage Current I

-20 1

µA

PD, TORB Internal Pulldown Resistance

= V

TORB

= 3.3V 1.5 MΩ

Input Capacitance C

2.5 pF

CLOCK INPUTS (CLKP, CLKN)

Sine wave

Differential Input Voltage Swing

Square wave

P-P

SYMBOL

MIN TYP MAX

REFIOCR

REFIO

TCO

SETTLE

REF

SETUP

HOLD

0.125 1.260

±25

-1.2

-100

1.125 1.375

110

DD3.3

> 1.5

> 0.5

100

DD3.3

+20

MAX5877

14-Bit, 250Msps, High-Dynamic-Performance,

Dual DAC with LVDS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, GND = 0, f

CLK

= 2 x f

DAC

, external reference V

REFIO

= +1.25V, out-

put load 50Ω double-terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values

are at T

= +25°C.) (Note 2)

Note 2: Specifications at T

≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design.

Note 3: Nominal full-scale current I

OUTFS

= 32 x I

REF

Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5877. Note 5: Parameter measured single-ended into a 50Ω termination resistor. Note 6: Not production tested. Guaranteed by design. Note 7: No termination resistance between XORP and XORN. Note 8: A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance. Note 9: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

PARAMETER

CONDITIONS

UNITS

Differential Input Slew Rate

(Note 8)

V/µs

External Common-Mode Voltage Range

COM

±0.3

Input Resistance R

CLK

5kΩ

Input Capacitance C

CLK

2.5 pF

POWER SUPPLIES

3.3

Analog Supply Voltage Range

1.8

3.3

Digital Supply Voltage Range

1.8

Clock Supply Voltage Range

3.3

DAC

= 250Msps, f

OUT

= 16MHz 52 58 mA

Power-down 1 µA

DAC

= 250Msps, f

OUT

= 16MHz 30 36 mA

Analog Supply Current

Power-down 1 µA

DAC

= 250Msps, f

OUT

= 16MHz 0.2 1 mA

Power-down 1 µA

DAC

= 250Msps, f

OUT

= 16MHz 34 40 mA

Digital Supply Current

Power-down 4 µA

DAC

= 250Msps, f

OUT

= 16MHz

Power Dissipation P

DISS

Power-down 16 µW

Power-Supply Rejection Ratio PSRR

DD3.3

= AV

CLK

= DV

DD3.3

= +3.3V ±5%

(Notes 8, 9)

%FS/V

SYMBOL

CLK

DD3.3

DD1.8

DD3.3

DD1.8

CLK

AVDD3.3

+ I

AVCLK

AVDD1.8

DVDD3.3

MIN TYP MAX

>100

CLK

3.135

1.710

3.135

1.710

3.135

/ 2

3.465

1.890

3.465

1.890

3.465

DVDD1.8

287 331

-0.1 +0.1

MAX5877

14-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

6 _______________________________________________________________________________________

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

DAC

= 50Msps)

MAX5877 toc01

OUT

(MHz)

SFDR (dBc)

2015105

100

025

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

DAC

= 100Msps)

MAX5877 toc02

OUT

(MHz)

SFDR (dBc)

40302010

100

050

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

DAC

= 150Msps)

MAX5877 toc03

OUT

(MHz)

SFDR (dBc)

60453015

100

075

-12dBFS

-6dBFS

0dBFS

Typical Operating Characteristics

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= +3.3V, AV

DD1.8

= DV

DD1.8

= +1.8V, external reference, V

REFIO

= +1.25V, RL = 50Ω double-terminated,

OUTFS

= 20mA, TA= +25°C, unless otherwise noted.)

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

DAC

= 200Msps)

MAX5877 toc04

OUT

(MHz)

SFDR (dBc)

80604020

100

0100

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

DAC

= 250Msps)

MAX5877 toc05

OUT

(MHz)

SFDR (dBc)

100755025

100

0125

-12dBFS

-6dBFS

0dBFS

TWO-TONE IMD vs. OUTPUT FREQUENCY

(1MHz CARRIER SPACING, f

DAC

= 100Msps)

MAX5877 toc06

OUT

(MHz)

TWO-TONE IMD (dBc)

353025201510

-90

-85

-100

-80

-95

540

-12dBFS

-6dBFS

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