MAXIM MAX5873 Technical data

General Description

The MAX5873 is an advanced 12-bit, 200Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from 3.3V and

1.8V supplies, this dual DAC offers exceptional dynamic performance such as 78dBc spurious-free dynamic range (SFDR) at f

OUT

= 16MHz and supports update rates of

200Msps, with a power dissipation of only 255mW. The MAX5873 utilizes a current-steering architecture

that supports a 2mA to 20mA full-scale output current range, and allows a 0.1V

P-P

to 1V

P-P

differential output

voltage swing. The MAX5873 features an integrated

1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy.

The digital and clock inputs of the MAX5873 accept

3.3V CMOS voltage levels. The MAX5873 features a flexible input data bus that allows for dual-port input or a single-interleaved data port. The MAX5873 is available in a 68-pin QFN package with an exposed paddle (EP) and is specified for the extended temperature range (-40°C to +85°C).

Refer to the MAX5874 and MAX5875 data sheets for pin-compatible 14-bit and 16-bit versions of the MAX5873, respectively. Refer to the MAX5876 for an LVDS-compatible version of the MAX5873.

Applications

Base Stations: Single-Carrier UMTS, CDMA, GSM

Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave

Direct Digital Synthesis (DDS)

Cable Modem Termination System (CMTS)

Automated Test Equipment (ATE)

Instrumentation

Features

♦ 200Msps Output Update Rate ♦ Noise Spectral Density = -152dBFS/Hz

at f

OUT

= 16MHz

♦ Excellent SFDR and IMD Performance

SFDR = 78dBc at f

OUT

= 16MHz (to Nyquist)

SFDR = 73dBc at f

OUT

= 80MHz (to Nyquist)

IMD = -85dBc at f

OUT

= 10MHz

IMD = -74dBc at f

OUT

= 80MHz

♦ ACLR = 74dB at f

OUT

= 61MHz

♦ 2mA to 20mA Full-Scale Output Current ♦ CMOS-Compatible Digital and Clock Inputs ♦ On-Chip 1.2V Bandgap Reference ♦ Low 255mW Power Dissipation ♦ 68-Lead QFN-EP Package ♦ Evaluation Kit Available (MAX5873EVKIT)

MAX5873

12-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

19-3446; Rev 3; 1/07

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*EP = Exposed pad. + Denotes lead-free package. D = Dry pack.

EVALUATION KIT

AVAILABLE

Selector Guide

PART

RESOLUTION

(BITS)

MAX5873 12 200 CMOS

MAX5874 14 200 CMOS

MAX5875 16 200 CMOS

MAX5876 12 250 LVDS

MAX5877 14 250 LVDS

MAX5878 16 250 LVDS

UPDATE

RATE (Msps)

LOGIC

INPUTS

PART TEMP RANGE

PINPACKAGE

MAX5873EGK-D -40°C to +85°C 68 QFN-EP* G6800-4

MAX5873EGK+D -40°C to +85°C 68 QFN-EP* G6800-4

PKG CODE

TOP VIEW

DD1.8

A10

A11

DV

N.C.

N.C.B0B1

B2

GND

DD3.3

AV

DD3.3

AV

B3

GND

5253

3433

B4

DD1.8

AV

51 B5

50

49

48 B8

47

46

45

44

43

42

41

40

39

38

37 CLKN

36

35

A4

A3

A2

A1

A0

N.C.

GND

DV

DD3.3

GND

AV

DD3.3

GND

REFIO

FSADJ 17

A6A7A8

A5

MAX5873

GND

OUTQP

GND

5859606162 5455565763

OUTIN

OUTIP

DD1.8

AV

64A9656667

2322212019 2726252418 2928 323130

GND

DD3.3

OUTQN

AV

QFN

68

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DACREF

B6

B7

B9

B10

B11

SELIQ

GND

XOR

DORI

PD

TORB

CLKP

GND

AV

CLK

MAX5873

12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AV

DD1.8

, DV

DD1.8

to GND, DACREF ................. -0.3V to +2.16V

AV

DD3.3

, DV

DD3.3

, AV

CLK

to GND, DACREF....... -0.3V to +3.9V

REFIO, FSADJ to GND, DACREF ........-0.3V to (AV

DD3.3

+ 0.3V)

OUTIP, OUTIN, OUTQP, OUTQN

to GND, DACREF .................................-1V to (AV

DD3.3

+ 0.3V)

CLKP, CLKN to GND, DACREF..............-0.3V to (AV

CLK

+ 0.3V)

A11/B11–A0/B0, XOR, SELIQ to

GND, DACREF ...................................-0.3V to (DV

DD3.3

+ 0.3V)

TORB, DORI, PD to GND, DACREF........-0.3V to (DV

DD3.3

+ 0.3

Continuous Power Dissipation (T

A

= +70°C) 68-Pin QFN-EP

(derate 41.7mW/°C above +70°C) (Note 1)...........3333.3mW

Thermal Resistance θ

JA

(Note 1)...................................+24°C/W

Operating Temperature Range ......................... -40°C to +85°C

Junction Temperature .................................................... +150°C

Storage Temperature Range ........................... -60°C to +150°C

Lead Temperature (soldering, 10s) ............................... +300°C

ELECTRICAL CHARACTERISTICS

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, GND = 0, f

CLK

= f

DAC

, external reference V

REFIO

= 1.25V, output load

50Ω double terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Note 1: Themal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution 12 Bits Integral Nonlinearity INL Measured differentially ±0.2 LSB

Differential Nonlinearity DNL Measured differentially ±0.13 LSB Offset Error OS -0.025 ±0.001 +0.025 %FS Offset-Drift Tempco ±10 ppm/°C

Full-Scale Gain Error GE

Gain-Drift Tempco

Full-Scale Output Current I

OUT

External reference ±1%FS

FS

Internal reference ±100 External reference ±50

(Note 3) 2 20 mA

Output Compliance Single-ended -0.5 +1.1 V

Output Resistance R

Output Capacitance C

OUT

DYNAMIC PERFORMANCE

Clock Frequency f

Output Update Rate f

Noise Spectral Density

CLK

DAC

f

= f

DAC

f

= f

DAC

f

= 150MHz f

DAC

f

= 200MHz f

DAC

CLK

, dual-port mode 1 200

CLK

1MΩ

5pF

1 200 MHz

/ 2, single-port mode 1 100

= 16MHz, -12dBFS -152

OUT

= 80MHz, -12dBFS -153

OUT

ppm/°C

Msps

dBFS/

Hz

MAX5873

12-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, GND = 0, f

CLK

= f

DAC

, external reference V

REFIO

= 1.25V, output load

50Ω double terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

f

= 1MHz, 0dBFS 86

OUT

f

= 1MHz, -6dBFS 82

OUT

f

= 1MHz, -12dBFS 80

OUT

f

= 10MHz, -12dBFS 85

OUT

= 30MHz, -12dBFS 80

f

OUT

f

= 10MHz, -12dBFS 80

OUT

f

= 16MHz, -12dBFS,

OUT

≥ +25oC

T

A

f

= 16MHz, -12dBFS 68 78

OUT

f

= 50MHz, -12dBFS 77

OUT

f

= 80MHz, -12dBFS 73

OUT

= 16MHz, -12dBFS 85 dBc

OUT

f

= 9MHz, -7dBFS;

OUT1

f

= 10MHz, -7dBFS

OUT2

f

= 79MHz, -7dBFS;

OUT1

f

= 80MHz, -7dBFS

OUT2

= 16MHz, -12dBFS -82 dBc

OUT

= 61.44MHz 74 dB

f

OUT

72 78

-85

-74

dBc

Spurious-Free Dynamic Range to Nyquist

Spurious-Free Dynamic Range, 25MHz Bandwidth

SFDR

SFDR f

Two-Tone IMD TTIMD

Four-Tone IMD, 1MHz Frequency Spacing, GSM Model

FTIMD f

Adjacent Channel Leakage Power Ratio 3.84MHz Bandwidth,

ACLR

W-CDMA Model

Output Bandwidth BW

-1dB

f

= 100MHz

DAC

f

= 200MHz

DAC

= 150MHz f

DAC

f

= 100MHz

DAC

f

= 200MHz

DAC

= 150MHz f

DAC

f

=

DAC

184.32MHz

(Note 4) 240 MHz

INTER-DAC CHARACTERISTICS

f

= DC - 80MHz ±0.2

Gain Matching ∆Gain

OUT

f

= DC +0.01

OUT

dB

Gain-Matching Tempco ∆Gain/°C ±20 ppm/°C Phase Matching ∆Phase f

Phase-Matching Tempco ∆Phase/°C ±0.002

Channel-to-Channel Crosstalk f

= 60MHz ±0.25 D egr ees

OUT

= 200MHz, f

CLK

= 50MHz, 0dBFS -70 dB

OUT

D eg r ees/

°C

REFERENCE

Internal Reference Voltage Range V

Reference Input Compliance Range

Reference Input Resistance R

REFIO

V

REFIOCR

REFIO

Reference Voltage Drift TCO

REF

1.14 1.2 1.26 V

0.125 1.250 V

10 kΩ

±25 ppm/°C

MAX5873

12-Bit, 200Msps, High-Dynamic-Performance, Dual DAC with CMOS Inputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, GND = 0, f

CLK

= f

DAC

, external reference V

REFIO

= 1.25V, output load

50Ω double terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ANALOG OUTPUT TIMING (See Figure 4)

Output Fall Time t

Output Rise Time t

Output-Voltage Settling Time t

Output Propagation Delay t

FALL

RISE

SETTLE

90% to 10% (Note 5) 0.7 ns

10 % to 90% (Note 5) 0.7 ns

Output settles to 0.025% FS (Note 5) 14 ns

Excluding data latency (Note 5) 1.1 ns

PD

Glitch Impulse Measured differentially 1 pV•s

I

= 2mA 30

Output Noise N

OUT

OUTFS

I

= 20mA 30

OUTFS

TIMING CHARACTERISTICS

Data to Clock Setup Time t

Data to Clock Hold Time t

Single-Port (Interleaved Mode) Data Latency

Dual-Port (Parallel Mode) Data Latency

Minimum Clock Pulse-Width High t

Minimum Clock Pulse-Width Low t

SETUP

HOLD

Referenced to rising edge of clock (Note 6) -0.6 -1.2 ns

Referenced to rising edge of clock (Note 6) 2.1 1.5 ns

Latency to I output 9

Latency to Q output 8

5.5

CLKP, CLKN 2.4 ns

CH

CLKP, CLKN 2.4 ns

CL

CMOS LOGIC INPUTS (A11/B11–A0/B0, XOR, SELIQ, PD, TORB, DORI)

Input Logic High V

Input Logic Low V

Input Leakage Current I

PD, TORB, DORI Internal Pulldown Resistance

Input Capacitance C

IH

IL

IN

= V

V

PD

IN

TORB

= V

= 3.3V 1.5 MΩ

DORI

DV

0.7 x

DD3.3

0.3 x

DV

120µA

2.5 pF

CLOCK INPUTS (CLKP, CLKN)

Differential Input Voltage Swing

Differential Input Slew Rate SR

External Common-Mode Voltage Range

V

Input Resistance R

Input Capacitance C

COM

Sine wave > 1.5

Square wave > 0.5

(Note 7) > 100 V/µs

CLK

AV

/ 2

CLK

±0.3

CLK

5kΩ

2.5 pF

POWER SUPPLIES

Analog Supply Voltage Range

AV

DD3.3

DD1.8

3.135 3.3 3.465

1.710 1.8 1.890

DD3.3

pA/√Hz

Clock

cycles

Clock

cycles

V

P-P

V

MAX5873

12-Bit, 200Msps, High-Dynamic-Performance,

Dual DAC with CMOS Inputs

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, GND = 0, f

CLK

= f

DAC

, external reference V

REFIO

= 1.25V, output load

50Ω double terminated, transformer-coupled output, I

OUTFS

= 20mA, TA = T

MIN

to T

MAX

, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

Note 2: Specifications at T

A

≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design

and characterization data.

Note 3: Nominal full-scale current I

OUTFS

= 32 x I

REF

.

Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5873. Note 5: Parameter measured single-ended into a 50Ω termination resistor. Note 6: Not production tested. Guaranteed by design and characterization data. Note 7: A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance. Note 8: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.

Typical Operating Characteristics

(AV

DD3.3

= DV

DD3.3

= AV

CLK

= 3.3V, AV

DD1.8

= DV

DD1.8

= 1.8V, external reference, V

REFIO

= 1.25V, RL = 50Ω double-terminated,

I

OUTFS

= 20mA, TA= +25°C, unless otherwise noted.)

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 50Msps)

MAX5873 toc01

f

OUT

(MHz)

SFDR (dBc)

2015105

20

40

60

80

100

0

025

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 100Msps)

MAX5873 toc02

f

OUT

(MHz)

SFDR (dBc)

40302010

20

40

60

80

100

0

050

-12dBFS

-6dBFS

0dBFS

SINGLE-TONE SFDR vs. OUTPUT

FREQUENCY (f

CLK

= 150Msps)

MAX5873 toc03

f

OUT

(MHz)

SFDR (dBc)

60453015

20

40

60

80

100

0

075

-12dBFS

-6dBFS

0dBFS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Digital Supply Voltage Range

DV

Clock Supply Voltage Range AV

I

AVDD3.3

Analog Supply Current

Digital Supply Current

+ I

I

AVDD1.8

I

DVDD3.3

I

DVDD1.8

Power Dissipation P

Power-Supply Rejection Ratio

PSRR

DD3.3

DD1.8

CLK

AVCLK Power-down 0.001

f

= 200Msps, f

DAC

f

= 200Msps, f

DAC

OUT

3.135 3.3 3.465

1.710 1.8 1.890

3.135 3.3 3.465 V

= 1MHz 52 58

= 1MHz 24 32

Power-down 0.001

f

= 200Msps, f

DAC

= 1MHz 0.5 3

OUT

Power-down 0.001

f

= 200Msps, f

DAC

= 1MHz 20 25

OUT

Power-down 0.001

f

DISS

= 200Msps, f

DAC

Power-down 14 µW

AV

DD3.3

= AV

CLK

(Notes 7, 8)

= 1MHz 255 300 mW

OUT

= DV

DD3.3

= +3.3V ±5%

-0.1 +0.1 %FS/V

V

mA