General Description
The MAX5873 is an advanced 12-bit, 200Msps, dual
digital-to-analog converter (DAC). This DAC meets the
demanding performance requirements of signal synthesis
applications found in wireless base stations and other
communications applications. Operating from 3.3V and
1.8V supplies, this dual DAC offers exceptional dynamic
performance such as 78dBc spurious-free dynamic range
(SFDR) at f
OUT
= 16MHz and supports update rates of
200Msps, with a power dissipation of only 255mW.
The MAX5873 utilizes a current-steering architecture
that supports a 2mA to 20mA full-scale output current
range, and allows a 0.1V
P-P
to 1V
P-P
differential output
voltage swing. The MAX5873 features an integrated
1.2V bandgap reference and control amplifier to ensure
high-accuracy and low-noise performance. A separate
reference input (REFIO) allows for the use of an external reference source for optimum flexibility and
improved gain accuracy.
The digital and clock inputs of the MAX5873 accept
3.3V CMOS voltage levels. The MAX5873 features a
flexible input data bus that allows for dual-port input or
a single-interleaved data port. The MAX5873 is available in a 68-pin QFN package with an exposed paddle
(EP) and is specified for the extended temperature
range (-40°C to +85°C).
Refer to the MAX5874 and MAX5875 data sheets for
pin-compatible 14-bit and 16-bit versions of the
MAX5873, respectively. Refer to the MAX5876 for an
LVDS-compatible version of the MAX5873.
Applications
Base Stations: Single-Carrier UMTS, CDMA, GSM
Communications: Fixed Broadband Wireless
Access, Point-to-Point Microwave
Direct Digital Synthesis (DDS)
Cable Modem Termination System (CMTS)
Automated Test Equipment (ATE)
Instrumentation
Features
♦ 200Msps Output Update Rate
♦ Noise Spectral Density = -152dBFS/Hz
at f
OUT
= 16MHz
♦ Excellent SFDR and IMD Performance
SFDR = 78dBc at f
OUT
= 16MHz (to Nyquist)
SFDR = 73dBc at f
OUT
= 80MHz (to Nyquist)
IMD = -85dBc at f
OUT
= 10MHz
IMD = -74dBc at f
OUT
= 80MHz
♦ ACLR = 74dB at f
OUT
= 61MHz
♦ 2mA to 20mA Full-Scale Output Current
♦ CMOS-Compatible Digital and Clock Inputs
♦ On-Chip 1.2V Bandgap Reference
♦ Low 255mW Power Dissipation
♦ 68-Lead QFN-EP Package
♦ Evaluation Kit Available (MAX5873EVKIT)
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
Ordering Information
19-3446; Rev 3; 1/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed pad.
+ Denotes lead-free package.
D = Dry pack.
EVALUATION KIT
AVAILABLE
Selector Guide
PART
RESOLUTION
(BITS)
MAX5873 12 200 CMOS
MAX5874 14 200 CMOS
MAX5875 16 200 CMOS
MAX5876 12 250 LVDS
MAX5877 14 250 LVDS
MAX5878 16 250 LVDS
UPDATE
RATE (Msps)
LOGIC
INPUTS
PART TEMP RANGE
PINPACKAGE
MAX5873EGK-D -40°C to +85°C 68 QFN-EP* G6800-4
MAX5873EGK+D -40°C to +85°C 68 QFN-EP* G6800-4
PKG
CODE
TOP VIEW
DD1.8
A10
A11
DV
N.C.
N.C.
N.C.
N.C.B0B1
B2
GND
DD3.3
AV
DD3.3
AV
B3
GND
5253
3433
B4
DD1.8
AV
51 B5
50
49
48 B8
47
46
45
44
43
42
41
40
39
38
37 CLKN
36
35
A4
A3
A2
A1
A0
N.C.
N.C.
N.C.
N.C.
GND
DV
DD3.3
GND
GND
AV
DD3.3
GND
REFIO
FSADJ 17
A6A7A8
A5
MAX5873
GND
OUTQP
GND
5859606162 5455565763
OUTIN
OUTIP
DD1.8
AV
64A9656667
2322212019 2726252418 2928 323130
GND
GND
DD3.3
DD3.3
OUTQN
AV
AV
QFN
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DACREF
B6
B7
B9
B10
B11
SELIQ
GND
XOR
DORI
PD
TORB
CLKP
GND
AV
CLK
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1.8
, DV
DD1.8
to GND, DACREF ................. -0.3V to +2.16V
AV
DD3.3
, DV
DD3.3
, AV
CLK
to GND, DACREF....... -0.3V to +3.9V
REFIO, FSADJ to GND, DACREF ........-0.3V to (AV
DD3.3
+ 0.3V)
OUTIP, OUTIN, OUTQP, OUTQN
to GND, DACREF .................................-1V to (AV
DD3.3
+ 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AV
CLK
+ 0.3V)
A11/B11–A0/B0, XOR, SELIQ to
GND, DACREF ...................................-0.3V to (DV
DD3.3
+ 0.3V)
TORB, DORI, PD to GND, DACREF........-0.3V to (DV
DD3.3
+ 0.3
Continuous Power Dissipation (T
A
= +70°C)
68-Pin QFN-EP
(derate 41.7mW/°C above +70°C) (Note 1)...........3333.3mW
Thermal Resistance θ
JA
(Note 1)...................................+24°C/W
Operating Temperature Range ......................... -40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ........................... -60°C to +150°C
Lead Temperature (soldering, 10s) ............................... +300°C
ELECTRICAL CHARACTERISTICS
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
Note 1: Themal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 12 Bits
Integral Nonlinearity INL Measured differentially ±0.2 LSB
Differential Nonlinearity DNL Measured differentially ±0.13 LSB
Offset Error OS -0.025 ±0.001 +0.025 %FS
Offset-Drift Tempco ±10 ppm/°C
Full-Scale Gain Error GE
Gain-Drift Tempco
Full-Scale Output Current I
OUT
External reference ±1%FS
FS
Internal reference ±100
External reference ±50
(Note 3) 2 20 mA
Output Compliance Single-ended -0.5 +1.1 V
Output Resistance R
Output Capacitance C
OUT
OUT
DYNAMIC PERFORMANCE
Clock Frequency f
Output Update Rate f
Noise Spectral Density
CLK
DAC
f
= f
DAC
f
= f
DAC
f
= 150MHz f
DAC
f
= 200MHz f
DAC
CLK
, dual-port mode 1 200
CLK
1MΩ
5pF
1 200 MHz
/ 2, single-port mode 1 100
= 16MHz, -12dBFS -152
OUT
= 80MHz, -12dBFS -153
OUT
ppm/°C
Msps
dBFS/
Hz
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
f
= 1MHz, 0dBFS 86
OUT
f
= 1MHz, -6dBFS 82
OUT
f
= 1MHz, -12dBFS 80
OUT
f
= 10MHz, -12dBFS 85
OUT
= 30MHz, -12dBFS 80
f
OUT
f
= 10MHz, -12dBFS 80
OUT
f
= 16MHz, -12dBFS,
OUT
≥ +25oC
T
A
f
= 16MHz, -12dBFS 68 78
OUT
f
= 50MHz, -12dBFS 77
OUT
f
= 80MHz, -12dBFS 73
OUT
= 16MHz, -12dBFS 85 dBc
OUT
f
= 9MHz, -7dBFS;
OUT1
f
= 10MHz, -7dBFS
OUT2
f
= 79MHz, -7dBFS;
OUT1
f
= 80MHz, -7dBFS
OUT2
= 16MHz, -12dBFS -82 dBc
OUT
= 61.44MHz 74 dB
f
OUT
72 78
-85
-74
dBc
dBc
Spurious-Free Dynamic Range
to Nyquist
Spurious-Free Dynamic Range,
25MHz Bandwidth
SFDR
SFDR f
Two-Tone IMD TTIMD
Four-Tone IMD, 1MHz
Frequency Spacing, GSM Model
FTIMD f
Adjacent Channel Leakage Power
Ratio 3.84MHz Bandwidth,
ACLR
W-CDMA Model
Output Bandwidth BW
-1dB
f
= 100MHz
DAC
f
= 200MHz
DAC
= 150MHz f
DAC
f
= 100MHz
DAC
f
= 200MHz
DAC
= 150MHz f
DAC
f
=
DAC
184.32MHz
(Note 4) 240 MHz
INTER-DAC CHARACTERISTICS
f
= DC - 80MHz ±0.2
Gain Matching ∆Gain
OUT
f
= DC +0.01
OUT
dB
Gain-Matching Tempco ∆Gain/°C ±20 ppm/°C
Phase Matching ∆Phase f
Phase-Matching Tempco ∆Phase/°C ±0.002
Channel-to-Channel Crosstalk f
= 60MHz ±0.25 D egr ees
OUT
= 200MHz, f
CLK
= 50MHz, 0dBFS -70 dB
OUT
D eg r ees/
°C
REFERENCE
Internal Reference Voltage Range V
Reference Input Compliance
Range
Reference Input Resistance R
REFIO
V
REFIOCR
REFIO
Reference Voltage Drift TCO
REF
1.14 1.2 1.26 V
0.125 1.250 V
10 kΩ
±25 ppm/°C
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG OUTPUT TIMING (See Figure 4)
Output Fall Time t
Output Rise Time t
Output-Voltage Settling Time t
Output Propagation Delay t
FALL
RISE
SETTLE
90% to 10% (Note 5) 0.7 ns
10 % to 90% (Note 5) 0.7 ns
Output settles to 0.025% FS (Note 5) 14 ns
Excluding data latency (Note 5) 1.1 ns
PD
Glitch Impulse Measured differentially 1 pV•s
I
= 2mA 30
Output Noise N
OUT
OUTFS
I
= 20mA 30
OUTFS
TIMING CHARACTERISTICS
Data to Clock Setup Time t
Data to Clock Hold Time t
Single-Port (Interleaved Mode)
Data Latency
Dual-Port (Parallel Mode) Data
Latency
Minimum Clock Pulse-Width High t
Minimum Clock Pulse-Width Low t
SETUP
HOLD
Referenced to rising edge of clock (Note 6) -0.6 -1.2 ns
Referenced to rising edge of clock (Note 6) 2.1 1.5 ns
Latency to I output 9
Latency to Q output 8
5.5
CLKP, CLKN 2.4 ns
CH
CLKP, CLKN 2.4 ns
CL
CMOS LOGIC INPUTS (A11/B11–A0/B0, XOR, SELIQ, PD, TORB, DORI)
Input Logic High V
Input Logic Low V
Input Leakage Current I
PD, TORB, DORI Internal
Pulldown Resistance
Input Capacitance C
IH
IL
IN
= V
V
PD
IN
TORB
= V
= 3.3V 1.5 MΩ
DORI
DV
0.7 x
DD3.3
0.3 x
DV
120µA
2.5 pF
CLOCK INPUTS (CLKP, CLKN)
Differential Input
Voltage Swing
Differential Input Slew Rate SR
External Common-Mode Voltage
Range
V
Input Resistance R
Input Capacitance C
COM
Sine wave > 1.5
Square wave > 0.5
(Note 7) > 100 V/µs
CLK
AV
/ 2
CLK
±0.3
CLK
CLK
5kΩ
2.5 pF
POWER SUPPLIES
Analog Supply Voltage Range
AV
AV
DD3.3
DD1.8
3.135 3.3 3.465
1.710 1.8 1.890
DD3.3
pA/√Hz
Clock
cycles
Clock
cycles
V
V
V
P-P
V
V
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, GND = 0, f
CLK
= f
DAC
, external reference V
REFIO
= 1.25V, output load
50Ω double terminated, transformer-coupled output, I
OUTFS
= 20mA, TA = T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
Note 2: Specifications at T
A
≥ +25°C are guaranteed by production testing. Specifications at TA< +25°C are guaranteed by design
and characterization data.
Note 3: Nominal full-scale current I
OUTFS
= 32 x I
REF
.
Note 4: This parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the MAX5873.
Note 5: Parameter measured single-ended into a 50Ω termination resistor.
Note 6: Not production tested. Guaranteed by design and characterization data.
Note 7: A differential clock input slew rate of > 100V/µs is required to achieve the specified dynamic performance.
Note 8: Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference, V
REFIO
= 1.25V, RL = 50Ω double-terminated,
I
OUTFS
= 20mA, TA= +25°C, unless otherwise noted.)
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 50Msps)
MAX5873 toc01
f
OUT
(MHz)
SFDR (dBc)
2015105
20
40
60
80
100
0
025
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 100Msps)
MAX5873 toc02
f
OUT
(MHz)
SFDR (dBc)
40302010
20
40
60
80
100
0
050
-12dBFS
-6dBFS
0dBFS
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 150Msps)
MAX5873 toc03
f
OUT
(MHz)
SFDR (dBc)
60453015
20
40
60
80
100
0
075
-12dBFS
-6dBFS
0dBFS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital Supply Voltage Range
DV
DV
Clock Supply Voltage Range AV
I
AVDD3.3
Analog Supply
Current
Digital Supply
Current
+ I
I
AVDD1.8
I
DVDD3.3
I
DVDD1.8
Power Dissipation P
Power-Supply
Rejection Ratio
PSRR
DD3.3
DD1.8
CLK
AVCLK Power-down 0.001
f
= 200Msps, f
DAC
f
= 200Msps, f
DAC
OUT
OUT
3.135 3.3 3.465
1.710 1.8 1.890
3.135 3.3 3.465 V
= 1MHz 52 58
= 1MHz 24 32
Power-down 0.001
f
= 200Msps, f
DAC
= 1MHz 0.5 3
OUT
Power-down 0.001
f
= 200Msps, f
DAC
= 1MHz 20 25
OUT
Power-down 0.001
f
DISS
= 200Msps, f
DAC
Power-down 14 µW
AV
DD3.3
= AV
CLK
(Notes 7, 8)
= 1MHz 255 300 mW
OUT
= DV
DD3.3
= +3.3V ±5%
-0.1 +0.1 %FS/V
V
mA
mA
mA
mA
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference, V
REFIO
= 1.25V, RL = 50Ω double-terminated,
I
OUTFS
= 20mA, TA= +25°C, unless otherwise noted.)
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 200Msps)
MAX5873 toc07
f
OUT
(MHz)
TWO-TONE IMD (dBc)
70605040302010
-90
-80
-70
-60
-50
-40
-100
080
-6dBFS
-12dBFS
SFDR vs. FULL-SCALE OUTPUT CURRENT
(f
CLK
= 200MHz)
MAX5873 toc08
f
OUT
(MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0 100
A
OUT
= -6dBFS
10mA
5mA
20mA
SFDR vs. TEMPERATURE
(f
CLK
= 200MHz)
MAX5873 toc09
f
OUT
(MHz)
SFDR (dBc)
80604020
75
80
85
90
70
0 100
A
OUT
= -6dBFS
TA = +85°C
TA = +25°C
TA = -40°C
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5873 toc10
DIGITAL INPUT CODE
INL (LSB)
307220481024
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-0.4
0 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5873 toc11
DIGITAL INPUT CODE
DNL (LSB)
307220481024
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-0.4
0 4096
SINGLE-TONE SFDR vs. OUTPUT
FREQUENCY (f
CLK
= 200Msps)
MAX5873 toc04
f
OUT
(MHz)
SFDR (dBc)
80604020
20
40
60
80
100
0
0100
-12dBFS
-6dBFS
0dBFS
TWO-TONE IMD vs. OUTPUT FREQUENCY
(1MHz CARRIER SPACING, f
CLK
= 100Msps)
MAX5873 toc05
f
OUT
(MHz)
TWO-TONE IMD (dBc)
353025201510
-90
-80
-70
-60
-50
-40
-100
540
-6dBFS
-12dBFS
TWO-TONE IMD (f
CLK
= 100Msps)
MAX5873 toc06
f
OUT
(MHz)
OUTPUT POWER (dBFS)
3432302826
-80
-60
-40
-20
0
-100
24 36
BW = 12MHz
2 x f
OUT1
- f
OUT2
2 x f
OUT2
- f
OUT1
f
OUT1
f
OUT1
= 29.9795MHz
f
OUT2
= 31.0049MHz
f
OUT2
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(AV
DD3.3
= DV
DD3.3
= AV
CLK
= 3.3V, AV
DD1.8
= DV
DD1.8
= 1.8V, external reference, V
REFIO
= 1.25V, RL = 50Ω double-terminated,
I
OUTFS
= 20mA, TA= +25°C, unless otherwise noted.)
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 100MHz, f
OUT
= 10MHz)
MAX5873 toc13
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
3.4353.3353.235
210
220
230
240
250
200
3.135
A
OUT
= 0dBFS
EXTERNAL REFERENCE
INTERNAL REFERENCE
FOUR-TONE POWER RATIO PLOT
(f
CLK
= 150MHz, f
CENTER
= 31.6040MHz)
MAX5873 toc14
f
OUT
(MHz)
OUTPUT POWER (dBFS)
3634323028
-80
-60
-40
-20
0
-100
26 38
BW = 12MHz
f
OUT1fOUT2fOUT3fOUT4
f
OUT1
= 29.6997MHz f
OUT3
= 32.4829MHz
f
OUT2
= 30.7251MHz f
OUT4
= 34.0210MHz
ACLR FOR WCDMA MODULATION,
TWO CARRIERS
MAX5873 toc15
3.05MHz/div
ANALOG OUTPUT POWER (dBm)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-120
f
CLK
= 184.32MHz
f
CENTER
= 30.72MHz
ACLR = 71.20dB
ACLR FOR WCDMA MODULATION,
SINGLE CARRIER
MAX5873 toc16
9.2MHz/div
ANALOG OUTPUT POWER (dBm)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
DC 92.16MHz
f
CENTER
= 30.72MHz
f
CLK
= 184.32MHz
ACLR = 76dB
WCDMA BASEBAND ACLR
MAX5873 toc17
NUMBER OF CARRIERS
ACLR (dB)
4321
65
70
75
80
85
60
ALTERNATE
ADJACENT
76.9
79.0
76.8
78.3
76.7
77.6
75.7
76.4
POWER DISSIPATION vs. CLOCK
FREQUENCY (f
280
A
= 0dBFS
OUT
260
240
220
POWER DISSIPATION (mW)
200
180
30
f
CLK
OUT
(MHz)
= 10MHz)
MAX5873 toc12
190170150130110907050
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
8 _______________________________________________________________________________________8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1–5
6–9, 57–60 N.C. No Connection. Leave floating or connect to GND.
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36, 43
A4, A3, A2,
A1, A0
GND Converter Ground
Data Bits A4–A0. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits
are not used. Connect bits A4–A0 to GND in single-port mode.
11 DV
14, 21, 22, 31,
32
16 REFIO
17 FSADJ
18 DACREF
19, 34 AV
24 OUTQN Complementary Q-DAC Output. Negative terminal for current output.
25 OUTQP Q-DAC Output. Positive terminal for current output.
28 OUTIN Complementary I-DAC Output. Negative terminal for current output.
29 OUTIP I-DAC Output. Positive terminal for current output.
35 AV
37 CLKN
38 CLKP
39 TORB
40 PD
41 DORI
AV
DD3.3
DD3.3
DD1.8
CLK
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1µF
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA fullscale output current, connect a 2kΩ resistor between FSADJ and DACREF. See Table 1.
Current-Set Resistor Return Path. For a 20mA full-scale output current, connect a 2kΩ resistor
between FSADJ and DACREF. Internally connected to GND. Do not use as a ground connection.
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1µF capacitor to GND.
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1µF
capacitor to GND.
Complementary Converter Clock Input. Negative input terminal for differential converter clock.
Internally biased to AV
Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to
/ 2.
AV
CLK
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’scomplement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format.
TORB has an internal pulldown resistor.
Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for normal
operation. PD has an internal pulldown resistor.
Dual (Parallel)/Single (Interleaved) Port Select Input. Set DORI high to configure as a dual-port
DAC. Set DORI low to configure as a single interleaved-port DAC. DORI has an internal pulldown
resistor.
CLK
/ 2.
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
_______________________________________________________________________________________ 9
Detailed Description
Architecture
The MAX5873 high-performance, 12-bit, dual currentsteering DAC (Figure 1) operates with DAC update rates
up to 200Msps. The converter consists of input registers
and a demultiplexer for single-port (interleaved) mode,
followed by a current-steering array. During operation in
interleaved mode, the input data registers demultiplex
the single-port data bus. The current-steering array generates differential full-scale currents in the 2mA to 20mA
range. An internal current-switching network, in combination with external 50Ω termination resistors, converts the
differential output currents into dual differential output
voltages with a 0.1V to 1V peak-to-peak output voltage
range. An integrated 1.2V bandgap reference, control
amplifier, and user-selectable external resistor determine
the data converter’s full-scale output range.
Reference Architecture and Operation
The MAX5873 supports operation with the internal 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, lowimpedance reference source. REFIO also serves as a
reference output when the DAC operates in internal reference mode. For stable operation with the internal reference, decouple REFIO to GND with a 1µF capacitor.
Due to its limited output drive capability, buffer REFIO
with an external amplifier when driving large
external loads.
The MAX5873’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
I
OUTFS
for the differential current outputs of the DAC.
Configured as a voltage-to-current amplifier, calculate
the output current as follows:
where I
OUTFS
is the full-scale output current of the
DAC. R
SET
(located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
OUTFS
and R
SET
selections.
Pin Description (continued)
Table 1. I
OUTFS
and R
SET
Selection
Matrix Based on a Typical 1.200V
Reference Voltage
PIN NAME FUNCTION
42 XOR
44 SELIQ
B11, B10, B9,
45–56
61 DV
62–68
— EP Exposed Pad. Must be connected to GND through a low-impedance path.
B8, B7, B6,
B5, B4, B3,
B2, B1, B0
DD1.8
A11, A10, A9
A8, A7, A6, A5
DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the
DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND.
DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct
data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ’s logic state is only valid in
single-port (interleaved) mode.
Data Bits B11–B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state
of SELIQ determines where the data bits are directed.
Digital Supply Voltage. Accepts a supply voltage range of 1.71V to 1.89V. Bypass with a 0.1µF
capacitor to GND.
Data Bits A11–A5. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits
are not used. Connect bits A11–A5 to GND in single-port mode.
I
=× ×
OUTFS
FULL-SCALE
CURRENT I
OUTFS
2 19.2k 19.1k
5 7.68k 7.5k
10 3.84k 3.83k
15 2.56k 2.55k
20 1.92k 1.91k
(mA)
V
REFIO
R
SET
CALCULATED 1% EIA STD
⎛
−32 1
⎜
⎝
R
(Ω)
SET
⎞
1
⎟
12
⎠
2
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
10 ______________________________________________________________________________________
Analog Outputs
(OUTIP, OUTIN, OUTQP, OUTQN)
Each MAX5873 DAC outputs two complementary currents (OUTIP/N, OUTQP/N) that operate in a singleended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25Ω termination resistor to ground and a
50Ω resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation.
Figure 3 displays a simplified diagram of the internal
output structure of the MAX5873.
Clock Inputs (CLKP, CLKN)
The MAX5873 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AV
CLK
) to achieve the lowest possible jitter performance. Drive the differential clock inputs from a singleended or a differential clock source. For single-ended
operation, drive CLKP with a logic source and bypass
CLKN to GND with a 0.1µF capacitor.
CLKP and CLKN are internally biased to AV
CLK
/ 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is > 5kΩ.
Data Timing Relationship
Figure 4 displays the timing relationship between digital
CMOS data, clock, and output signals. The MAX5873
features a 1.5ns hold, a -1.2ns setup, and a 1.1ns propagation delay time. A nine (eight)-clock-cycle latency
exists between CLKP/CLKN, and OUTIP/OUTIN
(OUTQP/OUTQN) when operating in single-port (interleaved) mode. In dual-port (parallel) mode, the clock
latency is 5.5 clock cycles for both channels.
Figure 1. MAX5873 High-Performance, 12-Bit, Dual Current-Steering DAC
TORB
DORI
DATA11–
DATA 0
SELIQ
AV
CLKP
CLKN
GND
XOR
CLK
DV
DD3.3
CMOS
RECEIVER
GND AV
LATCH
DV
DD1.8
LATCH
LATCH
CLK
INTERFACE
POWER-DOWN
BLOCK
PD GND
DD1.8
DECODE
DECODE
MAX5873
XOR/
XOR/
AV
DD3.3
LATCH
LATCH LATCH DAC
LATCH DAC
1.2V
REFERENCE
OUTIP
OUTIN
OUTQP
OUTQN
DACREF
REFIO
FSADJ
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 11
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB,
DORI
)
The TORB input selects between two’s-complement or
binary digital input data. Set TORB to a CMOS-logichigh level to indicate a two’s-complement input format.
Set TORB to a CMOS-logic-low level to indicate a binary input format.
The DORI input selects between a dual-port (parallel) or
single-port (interleaved) DAC. Set DORI high to configure
the MAX5873 as a dual-port DAC. Set DORI low to configure the MAX5873 as a single-port DAC. In dual-port
mode, connect SELIQ to ground.
CMOS DAC Inputs (A11/B11–A0/B0, XOR, SELIQ)
The MAX5873 latches input data on the rising edge of
the clock in a user-selectable two’s-complement or binary format. A logic-high voltage on TORB selects two’scomplement and a logic-low selects offset binary format.
The MAX5873 includes a single-ended, CMOS-compatible XOR input. Input data (all bits) are compared with the
bit applied to XOR through exclusive-OR gates. Pulling
XOR high inverts the input data. Pulling XOR low leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input and
applying decoding to XOR, the digital input data can be
decorrelated from the DAC output, allowing for the troubleshooting of possible spurious or harmonic distortion
degradation due to digital feedthrough on the printed
circuit board (PCB).
A11/B11–A0/B0, XOR, and SELIQ are latched on the rising edge of the clock. In single-port mode (DORI pulled
low) a logic-high signal on SELIQ directs the B11–B0
data onto the I-DAC inputs. A logic-low signal at SELIQ
directs data to the Q-DAC inputs. In dual-port (parallel)
mode (DORI pulled high), data on pins A11–A0 are
directed onto the Q-DAC inputs and B11–B0 are directed
onto the I-DAC inputs.
Power-Down Operation (PD)
The MAX5873 also features an active-high power-down
mode that reduces the DAC’s digital current consumption
from 21.5mA to less than 2µA and the analog current
consumption from 76mA to less than 2µA. Set PD high
to power down the MAX5873. Set PD low for normal
operation.
When powered down, the MAX5873 reduces the overall
power consumption to less than 14µW. The MAX5873
requires 10ms to wake up from power-down and enter
a fully operational state. The PD integrated pulldown
resistor activates the MAX5873 if PD is left floating.
Figure 2. Reference Architecture, Internal Reference
Configuration
Figure 3. Simplified Analog Output Structure
Table 2. DAC Output Code Table
1.2V
REFERENCE
10kΩ
REFIO
1µF
OUTIP
I
REF
= V
I
REF
REFIO
FSADJ
R
SET
DACREF
/ R
SET
CURRENT-SOURCE
ARRAY DAC
OUTIN
DIGITAL INPUT CODE
OFFSET BINARY
0000 0000 0000 1000 0000 0000 0 I
0111 1111 1111 0000 0000 0000 I
1111 1111 1111 0111 1111 1111 I
TWO’S
COMPLEMENT
OUT_P OUT_N
OUTFS
/ 2 I
OUTFS
OUTFS
OUTFS
0
/ 2
AV
DD
CURRENT
SWITCHES
CURRENT
SOURCES
I
OUT
OUTIN OUTIP
I
OUT
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
12 ______________________________________________________________________________________
Applications Information
CLK Interface
The MAX5873 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV
CLK
) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5ps
RMS
for meeting the specified noise density. For that reason, the CLKP/CLKN
input source must be designed carefully. The differential clock (CLKN and CLKP) input can be driven from a
single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
Figure 5 shows a convenient and quick way to apply a
differential signal created from a single-ended source
(e.g., HP/Agilent 8644B signal generator) and a wideband transformer. Alternatively, these inputs can be driven from a CMOS-compatible clock source; however, it is
recommended to use sinewave or AC-coupled differential
ECL/PECL drive for best dynamic performance.
Figure 4. Timing Relationships Between Clock and Input Data for (a) Dual-Port (Parallel) Mode and (b) Single-Port (Interleaved) Mode
DATA11–DATA0, XOR
CLK
DAC OUTPUT
CLK
DATA
IN
SELIQ
I OUT
I - 6
N - 1 N N + 1 N + 2
t
H
N - 4
(a) DUAL-PORT (PARALLEL) TIMING DIAGRAM
I - 4 I - 2
N - 3
I - 3
N - 6
I0 Q2I2Q1I1 I3 Q3Q0
t
t
S
H
I - 5
t
S
N - 5
t
PD
N - 2
Q OUT
Q - 6
Q - 5
t
PD
(b) SINGLE-PORT (INTERLEAVED) TIMING DIAGRAM
Q - 4
Q - 3 Q - 2
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 13
Differential Coupling Using a Wideband RF
Transformer
Use a pair of transformers (Figure 6) or a differential
amplifier configuration to convert the differential voltage
existing between OUTIP/OUTQP and OUTIN/OUTQN to
a single-ended voltage. Optimize the dynamic performance by using a differential transformer-coupled output to limit the output power to < 0dBm full scale. Pay
close attention to the transformer core saturation characteristics when selecting a transformer for the
MAX5873. Transformer core saturation can introduce
strong 2nd-order harmonic distortion especially at low
output frequencies and high signal amplitudes. For best
results, center tap the transformer to ground. When not
using a transformer, terminate each DAC output to
ground with a 25Ω resistor. Additionally, place a 50Ω
resistor between the outputs (Figure 7).
For a single-ended unipolar output, select OUTIP
(OUTQP) as the output and ground OUTIN (OUTQN) to
GND. Driving the MAX5873 single-ended is not recom-
mended since additional noise and distortion will
be added.
The distortion performance of the DAC depends on the
load impedance. The MAX5873 is optimized for 50Ω
differential double termination. It can be used with a
transformer output as shown in Figure 6 or just one 25Ω
resistor from each output to ground and one 50Ω resistor between the outputs (Figure 7). This produces a fullscale output power of up to -2dBm, depending on the
output current setting. Higher termination impedance
can be used at the cost of degraded distortion performance and increased output noise voltage.
Grounding, Bypassing, and Power-
Supply Considerations
Grounding and power-supply decoupling can strongly
influence the MAX5873 performance. Unwanted digital
crosstalk couples through the input, reference, power
supply, and ground connections, and affects dynamic
performance. High-speed, high-frequency applications
require closely followed proper grounding and powersupply decoupling. These techniques reduce EMI and
internal crosstalk that can significantly affect the
MAX5873 dynamic performance.
Use a multilayer PCB with separate ground and powersupply planes. Run high-speed signals on lines directly
above the ground plane. Keep digital signals as far
away from sensitive analog inputs and outputs, reference input sense lines, common-mode input, and clock
inputs as practical. Use a symmetric design of clock
input and the analog output lines to minimize 2nd-order
harmonic distortion components, thus optimizing the
DAC’s dynamic performance. Keep digital signal paths
short and run lengths matched to avoid propagation
delay and data skew mismatches.
Figure 5. Differential Clock-Signal Generation
Figure 6. Differential-to-Single-Ended Conversion Using a Wideband RF Transformer
WIDEBAND RF TRANSFORMER
PERFORMS SINGLE-ENDED-TO-
DIFFERENTIAL CONVERSION
SINGLE-ENDED
CLOCK SOURCE
1:1
GND
25Ω
25Ω
0.1µF
CLKP
TO DAC
0.1µF
CLKN
50Ω
DATA11–DATA0
MAX5873
12
GND
OUTIP/OUTQP
OUTIN/OUTQN
100Ω
T1, 1:1
50Ω
V
, SINGLE-ENDED
T2, 1:1
WIDEBAND RF TRANSFORMER T2 PERFORMS THE
DIFFERENTIAL-TO-SINGLE-ENDED CONVERSION
OUT
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
14 ______________________________________________________________________________________
The MAX5873 requires five separate power-supply inputs
for analog (AV
DD1.8
and AV
DD3.3
), digital (DV
DD1.8
and
DV
DD3.3
), and clock (AV
CLK
) circuitry. Decouple each
AVDD, DVDD, and AV
CLK
input pin with a separate 0.1µF
capacitor as close to the device as possible with the
shortest possible connection to the ground plane (Figure
8). Minimize the analog and digital load capacitances for
optimized operation. Decouple all three power-supply
voltages at the point they enter the PCB with tantalum or
electrolytic capacitors. Ferrite beads with additional
decoupling capacitors forming a pi-network could also
improve performance.
The analog and digital power-supply inputs AV
DD3.3
,
AV
CLK
, and DV
DD3.3
allow a 3.135V to 3.465V supply
voltage range. The analog and digital power-supply
inputs AV
DD1.8
and DV
DD1.8
allow a 1.71V to 1.89V
supply voltage range.
The MAX5873 is packaged in a 68-pin QFN-EP package, providing greater design flexibility, increased thermal efficiency, and optimized DAC AC performance.
The EP enables the use of necessary grounding techniques to ensure highest performance operation.
Thermal efficiency is not the key factor, since the
MAX5873 features low-power operation. The exposed
pad ensures a solid ground connection between the
DAC and the PCB’s ground layer.
The data converter die attaches to an EP lead frame with
the back of this frame exposed at the package bottom
surface, facing the PCB side of the package. This allows
for a solid attachment of the package to the PCB with
standard infrared reflow (IR) soldering techniques. A specially created land pattern on the PCB, matching the size
of the EP (6mm x 6mm), ensures the proper attachment
and grounding of the DAC. Refer to the MAX5873 EV kit
data sheet. Designing vias into the land area and imple-
menting large ground planes in the PCB design allow
for the highest performance operation of the DAC. Use an
array of at least 4 x 4 vias (≤ 0.3mm diameter per via hole
and 1.2mm pitch between via holes) for this 68-pin QFNEP package. Connect the MAX5873 exposed paddle to
GND. Vias connect the land pattern to internal or external
copper planes. Use as many vias as possible to the
ground plane to minimize inductance.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer function, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees a
monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Figure 7. Differential Output Configuration
Figure 8. Recommended Power-Supply Decoupling and
Bypassing Circuitry
25Ω
DATA11–DATA0
MAX5873
12
GND
OUTIP/OUTQP
50Ω
OUTIN/OUTQN
25Ω
OUTP
OUTN
BYPASSING—DAC LEVEL
DD1.8
DD1.8
AV
DD3.3
0.1µF
0.1µF 0.1µF
MAX5873
DV
DD3.3
0.1µF
AV
CLK
OUTIP/OUTQP
OUTIN/OUTQN
AV
DATA11–DATA0
12
DV
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
0.1µF
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________ 15
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
SNR = 6.02 x N + 1.76
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantization noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal components) to the RMS value of
their next-largest distortion component. SFDR is usually
measured in dBc and with respect to the carrier frequency amplitude or in dBFS with respect to the DAC’s fullscale range. Depending on its test condition, SFDR is
observed within a predefined window or to Nyquist.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband codedivision multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011...111 to 100...000. The glitch
impulse is found by integrating the voltage of the glitch
at the midscale transition over time. The glitch impulse
is usually specified in pV•s.
MAX5873
12-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
Revision History
Pages changed at Rev 3: 1–16
68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
21-0122
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
21-0122
C
C
1
2
1
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