MAXIM MAX5858A Technical data

General Description

The MAX5858A dual, 10-bit, 300Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The MAX5858A
integrates two 10-bit DAC cores, 4x/2x/1x programmable
digital interpolation filters, phase-lock loop (PLL) clock
multiplier, and a 1.24V reference. The MAX5858A sup­ports single-ended and differential modes of operation.
The MAX5858A dynamic performance is maintained over
the entire power-supply operating range of 2.7V to 3.3V.
The analog outputs support a compliance voltage of

-1.0V to +1.25V.

The 4x/2x/1x programmable interpolation filters feature
excellent passband distortion and noise performance.
Interpolating filters minimize the design complexity of
analog reconstruction filters while lowering the data bus
and the clock speeds of the digital interface. The PLL
multiplier generates all internal, synchronized high­speed clock signals for interpolating filter operation and
DAC core conversion. The internal PLL helps minimize
system complexity and lower cost. To reduce the I/O pin
count, the DAC can also operate in interleave data
mode. This allows the MAX5858A to be updated on a
single 10-bit bus.

The MAX5858A features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on­chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref­erence can be disabled and an external reference can
be applied for high-accuracy applications.

The MAX5858A features full-scale current outputs of
2mA to 20mA and operates from a 2.7V to 3.3V single
supply. The DAC supports three modes of power-con­trol operation: normal, low-power standby, and com­plete power-down. In power-down mode, the operating
current is reduced to 1µA.

The MAX5858A is packaged in a 48-pin TQFP with
exposed paddle (EP) for enhanced thermal dissipation
and is specified for the extended (-40°C to +85°C) opera­ting temperature range.

Applications

Communications

SatCom, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links

Wireless Base Stations

Direct Digital Synthesis

Instrumentation/ATE

Features

♦ 10-Bit Resolution, Dual DAC

♦ 300Msps Update Rate

♦ Integrated 4x/2x/1x Interpolating Filters

♦ Internal PLL Multiplier

♦ 2.7V to 3.3V Single Supply

♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

73dBc SFDR at f

OUT

= 20MHz

UMTS ACLR = 63dB at f

OUT

= 30.7MHz

♦ Programmable Channel Gain Matching

♦ Integrated 1.24V Low-Noise Bandgap Reference

♦ Single-Resistor Gain Control

♦ Interleave Data Mode

♦ Differential Clock Input Modes

♦ EV Kit Available—MAX5858AEVKit

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x

Interpolation Filters and PLL

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2999; Rev 0; 10/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration

*EP = Exposed paddle.

PART TEMP RANGE PIN-PACKAGE

MAX5858AECM -40°C to +85°C 48 TQFP-EP*

DD

DD

AV

DV

DGND

OUTPA

48 47 46 45 44 43EP42 41 40 39 38 37

1

DA9/PD

DA8/DACEN

DA7/F2EN
DA6/F1EN

2
3
4
5

DA5/G3

6

DGND
DV

7

DD

8

DA4/G2

9

DA3/G1

10

DA2/G0

DA1

11
12

DA0

13 14 15 16 17 18 19 20 21 22 23 24

DB9

NOTE: EXPOSED PADDLE CONNECTED TO GND.

DB8

MAX5858A

DB7

DB6

TQFP-EP

OUTNA

DB5

DV

AGND

DD

OUTPB

DGND

OUTNB

CLK

AV

IDE

DD

N.C.

REFR

N.C.

REFO

36
35

REN

34

PLLF

33

PGND
PV

32

DD

31

CLKXN

30

CLKXP
PLLEN

29
28

LOCK

27

CW

26

DB0

DB1

25

DB2

DB3

DB4

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

V

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C

guaranteed by production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDD, PVDDto AGND, DGND, PGND ..........-0.3V to +4V

DA9–DA0, DB9–DB0, CW, REN, PLLF, PLLEN to AGND,

DGND, PGND........................................................-0.3V to +4V

IDE to AGND, DGND, PGND ...................-0.3V to (DV

DD

+ 0.3V)

CLKXN, CLKXP to PGND .........................................-0.3V to +4V

OUTP_, OUTN_ to AGND.......................-1.25V to (AV

DD

+ 0.3V)

CLK, LOCK to DGND...............................-0.3V to (DVDD+ 0.3V)

REFR, REFO to AGND .............................-0.3V to (AV

DD

+ 0.3V)

AGND to DGND, DGND to PGND,

AGND to PGND ..................................................-0.3V to +0.3V

Maximum Current into Any Pin

(excluding power supplies) ............................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ....2.899W

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

STATIC PERFORMANCE

Resolution 10 Bits

Integral Nonlinearity INL RL = 0 -1.25 ±0.5 +1.25 LSB

Differential Nonlinearity DNL Guaranteed monotonic, RL = 0 -0.75 ±0.25 +0.75 LSB

Offset Error V

Gain Error (See Gain Error
Parameter Definitions Section)

DYNAMIC PERFORMANCE

Maximum DAC Update Rate f

Glitch Impulse 5 pV-s

Spurious-Free Dynamic Range to
Input Update Rate Nyquist

Spurious-Free Dynamic Range
Within a Window

Multitone Power Ratio, 8 Tones,
~300kHz Spacing

Adjacent Channel Leakage Ratio
with UMTS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OS

GE

DAC

SFDR

SFDR

MTPR f

ACLR f

Internal reference (Note 1) -10 ±1.6 +11

External reference -8 ±1.2 +8

4x/2x interpolation modes 300 Msps

f

= 165Msps

DAC

f

= 300Msps,

DAC

2x interpolation

f

= 200Msps, 2x interpolation,

DAC

f

= 40MHz, span = 20MHz

OUT

f

= 165Msps, f

DAC

span = 4MHz

= 165Msps, f

DAC

=122.88Msps, f

DAC

f

= 5MHz,

OUT

≥ +25°C

T

A

f

= 20MHz 73

OUT

f

= 50MHz 66

OUT

= 70MHz 65

f

OUT

f

= 5MHz 76

OUT

f

= 40MHz 73

OUT

f

= 60MHz 72

OUT

= 5MHz,

OUT

= 20MHz 76 dBc

OUT

= 30.72MHz 63 dB

OUT

-0.5 ±0.1 +0.5 LSB

68 76

85

76.5 85

%

dBc

dBc

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

V

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C

guaranteed by production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Total Harmonic Distortion to
Nyquist

Noise Spectral Density n

Output Channel-to-Channel
Isolation

Gain Mismatch Between
Channels

Phase Mismatch Between
Channels

Wideband Output Noise 50 pA/√Hz

ANALOG OUTPUT

Full-Scale Output Current Range I

Output Voltage Compliance
Range

Output Leakage Current Power-down or standby mode -5 +5 µA

REFERENCE

Reference Output Voltage V

Output-Voltage Temperature Drift TCV

Reference Output Drive
Capability

Reference Input Voltage Range REN = AV

Reference Supply Rejection 0.2 mV/V

Current Gain IFS/I

INTERPOLATION FILTER (2x interpolation)

Passband Width

Stopband Rejection

Group Delay 18

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

THD f

D

FS

REF0

REF

REF

f

/

OUT

0.5f

DAC

= 165Msps, f

DAC

f

= 165Msps, f

DAC

= 5MHz 80 dB

f

OUT

f

= 5MHz ±0.05 dB

OUT

f

= 5MHz ±0.15 Degrees

OUT

REN = AGND 1.14 1.24 1.34 V

DD

-0.005dB 0.398

-0.01dB 0.402

-0.1dB 0.419

-3dB 0.478

0.604f

0.600f

0.594f

0.532f

/ 2 to 1.396f

DAC

/ 2 to 1.400f

DAC

/ 2 to 1.406f

DAC

/ 2 to 1.468f

DAC

= 5MHz -72 dBc

OUT

= 5MHz -143 dBm/Hz

OUT

/ 2 74

DAC

/ 2 62

DAC

/ 2 53

DAC

/ 2 14

DAC

220mA

-1.0 +1.25 V

±50 ppm/°C

50 µA

0.10 1.32 V

32 mA/mA

MHz/

MHz

dB

Data

clock

cycles

Impulse Response Duration 22

Data

clock

cycles

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

V

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C

guaranteed by production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

INTERPOLATION FILTER (4x interpolation)

Passband Width

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Stopband Rejection

Group Delay 22

Impulse Response Duration 27

LOGIC INPUTS (IDE, CW, REN, DA9–DA0, DB9–DB0, PLLEN)

Digital Input-Voltage High V

Digital Input-Voltage Low V

Digital Input-Current High I

Digital Input-Current Low I

Digital Input Capacitance C

DIGITAL OUTPUTS (CLK, LOCK)

Digital Output-Voltage High V

Digital Output-Voltage Low V

DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN)

Clock Input Internal Bias PV

Differential Clock Input Swing 0.5 V
Clock Input Impedance Single-ended clock drive 5 kΩ

TIMING CHARACTERISTICS

Input Data Rate f

Clock Frequency at CLK Input f

-0.005dB 0.200

f

0.5f

OUT

OH

DATA

CLK

-0.01dB 0.201

/

DAC

-0.1dB 0.210

-3dB 0.239

0.302f

0.300f

0.297f

0.266f

IH

IL

VIH = 2V -1 +1 µA

H

VIL = 0.8V -1 +1 µA

IL

IN

I

SOURCE

I

OL

SINK

No interpolation 165

2x interpolation

4x interpolation

No interpolation, PLL enabled 165

2x interpolation, PLL enabled 75 150

4x interpolation, PLL enabled 37.5 75

/ 2 to 1.698f

DAC

/ 2 to 1.700f

DAC

/ 2 to 1.703 f

DAC

/ 2 to 1.734f

DAC

= 0.5mA, Figure 1

= 0.5mA, Figure 1

/ 2 74

DAC

/ 2 63

DAC

/ 2 53

DAC

/ 2 14

DAC

PLL disabled 150

PLL enabled 75 150

PLL disabled 75

PLL enabled 37.5 75

2V

3pF

0.9 ×

DV

DD

/ 2 V

DD

0.8 V

0.1 ×

DV

DD

MHz/

MHz

dB

Data

clock

cycles

Data

clock

cycles

V

V

P-P

Msps

MHz

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

V

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C

guaranteed by production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Output Settling Time t

Output Rise Time 10% to 90% (Note 2) 2.5 ns

Output Fall Time 90% to 10% (Note 2) 2.5 ns

Data-to-CLK Rise Setup Time
(Note 3)

Data-to-CLK Rise Hold Time
(Note 3)

Data-to-CLK Fall Setup Time
(Note 3)

Data-to-CLK Fall Hold Time
(Note 3)

Control Word to CW Fall Setup
Time

Control Word to CW Fall Hold
Time

CW High Time 5ns
CW Low Time 5ns

DACEN Rise-to-V

PD Fall-to-V

Clock Frequency at
CLKXP/CLKXN Input

CLKXP/CLKXN Differential Clock
Input to CLK Output Delay

Minimum CLKXP/CLKXN Clock
High Time

Minimum CLKXP/CLKXN Clock
Low Time

POWER REQUIREMENTS

Analog Power-Supply Voltage AV

Analog Supply Current I

Digital Power-Supply Voltage DV

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Stable t

OUT

Stable t

OUT

To ±0.1% error band (Note 2) 11 ns

s

t

DCSR

t

DCHR

t

DCSF

t

DCHF

t

CWS

t

CWH

STB

PDSTB

f

CLKDIFF

t

CXD

t

CXH

t

CXL

AVDD

PLL disabled 1.5

PLL enabled 2.2

PLL disabled 0.4

PLL enabled 1.4

PLL disabled 1.8

PLL enabled 2.4

PLL disabled 1.2

PLL enabled 1.3

External reference 0.5 ms

Differential clock, PLL disabled 300 MHz

PLL disabled 4.6 ns

DD

(Note 4) 45 49 mA

DD

2.5 ns

2.5 ns

0.7 µs

1.5 ns

1.5 ns

2.7 3.3 V

2.7 3.3 V

ns

ns

ns

ns

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

V

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C

guaranteed by production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Note 1: Including the internal reference voltage tolerance.
Note 2: Measured single ended with 50Ω load and complementary output connected to ground.
Note 3: Guaranteed by design, not production tested.
Note 4: Tested with an output frequency of f

OUT

= 5MHz.

Note 5: All digital inputs at 0 or DV

DD

. Clock signal disabled.

Figure 1. Load Test Circuit for CLK Outputs

Digital Supply Current (Note 4) I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PLL Power-Supply Voltage PV

PLL Supply Current (Note 4) I

Standby Current I

Power-Down Current I

Total Power Dissipation
(Note 4)

f

DAC

DVDD

PVDD

STANDBY

PD

P

TOT

DAC

f

DAC

DD

f

DAC

f

DAC

f

DAC

interpolation

(Note 5) 4.4 4.8 mA

(Note 5) 1 µA

f

DAC

DAC

f

DAC

= 60Msps

= 165Msps

= 200Msps

= 60Msps 17

= 165Msps 46 52

= 200Msps, 2x interpolation or 4x

= 60Msps

= 165Msps

= 200Msps

No interpolation 34

2x interpolation 75

4x interpolation 72

No interpolation 54 61

2x interpolation 146f

4x interpolation 140

2x interpolation 172 186

4x interpolation 165 178

No interpolation 324

2x interpolation 487

4x interpolation 498

No interpolation 438 486

2x interpolation 735f

4x interpolation 721

2x interpolation 816

4x interpolation 795

2.7 3.3 V

mA

mA

55 61

mW

TO OUTPUT

PIN

5pF

0.5mA

0.5mA

1.6V

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 7

)

Typical Operating Characteristics

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA,
differential output, T

A

= +25°C, unless otherwise noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

100

90

80

70

60

50

SFDR (dBc)

40

30

20

10

A

A

OUT

PLL DISABLED

0

0 102030405060708090

SPURIOUS-FREE DYNAMIC RANGE

(2x INTERPOLATION, f

100

A

90

80

70

60

50

SFDR (dBc)

40

30

20

10

OUT

A

OUT

PLL ENABLED

0

080

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

DAC

= -6dBFS

OUT

= -12dBS

OUTPUT FREQUENCY (MHz)

A

= 165MHz)

= 0dBFS

OUT

MAX5858A toc01

(NO INTERPOLATION, f

100

A

= -6dBFS

90

80

70

60

A

OUT

50

SFDR (dBc)

40

30

20

10

PLL DISABLED

0

035

OUT

= -12dBFS

OUTPUT FREQUENCY (MHz)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

= 300MHz)

DAC

= -6dBFS

= -12dBFS

OUTPUT FREQUENCY (MHz)

40302010 706050

A

OUT

= 0dBFS

MAX5858A toc04

100

90

80

70

60

50

SFDR (dBc)

40

30

20

10

0

vs. OUTPUT FREQUENCY

(2x INTERPOLATION, f

A

= -6dBFS

OUT

A

= 0dBFS

OUT

PLL DISABLED

045

2015105403530

OUTPUT FREQUENCY (MHz)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

100

A

= -6dBFS

OUT

90

80

70

60

A

= 0dBFS

50

SFDR (dBc)

40

30

20

10

0

OUT

PLL ENABLED

040

OUTPUT FREQUENCY (MHz)

DAC

2015105353025

= 300MHz)

A

= -12dBFS

OUT

MAX5858A toc07

DAC

20151053025

DAC

A

OUT

25

= 65MHz)

A

= 0dBFS

OUT

= 165MHz)

= -12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

DAC

40302010 706050

= 300MHz)

A

= -12dBFS

OUT

MAX5858A toc02

(2x INTERPOLATION, f

100

A

= -6dBFS

90

80

70

60

50

SFDR (dBc)

40

30

20

10

0

OUT

A

= 0dBFS

OUT

PLL DISABLED

080

OUTPUT FREQUENCY (MHz)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

= 165MHz)

DAC

A

OUT

= 0dBFS

MAX5858A toc05

(4x INTERPOLATION, f

100

SFDR (dBc)

A

= -6dBFS

90

80

70

60

50

40

30

20

10

OUT

A

= -12dBFS

OUT

PLL DISABLED

0

03691215 18 21

OUTPUT FREQUENCY (MHz)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

100

SFDR (dBc)

A

= -6dBFS

90

80

70

60

50

40

30

20

10

OUT

A

= 0dBFS

OUT

PLL DISABLED

0

040

OUTPUT FREQUENCY (MHz

DAC

A

2015105353025

= 300MHz)

= -12dBFS

OUT

MAX5858A toc08

MAX5858A toc03

MAX5858A toc06

MAX5858A

Dual, 10-Bit, 300Msps, DAC with 4x/2x/1x
Interpolation Filters and PLL

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA,
differential output, T

A

= +25°C, unless otherwise noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5858A toc10

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

807050 6020 30 4010

10

20

30

40

50

60

70

80

90

100

0

090

TA = -10°C

TA = +25°C

TA = +85°C

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0

7.8 11.4

FFT PLOT

(±2MHz WINDOW)

MAX5858A toc11

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

9.49.08.68.2 11.010.610.29.8

f

DAC

= 165MHz

f

OUT

= 10MHz

A

OUT

= -6dBFS

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0

0

8.25

16.50

24.75

33.00

41.25

49.50

57.75

66.00

74.25

82.50

FFT PLOT FOR DAC UPDATE NYQUIST WINDOW

(NO INTERPOLATION, f

DAC

= 165MHz,

f

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5858A toc12

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

0 102030405060708090100

FFT PLOT FOR DAC UPDATE NYQUIST

WINDOW (2x INTERPOLATION,

f

DAC

= 200MHz, f

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5858A toc13

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0

0 102030405060708090100

FFT PLOT FOR DAC UPDATE NYQUIST

WINDOW (4x INTERPOLATION,

f

DAC

= 200MHz, f

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5858A toc14

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE (NO INTERPOLATION,

f

DAC

= 165MHz, f

OUT

= 5MHz)

MAX5858A toc09

TEMPERATURE (°C)

SFDR (dBc)

603510-15

10

20

30

40

50

60

70

80

90

100

0

-40 85

A

OUT

= -12dBFS

A

OUT

= -6dBFS

A

OUT

= 0dBFS