MAXIM MAX5856A Technical data

General Description

The MAX5856A dual, 8-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5856A integrates two 8-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock multiplier, and a 1.24V reference. The MAX5856A supports single-ended and differential modes of operation. The MAX5856A dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of

-1.0V to +1.25V. The 4x/2x/1x programmable interpolation filters feature

excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. The PLL multiplier generates all internal synchronized high-speed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5856A to be updated on a single 8-bit bus.

The MAX5856A features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip

1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications.

The MAX5856A features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA.

The MAX5856A is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40°C to +85°C) operating temperature range.

Applications

Communications

SATCOM, LMDS, MMDS, HFC, DSL, WLAN,

Point-to-Point Microwave Links Wireless Base Stations Direct Digital Synthesis Instrumentation/ATE

Features

♦ 8-Bit Resolution, Dual DAC

♦ 300Msps Update Rate

♦ Integrated 4x/2x/1x Interpolating Filters

♦ Internal PLL Multiplier

♦ 2.7V to 3.3V Single Supply

♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance: 68dBc SFDR at

OUT

= 20MHz

♦ Programmable Channel Gain Matching

♦ Integrated 1.24V Low-Noise Bandgap Reference

♦ Single-Resistor Gain Control

♦ Interleave Data Mode

♦ Differential Clock Input Modes

♦ EV Kit Available—MAX5858AEVKIT

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

________________________________________________________________ Maxim Integrated Products 1

TQFP-EP

1 2 3 4 5 6 7 8

9 10 11 12

36 35 34 33 32 31 30 29 28 27 26 25

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43EP42 41 40 39 38 37

DB7

DB6

DB5

DB4

DB3

DGND

CLK

IDE

DB2

DB1

DB0

DGND

AVDDOUTPA

OUTNA

AGND

OUTPB

OUTNB

AVDDREFR

N.C.

DA7/PD

DA6/DACEN

DA5/F2EN DA4/F1EN

DA3/G3

DGND

DA2/G2 DA1/G1 DA0/G0

N.C. N.C.

REF0

PLLF PGND PV

CLKXN CLKXP PLLEN LOCK

N.C. N.C.

REN

NOTE: EXPOSED PADDLE CONNECTED TO GND.

MAX5856A

TOP VIEW

Pin Configuration

Ordering Information

19-3019; Rev 1; 3/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5856AECM

-40°C to +85°C 48 TQFP-EP*

*EP = Exposed paddle.

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDD, PVDDto AGND, DGND, PGND ..........-0.3V to +4V

DA7–DA0, DB7–DB0,

CW, REN, PLLF, PLLEN to AGND,

DGND, PGND........................................................-0.3V to +4V

IDE to AGND, DGND, PGND...................-0.3V to (DV

+ 0.3V)

CLKXN, CLKXP to PGND .........................................-0.3V to +4V

OUTP_, OUTN_ to AGND.......................-1.25V to (AV

+ 0.3V)

CLK, LOCK to DGND...............................-0.3V to (DV

+ 0.3V)

REFR, REFO to AGND .............................-0.3V to (AV

+ 0.3V) AGND to DGND, DGND to PGND,

AGND to PGND.................................................-0.3V to +0.3V

Maximum Current into Any Pin

(excluding power supplies)..........................................±50mA

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ....2.899W

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C,

guaranteed by production test. T

< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution 8 Bits Integral Nonlinearity INL RL = 0

LSB

Differential Nonlinearity DNL Guaranteed monotonic, RL = 0

LSB

Offset Error V

LSB

Internal reference (Note 1) -10

Gain Error (See the Parameter Definitions Section)

External reference

DYNAMIC PERFORMANCE

Maximum DAC Update Rate f

DAC

4x/2x interpolation modes

Msps

Glitch Impulse 5

pV-s

OUT

= 5MHz,

≥ +25°C

65 67

OUT

= 20MHz 68

OUT

= 50MHz 63

DAC

= 165Msps

OUT

= 70MHz 56

OUT

= 5MHz 68

OUT

= 40MHz 65

Spurious-Free Dynamic Range to Input Update Rate Nyquist

SFDR

DAC

= 300Msps,

2x interpolation

OUT

= 60MHz 67

dBc

DAC

= 200Msps, 2x interpolation,

OUT

= 40MHz, span = 20MHz

Spurious-Free Dynamic Range Within a Window

SFDR

DAC

= 165Msps, f

OUT

= 5MHz,

span = 4MHz

68 72

dBc

Multitone Power Ratio, 8 Tones, ~300kHz Spacing

MTPR f

DAC

= 165Msps, f

OUT

= 20MHz 65 dBc

Total Harmonic Distortion to Nyquist

THD f

DAC

= 165Msps, f

OUT

= 5MHz 70 dBc

-0.4 ±0.15 +0.4

-0.2 ±0.07 +0.2

-0.1 ±0.03 +0.1

-6.5 ±0.8 +6.5

300

±1.2 +10

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C,

guaranteed by production test. T

< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Noise Spectral Density n

DAC

= 165Msps, f

OUT

= 5MHz

dBm/Hz

Output Channel-to-Channel Isolation

OUT

= 5MHz 80 dB

Gain Mismatch Between Channels

OUT

= 5MHz

Phase Mismatch Between Channels

OUT

= 5MHz

Degrees

Wideband Output Noise 50

pA/√Hz

ANALOG OUTPUT

Full-Scale Output Current Range

220mA

Output Voltage Compliance Range

Output Leakage Current Power-down or standby mode -5 +5 µA

REFERENCE

Reference Output Voltage V

REFO

REN = AGND

Output-Voltage Temperature Drift

ppm/°C

Reference Output Drive Capability

50 µA

Reference Input Voltage Range REN = AV

0.1

Reference Supply Rejection 0.2

mV/V

Current Gain

mA/mA

INTERPOLATION FILTER (2x interpolation)

-0.005dB

-0.01dB

-0.1dB

Passband Width

OUT

-3dB

MHz/

MHz

0.604f

DAC

/ 2 to 1.396f

DAC

/ 2 74

0.600f

DAC

/ 2 to 1.400f

DAC

/ 2 62

0.594f

DAC

/ 2 to 1.406f

DAC

/ 2 53

Stopband Rejection

0.532f

DAC

/ 2 to 1.468f

DAC

/ 2 14

Group Delay 18

Data

clock

cycles

Impulse Response Duration 22

Data

clock

cycles

TCV

REF

IFS/I

REF

0.5f

DAC

-133

±0.05

±0.15

-1.0 +1.25

1.14 1.24 1.34 ±50

0.398

0.402

0.419

0.478

1.32

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C,

guaranteed by production test. T

< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

INTERPOLATION FILTER (4x interpolation)

-0.005dB 0.2

-0.01dB

-0.1dB

Passband Width

OUT

-3dB

MHz/

MHz

0.302f

DAC

/ 2 to 1.698f

DAC

/ 2 74

0.300f

DAC

/ 2 to 1.700f

DAC

/ 2 63

0.297f

DAC

/ 2 to 1.703 f

DAC

/ 2 53

Stopband Rejection

0.266f

DAC

/ 2 to 1.734f

DAC

/ 2 14

Group Delay 22

Data

clock

cycles

Impulse Response Duration 27

Data

clock

cycles

LOGIC INPUTS (IDE, CW, REN, DA7–DA0, DB7–DB0, PLLEN)

Digital Input Voltage High V

Digital Input Voltage Low V

0.8 V

Digital Input Current High I

VIH = 2V -1 +1 µA

Digital Input Current Low I

VIL = 0.8V -1 +1 µA

Digital Input Capacitance C

3pF

DIGITAL OUTPUTS (CLK, LOCK)

Digital Output-Voltage High V

SOURCE

= 0.5mA, Figure 1

0.9 × V

Digital Output-Voltage Low V

SINK

= 0.5mA, Figure 1

0.1 × V

DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN)

Clock Input Internal Bias

Differential Clock Input Swing 0.5

P-P

Clock Input Impedance Single-ended clock drive 5 kΩ

TIMING CHARACTERISTICS

No interpolation 165

PLL disabled 150

2x interpolation

PLL enabled 75 150 PLL disabled 75

Input Data Rate f

DATA

4x interpolation

PLL enabled

Msps

SYMBOL

0.5f

DAC

MIN TYP MAX

0.201

0.21

0.239

/ 2

37.5

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C,

guaranteed by production test. T

< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

No interpolation, PLL enabled 165 2x interpolation, PLL enabled 75 150Clock Frequency at CLK Input f

CLK

4x interpolation, PLL enabled

MHz

Output Settling Time t

To ±0.1% error band (Note 2) 11 ns Output Rise Time 10% to 90% (Note 2) 2.5 ns Output Fall Time 90% to 10% (Note 2) 2.5 ns

PLL disabled 1.5

Data-to-CLK Rise Setup Time (Note 3)

DCSR

PLL enabled 2.2

PLL disabled 0.4

Data-to-CLK Rise Hold Time (Note 3)

DCHR

PLL enabled 1.4

PLL disabled 1.8

Data-to-CLK Fall Setup Time (Note 3)

DCSF

PLL enabled 2.4

PLL disabled 1.2

Data-to-CLK Fall Hold Time (Note 3)

DCHF

PLL enabled 1.3

Control Word to CW Fall Setup Time

CWS

2.5 ns

Control Word to CW Fall Hold Time

CWH

2.5 ns

CW High Time 5ns CW Low Time 5ns

DACEN Rise-to-V

OUT

Stable t

STB

0.7 µs

PD Fall-to-V

OUT

Stable t

PDSTB

External reference 0.5 ms Clock Frequency at

CLKXP/CLKXN Input

Differential clock, PLL disabled 300

MHz

CLKXP/CLKXN Differential Clock Input to CLK Output Delay

CXD

PLL disabled 4.6 ns

Minimum CLKXP/CLKXN Clock High Time

CXH

1.5 ns

Minimum CLKXP/CLKXN Clock Low Time

CXL

1.5 ns

POWER REQUIREMENTS

Analog Power-Supply Voltage AV

2.7 3.3 V

Analog Supply Current I

AVDD

(Note 4) 44 47 mA Digital Power-Supply Voltage DV

2.7 3.3 V

SYMBOL

CLKDIFF

MIN TYP MAX

37.5

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f

DAC

= 165Msps, no interpolation, PLL disabled, external reference,

REFO

= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA> +25°C,

guaranteed by production test. T

< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

No interpolation 43 2x interpolation 99f

DAC

= 60Msps

4x interpolation No interpolation 53 58 2x interpolation

DAC

= 165Msps

4x interpolation 2x interpolation

178

Digital Supply Current (Note 4) I

DVDD

DAC

= 200Msps

4x interpolation

175

PLL Power-Supply Voltage PV

2.7 3.3 V

DAC

= 60Msps 16

DAC

= 165Msps 47 50

PLL Supply Current (Note 4) I

PVDD

DAC

= 200Msps, 2x interpolation or 4x

interpolation

55 60

Standby Current

(Note 5) 4.4 4.8 mA

Power-Down Current I

(Note 5) 1 µA

No interpolation 2x interpolation

DAC

= 60Msps

4x interpolation No interpolation

456

2x interpolation

DAC

= 165Msps

4x interpolation 2x interpolation

Total Power Dissipation (Note 4)

TOT

DAC

= 200Msps

4x interpolation

Note 1: Including the internal reference voltage tolerance. Note 2: Measured single ended with 50Ω load and complementary output connected to ground. Note 3: Guaranteed by design, not production tested. Note 4: Tested with an output frequency of f

OUT

= 5MHz.

Note 5: All digital inputs at 0 or DV

. Clock signal disabled.

1.6V

5pF

TO OUTPUT PIN

0.5mA

Figure 1. Load Test Circuit for CLK Outputs

SYMBOL

MIN TYP MAX

104

STANDBY

147 147 165 162

309 477 492 432 714 714 792 783

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 7

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5856A toc01

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

807050 6020 30 4010

100

090

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL DISABLED

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 65MHz)

MAX5856A toc02

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

3020 255 10 15

100

035

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL DISABLED

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(2x INTERPOLATION, f

DAC

= 300MHz)

MAX5856A toc04

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

706040 5010 20 30

100

080

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL ENABLED

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(2x INTERPOLATION, f

DAC

= 300MHz)

MAX5856A toc03

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

706040 5010 20 30

100

080

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL DISABLED

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(2x INTERPOLATION, f

DAC

= 165MHz)

MAX5856A toc05

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

403525 3010 15 205

100

045

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL DISABLED

Typical Operating Characteristics

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA, differential output, TA= +25°C, unless otherwise noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

DAC

= 300MHz)

MAX5856A toc06

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

353020 255 10 15

100

040

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL DISABLED

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

DAC

= 300MHz)

MAX5856A toc07

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

353020 255 10 15

100

040

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL ENABLED

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(4x INTERPOLATION, f

DAC

= 165MHz)

MAX5856A toc08

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

1812 153 6 9

100

021

OUT

= -6dBFS

OUT

= 0dBFS

OUT

= -12dBFS

PLL DISABLED

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA, differential output, TA= +25°C, unless otherwise noted.)

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5856A toc10

OUTPUT FREQUENCY (MHz)

SFDR (dBc)

807010 20 30 5040 60

090

TA = +25°C

TA = -10°C

TA = +85°C

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE (NO INTERPOLATION,

DAC

= 165MHz, f

OUT

= 5MHz)

MAX5856A toc 09

TEMPERATURE (°C)

SFDR (dBc)

603510-15

100

-40 85

OUT

= 0dBFS

OUT

= -6dBFS

OUT

= -12dBFS

FFT PLOT (±2MHz WINDOW)

MAX5856A toc11

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

11.310.79.5 10.18.98.3

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

7.7 11.7

CLK

= 165MHz

OUT

= 9.7MHz

OUT

= -6dBFS

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

8.25

16.50

24.75

33.00

41.25

49.50

57.75

66.00

74.25

82.50

FFT PLOT FOR DAC UPDATE NYQUIST WINDOW

(NO INTERPOLATION, f

DAC

= 165MHz,

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5856A toc12

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

0102030405060708090100

FFT PLOT FOR DAC UPDATE NYQUIST

WINDOW (2x INTERPOLATION,

DAC

= 200MHz, f

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5856A toc13

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

0102030405060708090100

FFT PLOT FOR DAC UPDATE NYQUIST

WINDOW (4x INTERPOLATION,

DAC

= 200MHz, f

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5856A toc14

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

-100

-60

-70

-80

-90

-40

-50

-20

-30

-10

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

_______________________________________________________________________________________ 9

Typical Operating Characteristics (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA, differential output, TA= +25°C, unless otherwise noted.)

2-TONE IMD PLOT

(NO INTERPOLATION, f

DAC

= 165MHz)

MAX5856A toc15

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

5.35.14.94.7

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

4.5 5.5

2 x fT1 - f

2 x fT2 - f

OUT

= -6dBFS

BW = 1MHz

fT1 = 4.9450MHz f

= 5.0683MHz

8-TONE MTPR PLOT (NO INTERPOLATION,

DAC

= 165MHz, f

CENTER

= 20.0052MHz)

MAX5856A toc16

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

21.020.519.5 20.019.0

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

18.5 21.5

OUT

= -18dBFS BW = 3MHz f

= 18.9550MHz

= 19.2551MHz

fT6 = 20.4352MHz f

= 20.7050MHz

= 20.9451MHz

fT3 = 19.4550MHz f

= 19.7553MHz

= 20.2551MHz

8-TONE MTPR PLOT (4x INTERPOLATION,

DAC

= 286.4MHz, f

CENTER

= 29.9923MHz)

MAX5856A toc17

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

31.030.529.5 30.029.0

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

28.5 31.5

OUT

= -18dBFS BW = 3MHz f

= 28.8866MHz

= 29.0912MHz

fT6 = 30.5911MHz f

= 30.8271MHz

= 31.1417MHz

= 29.3936MHz

= 29.6995MHz

= 30.2851MHz

T2fT3fT4fT5fT6fT7fT8

PHASE NOISE WITH PLL DISABLED

AND ENABLED

OUT

= f

DATA

/4, 2x INTERPOLATION)

MAX5856A toc20

OFFSET FREQUENCY (MHz)

NOISE DENSITY (dBm/Hz)

0.5MHz/div05

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-150

PLL ENABLED f

DATA

= 125MHz

PLL ENABLED f

DATA

= 100MHz PLL ENABLED f

DATA

= 150MHz

PLL DISABLED, f

DATA

= 75MHz

-100

-10

-20

-50

-60

-70

-80

-90

-40

-30

1.00

9.15

17.30

25.25

33.60

41.75

49.90

58.05

66.20

74.35

82.50

8-TONE MTPR PLOT FOR NYQUIST WINDOW

(NO INTERPOLATION, f

DAC

= 165MHz,

CENTER

= 19.9569MHz, A

OUT

= -18dBFS)

MAX5856A toc18

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

MTPR = 76dBc

-100

-40

-50

-30

-20

-80

-90

-70

-60

-10

1.0

15.2

28.6

42.9

57.2

71.5

85.8

100.1

114.4

128.7

143.2

8-TONE MTPR PLOT FOR

DAC UPDATE NYQUIST WINDOW

(4x INTERPOLATION, f

DAC

= 286.4MHz, f

CENTER

= 20MHz,

INPUT TONES SPACING ~300kHz, A

OUT

= -18dBFS)

MAX5856A toc19

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

A: IN-BAND-RANGE B: OUT-OF-BAND RANGE

35.8MHz

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

10 ______________________________________________________________________________________

POWER DISSIPATION

vs. SUPPLY VOLTAGE

MAX5856A toc26

SUPPLY VOLTAGE (V)

POWER DISSIPATION (mW)

3.23.12.8 2.9 3.0

300

400

500

600

700

800

900

1000

200

2.7 3.3

2x INTERPOLATION f

CLK

= 200MHz

OUT

= 5MHz

4x INTERPOLATION f

CLK

= 200MHz

OUT

= 5MHz

NO INTERPOLATION f

CLK

= 165MHz

OUT

= 5MHz

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX5856A toc27

SUPPLY VOLTAGE (V)

INTERNAL REFERENCE VOLTAGE (V)

3.23.13.02.92.8

1.21

1.22

1.23

1.24

1.25

1.26

1.27

1.20

2.7 3.3

1.20

1.22

1.21

1.24

1.23

1.26

1.25

1.27

1.28

-40 85

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX5856A toc28

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE (V)

10-15 35 60

Typical Operating Characteristics (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA, differential output, TA= +25°C, unless otherwise noted.)

FFT PLOT FOR PLL DISABLED

AND PLL ENABLED

OUT

= 10MHz, 2x INTERPOLATION)

MAX5856A toc21

OUTPUT FREQUENCY (MHz)

OUTPUT POWER (dBm)

1MHz/div

-100 515

-90

-80

-70

-60

-50

-40

-30

-20

-10

A: PLL DISABLED B: PLL ENABLED

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5856A toc22

INL (LSB)

DIGITAL INPUT CODE

224

192128 16064 9632

-0.08

-0.06

-0.04

-0.02

0.02

0.04

0.06

0.08

0.10

-0.10 0 256

RL = 0

POWER DISSIPATION vs. f

DAC

MAX5856A toc25

DAC

(MHz)

POWER DISSIPATION (mW)

25020050 100 150

300

400

500

600

700

800

900

1000

200

0 300

4x INTERPOLATION

2x INTERPOLATION

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5856A toc23

DIGITAL INPUT CODE

DNL (LSB)

224192160128966432

-0.05

-0.03

-0.01

0.01

0.03

0.05

0.07

-0.07 0 256

RL = 0

POWER DISSIPATION vs. f

DAC

MAX5856A toc24

DAC

(MHz)

POWER DISSIPATION (mW)

132996633

250

300

350

400

450

500

200

0 165

NO INTERPOLATION

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

______________________________________________________________________________________ 11

DYNAMIC RESPONSE FALL TIME

MAX5856A toc30

10ns/div

RL = 50Ω SINGLE ENDED

200mV/div

DYNAMIC RESPONSE RISE TIME

MAX5856A toc29

10ns/div

200mV/div

RL = 50Ω SINGLE ENDED

Typical Operating Characteristics (continued)

(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA, differential output, TA= +25°C, unless otherwise noted.)

Pin Description

PIN NAME FUNCTION

1 DA7/PD

Channel A Input Data Bit 7 (MSB)/Power-Down Control Bit: 0: Enter DAC standby mode (DACEN = 0) or power up DAC (DACEN = 1). 1: Enter power-down mode.

Channel A Input Data Bit 6/DAC Enable Control Bit: 0: Enter DAC standby mode with PD = 0. 1: Power up DAC with PD = 0. X: Enter power-down mode with PD = 1 (X = don’t care).

Channel A Input Data Bit 5/Second Interpolation Filter Enable Bit: 0: Interpolation mode is determined by F1EN. 1: Enable 4x interpolation mode. (F1EN must equal 1.)

Channel A Input Data Bit 4/First Interpolation Filter Enable Bit: 0: Interpolation disable. 1: Enable 2x interpolation.

5 DA3/G3 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3 6, 19, 47 DGND Digital Ground 7, 18, 48 DV

Digital Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. 8 DA2/G2 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2 9 DA1/G1 Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1

10 DA0/G0 Channel A Input Data Bit 0/Channel A Gain Adjustment Bit 0

11, 12, 25,

26, 37, 38

N.C. No Connection. Not connected internally.

13 DB7 Channel B Input Data Bit 7 (MSB) 14 DB6 Channel B Input Data Bit 6

DA6/DACEN

DA5/F2EN

DA4/F1EN

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

12 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

15 DB5 Channel B Input Data Bit 5 16 DB4 Channel B Input Data Bit 4 17 DB3 Channel B Input Data Bit 3

20 CLK

Clock Output/Input. CLK becomes an input when the PLL is enabled. CLK is an output when the PLL is disabled.

21 IDE

Interleave Data Mode Enable. When IDE is high, data for both DAC channels is written through port A (bits DA7–DA0). When IDE is low, channel A data is latched on the rising edge of CLK and channel B is latched on the falling edge of CLK.

22 DB2 Channel B Input Data Bit 2 23 DB1 Channel B Input Data Bit 1 24 DB0 Channel B Input Data Bit 0 27 CW Active-Low Control Word Write Pulse. The control word is latched on the falling edge of CW. 28 LOCK PLL Lock Signal Output. High level indicates that PLL is locked to the CLK signal. 29 PLLEN PLL Enabled Input. PLL is enabled when PLLEN is high.

30 CLKXP

Differential Clock Input Positive Terminal. Connect to PGND when the PLL is enabled. Bypass CLKXP with a 0.01µF capacitor to PGND when CLKXN is in single-ended mode.

31 CLKXN

Differential Clock Input Negative Terminal. Connect to PV

when the PLL is enabled. Bypass CLKXN

with a 0.01µF capacitor to PGND when CLKXP is in single-ended mode.

32 PV

PLL Power Supply. See Power Supplies, Bypassing, Decoupling, and Layout section. 33 PGND PLL Ground 34 PLLF

PLL Loop Filter. Connect a 4.12kΩ resistor in series with a 100pF capacitor between PLLF and PGND.

35 REN Active-Low Reference Enable. Connect REN to AGND to activate the on-chip 1.24V reference.

36 REFO

Reference I/O. REFO serves as the reference input when the internal reference is disabled. If the

internal 1.24V reference is enabled, REFO serves as the output for the internal reference. When the

internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor.

39 REFR

Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor R

SET

between REFR and AGND. The output full-scale current is equal to 32 × V

REFO / RSET

40, 46 AV

Analog Power Supply. See Power Supplies Bypassing, Decoupling, and Layout section. 41 OUTNB Channel B Negative Analog Current Output 42 OUTPB Channel B Positive Analog Current Output 43 AGND Analog Ground 44 OUTNA Channel A Negative Analog Current Output 45 OUTPA Channel A Positive Analog Current Output

—EPExposed Pad. Connect to the ground plane.

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

______________________________________________________________________________________ 13

Detailed Description

The MAX5856A dual, high-speed, 8-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal reconstruction. The MAX5856A combines two DAC cores with 4x/2x/1x programmable digital interpolation filters, a PLL clock multiplier, divide-by-N clock output, and an onchip 1.24V reference. The DAC current outputs can be configured for differential or single-ended operation. The full-scale output current range is adjustable from 2mA to 20mA to optimize power dissipation and gain control.

The MAX5856A accepts an input data rate up to 165MHz or a DAC conversion rate up to 300MHz. The inputs are latched on the rising edge of the clock. The outputs are latched on the following rising edge.

The two-stage digital interpolation filters are programmable to 4x, 2x, or no interpolation. When operating in 4x interpolation mode, the interpolator increases the DAC conversion rate by a factor of four, providing a four-fold increase in separation between the reconstructed waveform spectrum and its first image.

The on-chip PLL clock multiplier generates and distributes all internal, synchronized high-speed clock signals required by the input data latches, interpolation filters, and DAC cores. The on-chip PLL includes phase detector, VCO, prescalar, and charge pump circuits. The PLL can be enabled or disabled through PLLEN.

The analog and digital sections of the MAX5856A have separate power supply inputs (AVDDand DVDD). Also, a separate supply input is provided for the PLL clock multiplier (PV

). AVDD, DVDD, and PVDDoperate from

a 2.7V to 3.3V single supply. The MAX5856A features three power modes: normal,

standby, and power-down. These modes allow efficient power management. In power-down, the MAX5856A consumes only 1µA of supply current. Wake-up time from standby mode to normal DAC operation is 0.7µs.

Programming the DAC

An 8-bit control word routed through channel A’s data port programs the gain matching, interpolator configuration, and operational mode of the MAX5856A. The control word is latched on the falling edge of controlword write pulse (CW). The CW signal is asynchronous with CLK and CLKXN/CLKXP; therefore, the conversion clock (CLK or CLKXN/CLKXP) can run uninterrupted when a control word is written to the device.

Table 1 illustrates the control word format and function. The gain on channel A can be adjusted to achieve gain

matching between two channels in a user’s system. The gain on channel A can be adjusted from +0.4dB to

-0.35dB in steps of 0.05dB by using bits G3 to G0 (see Table 3).

INPUT

2x DIGITAL

INTERPOLATION

FILTER

2x DIGITAL

INTERPOLATION

FILTER

8-BIT

300MHz

DAC

PLL CLOCK MULTIPLIER

1.2V REFERENCE AND CONTROL AMPLIFIER

88 8 8

INPUT

2x DIGITAL

INTERPOLATION

FILTER

2x DIGITAL

INTERPOLATION

FILTER

8-BIT

300MHz

DAC

88 8 8

OUTPA

OUTNA

REFO REFR

CLKXP CLK

DA7–DA0

F1EN

F2EN

CLKXN

OUTPB

OUTNB

DB7–DB0

CONTROL REGISTER

AGNDPGND

DDPVDD

DGND

SET

PLLF

PLLEN

LOCK

IDE

REN

MAX5856A

Functional Diagram

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

14 ______________________________________________________________________________________

Device Power-Up and

States of Operation

At power-up, the MAX5856A is configured in no-interpolation mode with a gain adjustment setting of 0dB and a fully operational converter. In shutdown, the MAX5856A consumes only 1µA of supply current, and in standby the current consumption is 4.4mA. Wake-up time from standby mode to normal operation is 0.7µs.

Interpolation Filters

The MAX5856A features a 2-stage, 2x digital interpolating filter based on 43-tap and 23-tap FIR topology. F1EN and F2EN enable the interpolation filters. F1EN = 1 enables the first filter for 2x interpolation and F2EN = 1 enables the second filter for combined 4x interpolation. To bypass and disable both interpolation filters (no-interpolation mode or 1x mode) set F1EN = F2EN = 0. When set for 1x mode the filters are powered down and consume virtually no current. An illegal condition is defined by: F1EN = 0, F2EN = 1 (see Table 2 for configuration modes).

The programmable interpolation filters multiply the

MAX5856A input data rate by a factor of two or four to separate the reconstructed waveform spectrum and the first image. The original spectral images, appearing around multiples of the DAC input data rate, are attenuated at least 60dB by the internal digital filters. This feature provides three benefits:

1) Image separation reduces complexity of analog reconstruction filters.

2) Lower input data rates eliminate board-level highspeed data transmission.

3) Sin(x)/x rolloff is reduced over the effective bandwidth.

Figure 2 shows an application circuit and Figure 3 illustrates a practical example of the benefits when using the MAX5856A with 4x-interpolation mode. The example illustrates signal synthesis of a 20MHz IF with a ±10MHz bandwidth. Three options can be considered to address the design requirements. The tradeoffs for each solution are shown in Table 4.

MSB

LSB

PD DACEN F2EN F1EN G3 G2 G1 G0

CONTROL WORD

FUNCTION

PD Power-down; The part enters power-down mode if PD = 1.

DACEN DAC Enable; When DACEN = 0 and PD = 0, the part enters standby mode.

F2EN

Filter Enable; When F2EN = 1 and F1EN = 1, 4x interpolation is enabled. When F2EN = 0, the interpolation mode is determined by F1EN.

F1EN

Filter Enable; When F1EN = 1 and F2EN = 0, 2x interpolation is active. With F1EN = 0 and F2EN = 0, the interpolation is disabled.

G3 Bit 3 (MSB) of gain adjust word. G2 Bit 2 of gain adjust word. G1 Bit 1 of gain adjust word. G0 Bit 0 (LSB) of gain adjust word.

Table 1. Control Word Format and Function

MODE PD

DACEN

F2EN

F1EN

No interpolation

0100 2x interpolation 0101 4x interpolation 0111

Standby 0 0 X X

Power-down 1 X X X

Power-up 0 1 X X

Table 2. Configuration Modes

X = Don’t care. F1EN = 0, F2EN = 1: illegal condition.

GAIN ADJUSTMENT ON

CHANNEL A (dB)

G3 G2 G1 G0

+0.4 0000

0 1000

-0.35 1111

Table 3. Gain Difference Setting

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

______________________________________________________________________________________ 15

FS ANALOG OUT SPECIFIED OVER

ENTIRE SUPPLY RANGE

+2.7V TO +3.3V

CLOCK SOURCE

DAC

= 286.4MHz

SINGLE SUPPLY

+2.7V TO +3.3V

CHA DAC

CHB DAC

DIV-4 DIV-2 DIV-1

INTERPOLATING

FILTERS 4X/2X

INTERPOLATING

FILTERS 4X/2X

DATA LATCH

8-BIT BUS

DATA LATCH

8-BIT BUS

DIGITAL BASEBAND

OFDM PROCESSOR

QAM-MAPPER

INTERLEAVE DATA LATCH

BOUT

AOUT

SINGLE 8-BIT BUS

SAVES I/O PINS

DATA CLOCK OUT

DATA

= 71.6MHz

MAX5856A

Figure 2. Typical Application Circuit

OPTION

SOLUTION ADVANTAGE DISADVANTAGE

• No interpolation

• 2.6x oversample

• f

DAC

= f

DATA

= 78MHz

• Low data rate

• Low clock rate

• High-order filter

• Filter gain/phase match

• No interpolation

• 8x oversample

• f

DAC

= f

DATA

= 240MHz

• Push image to f

IMAGE

= 210MHz

• Lower order filter

• Filter gain/phase match

• High clock rate

• High data rate

• 4x interpolation

• Passband attenuation = 0.1dB

• Push image to 256MHz

• Low data rate

• Low-order filter

• 60dB image attenuate

• Filter gain/phase match

• None

Table 4. Benefits of Interpolation

• f

= 286.4MHz, f

DAC

= 71.6MHz

DATA

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

16 ______________________________________________________________________________________

This example demonstrates that 4x interpolation with digital filtering yields significant benefits in reducing system complexity, improving dynamic performance, and lowering cost. Data can be written to the MAX5856A at much lower speeds while achieving image attenuation greater than 60dB and image separation beyond three octaves. The main benefit is in analog reconstruction fil-

ter design. Reducing the filter order eases gain/phase matching while lowering filter cost and saving board space. Because the data rate is lowered to 71.6MHz, the setup and hold times are manageable and the clock signal source is simplified, which results in improved system reliability and lower cost.

SOLUTION 1

SOLUTION 2

SOLUTION 3

IMAGE SEPARATION = 18MHz LESS THAN ONE OCTAVE HIGH ORDER ANALOG FILTER

IMAGE SEPARATION = 180MHz

HIGH-SPEED CLK = 240MHz

LOWER ORDER ANALOG FILTER

NEW FIRST IMAGE

SEPARATION > 3-OCTAVES

SIMPLE ANALOG FILTER

FREQUENCY AXIS NOT TO SCALE

DIGITAL FILTER

ATTENUATION > 60dB

OUT

20MHz

±10MHz

OUT

20MHz

BW = ±10MHz

OUT

20MHz

BW = ±10MHz

IMAGE

DAC

- f

OUT

48MHz

IMAGE

DAC

+ f

OUT

108MHz

DAC

78MHz

IMAGE

DAC

- f

OUT

210MHz

IMAGE

DAC

+ f

OUT

270MHz

DAC

240MHz

IMAGE

DAC

- f

OUT

256MHz

IMAGE

DAC

+ f

OUT

316MHz

DAC

286MHz

DATA

71.6MHz

Figure 3. MAX5856A in 4x Interpolation Mode

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

______________________________________________________________________________________ 17

PLL Clock Multiplier and

Clocking Modes

The MAX5856A features an on-chip PLL clock multiplier, which generates all internal, synchronized highspeed clock signals required by the input data latches, interpolation filters, and DAC cores. The on-chip PLL includes a phase detector, VCO, prescalar, and charge-pump circuits. The PLL can be enabled or disabled through PLLEN. To enable PLL, set PLLEN = 1.

With the PLL enabled (PLLEN = 1) and 4x/2x interpolation enabled, an external low-frequency clock reference source may be applied to CLK pin. The clock reference source serves as the input data clock. The on-chip PLL multiplies the clock reference by a factor of two (2x) or a factor of four (4x). The input data rate range and CLK frequency are set by the selected interpolation mode. In 2x interpolation mode, the data rate range is 75MHz to 150MHz. In 4x interpolation mode, the data rate range is 37.5MHz to 75MHz.

Note: When the PLL is enabled, CLK becomes an input, requiring CLKXP to be pulled low and CLKXN to be pulled high. To obtain the best phase noise performance, disable the PLL function.

With the PLL disabled (PLLEN = 0) and 4x/2x interpolation enabled, an external conversion clock is applied at CLKXN/CLKXP. The conversion clock at CLKXN/CLKXP has a frequency range of 0 to 300MHz (see Table 5). This clock is buffered and distributed by the MAX5856A to drive the interpolation filters and DAC cores. In this mode, CLK becomes a divide-by-N (DIVN) output at either a divide-by-two or divide-by-four rate. The DIV-N factor is set by the selected interpola-

tion mode. The CLK output, at DIV-N rate, must be used to synchronize data into the MAX5856A data ports. In this mode, keep the capacitive load at the CLK output low (10pF or less at f

DAC

= 165MHz).

With the interpolation disabled (1x mode) and the PLL disabled (PLLEN = 0), the input clock at CLKXN/CLKXP can be used to directly update the DAC cores. In this mode, the maximum data rate is 165MHz.

Internal Reference and Control Amplifier

The MAX5856A provides an integrated 50ppm/°C,

1.24V, low-noise bandgap reference that can be disabled and overridden with an external reference voltage. REFO serves either as an external reference input or an integrated reference output. If REN is connected to AGND, the internal reference is selected and REFO provides a 1.24V (50µA) output. Buffer REFO with an external amplifier, when driving a heavy load.

The MAX5856A also employs a control amplifier designed to simultaneously regulate the full-scale output current (IFS) for both outputs of the devices. Calculate the output current as:

IFS= 32 x I

REF

where I

REF

is the reference output current (I

REF

REFO/RSET

) and IFSis the full-scale output current.

SET

is the reference resistor that determines the amplifier output current of the MAX5856A (Figure 4). This current is mirrored into the current-source array where IFSis equally distributed between matched current segments and summed to valid output current readings for the DACs.

COMP

REFR

REF

REFO

MAX4040

1.24V

BANDGAP

REFERENCE

CURRENT-

SOURCE ARRAY

*COMPENSATION CAPACITOR (C

COMP

≈ 100nF)

OPTIONAL EXTERNAL BUFFER FOR HEAVIER LOADS

REN

MAX5856A

REF

SET

AGND

Figure 4. Setting IFS with the Internal 1.24V Reference and the Control Amplifier

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

18 ______________________________________________________________________________________

External Reference

To disable the internal reference of the MAX5856A, connect REN to AVDD. Apply a temperature-stable, external reference to REFO to set the full-scale output (Figure 5). For improved accuracy and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference.

Detailed Timing

The MAX5856A accepts an input data rate up to 165MHz or a DAC conversion rate of up to 300MHz. The inputs are latched on the rising edge of the clock. The outputs are latched on the following rising edge.

0.1µF10µF

SET

REF

REFR

REFO

1.24V

BANDGAP

REFERENCE

CURRENT-

SOURCE ARRAY

EXTERNAL

1.24V

REFERENCE

REN

MAX5856A

MAX6520

AGND

Figure 5. MAX5856A with External Reference

PLLEN

F2EN

F1EN

DIFFERENTIAL CLOCK

FREQUENCY

CLKDIFF

(MHz)

CLOCK

FREQUENCY

CLK

(MHz)

DAC RATE

DAC

INTERPOLATION

MAX SIGNAL

BANDWIDTH

(MHz)

100

N/A (tie CLXP low

and CLXN high)

0 to 165 (input) f

CLK

1x 82

101

N/A (tie CLXP low

and CLXN high)

2* f

CLK

2x 63

111

N/A (tie CLXP low

and CLXN high)

37 to 75 (input) 4* f

CLK

4x 31

000 0 to 165

1x 82

001 0 to 300

2x 63

011 0 to 300

4x 31 010 110

Illegal

Table 5. PLL Clocking Modes

75 to 150 (input)

CLKDIFF

/ 2 (output) f / 4 (output) f

(output) f

CLKDIFF CLKDIFF CLKDIFF

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

______________________________________________________________________________________ 19

CLKXP

CLK

DA0–DA7/

CONTROL WORD

CXD

DCSR

DCHR

CONTROL WORD

N+1

1. CLKXP AND CLKXN MUST BE PRESENT ONLY WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION.

2. CLK IS AN OUTPUT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND; OTHERWISE, IT IS AN INPUT.

CLKXN

CWH

DB0–DB7

CXD

CWS

Figure 6. Timing Diagram for Noninterleave Data Mode (IDE = Low)

Figure 6 illustrates the DAC write cycle in 4x interpolation mode. With the interpolation feature enabled, the device can operate with the PLL enabled or disabled. To obtain best phase noise performance, disable the PLL and keep the capacitive load at the CLK output low (10pF or less at f

DAC

= 165MHz).

With the PLL disabled (PLLEN = 0), the clock signal is applied to CLKXP/CLKXN and internally divided by 4 to generate the DAC’s CLK signal. The CLK signal is a divide-by-4 output, used to synchronize data into the MAX5856A data ports. The CLKXP/CLKXN signal drives the interpolation filters and DAC cores at the desired conversion rate.

If the PLL is enabled (PLLEN = 1), then CLK becomes an input and the clock signal may be applied to CLK. In Figure 6, the CLK signal is multiplied by a factor of four by the PLL and distributed to the interpolation filters and DAC cores. In this mode, CLKXP must be pulled low and CLKXN pulled high.

The MAX5856A can operate with a single-ended clock input used as both data clock and conversion clock. To operate the device in this mode, disable the interpolation filters and enable the PLL (PLLEN = 1). Apply a singleended clock input at CLK. The CLK signal acts as the data synchronization clock and DAC core conversion clock. Though the PLL is enabled, the lock pin (LOCK) is not valid and the PLL is internally disconnected from the interpolating filters and DAC cores. In this mode, CLKXP must be pulled low and CLKXN pulled high.

Figure 6 shows the timing for the CW. An 8-bit control word routed through channel A’s data port programs the gain matching, interpolator configuration, and operational mode of the MAX5856A. The control word is latched on the falling edge of CW. The CW signal is asynchronous with conversion clocks CLK and CLKXN/CLKXP; therefore, the conversion clock (CLK or CLKXN/CLKXP) can run uninterrupted when a control word is written to the device.

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

20 ______________________________________________________________________________________

CLKXP

CLK

CXD

DCSR

DCSFtDCHF

DCHR

N+1

N+2

1. CLKXP AND CLKXN MUST BE PRESENT ONLY WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND. THE DIAGRAM SHOWS 4x INTERPOLATION.

2. CLK IS AN OUTPUT WHEN PLL IS DISABLED, WITH PLLEN CONNECTED TO GND; OTHERWISE, IT IS AN INPUT.

CLKXN

DA0–DA7

CXD

Figure 7. Timing Diagram for Interleave Data Mode (IDE = High)

1/2 MAX5856A

DA0–DA7

1/2 MAX5856A

DB0–DB7

DDDVDDPVDD

AGND DGND PGND

OUTPA

OUTNA

50Ω

100Ω

OUTA

SINGLE ENDED

OUTPB

OUTNB

50Ω

100Ω

OUTB

SINGLE ENDED

Figure 8. Application with Output Transformer Performing Differential to Single-Ended Conversion

The MAX5856A can operate in interleave data mode by setting IDE = 1. In interleave data mode, data for both DAC channels is written through input port A. Channel B data is written on the falling edge of the CLK signal and then channel A data is written on the following rising edge of the CLK signal. Both DAC outputs (channel A and B) are updated simultaneously on the next rising edge of CLK. In interleave data mode, the maximum input data rate per channel is one-half the rate of noninterleave mode. Interleave data mode is an attractive feature that lowers digital I/O pin count, reduces digital ASIC cost, and improves system reliability (Figure 7).

Applications Information

Differential-to-Single-Ended Conversion

The MAX5856A exhibits excellent dynamic performance to synthesize a wide variety of modulation schemes, including high-order QAM modulation with OFDM.

Figure 8 shows a typical application circuit with output transformers performing the required differential-to-single-ended signal conversion. In this configuration, the MAX5856A operates in differential mode, which reduces even-order harmonics, and increases the available output power.

Differential DC-Coupled Configuration

Figure 9 shows the MAX5856A output operating in differential DC-coupled mode. This configuration can be used in communication systems employing analog quadrature upconverters and requiring a baseband sampling, dualchannel, high-speed DAC for I/Q synthesis. In these applications, information bandwidth can extend from 10MHz down to several hundred kilohertz. DC-coupling is desirable in order to eliminate long discharge time constants that are problematic with large, expensive coupling capacitors. Analog quadrature upconverters have a DC common-mode input requirement of typically

0.7V to 1.0V. The MAX5856A differential I/Q outputs can maintain the desired full-scale signal level at the required

0.7V to 1.0V DC common-mode voltage when powered from a single 2.85V (±5%) supply. The MAX5856A meets this low-power requirement with minimal reduction in dynamic range while eliminating the need for level-shifting resistor networks.

Power Supplies, Bypassing,

Decoupling, and Layout

Grounding and power-supply decoupling strongly influence the MAX5856A performance. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, which can affect dynamic specifications, like signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX5856A. Observe the grounding and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the power-supply and filter configuration to achieve optimum dynamic performance.

Use of a multilayer printed circuit (PC) board with separate ground and power-supply planes is recommended. Run high-speed signals on lines directly above the ground plane. The MAX5856A has separate analog and digital ground buses (AGND, PGND, and DGND, respectively). Provide separate analog, digital, and clock ground sections on the PC board with only one point connecting the three planes. The ground connection points should be located underneath the device and connected to the exposed paddle. Run digital signals above the digital ground plane and analog/clock signals above the analog/clock ground plane. Digital signals should be kept away from sensitive analog, clock, and reference inputs. Keep digital signal paths short and metal trace lengths matched to avoid propagation delay and data skew mismatch.

The MAX5856A includes three separate power-supply inputs: analog (AV

), digital (DVDD), and clock (PVDD). Use a single linear regulator power source to branch out to three separate power-supply lines (AVDD, DVDD, PVDD) and returns (AGND, DGND, PGND). Filter each power-supply line to the respective return line using LC filters comprising ferrite beads and 10µF capacitors. Filter each supply input locally with 0.1µF ceramic capacitors to the respective return lines.

Note: To maintain the dynamic performance of the Electrical Characteristics, ensure the voltage difference between DVDD, AVDD, and PVDDdoes not exceed 150mV.

Thermal Characteristics and

Packaging

Thermal Resistance

48-lead TQFP-EP:

θJA = 27.6°C/W

Keep the device junction temperature below +125°C to meet specified electrical performance. Lower the power-supply voltage to maintain specified performance when the DAC update rate approaches 300Msps and the ambient temperature equals +85°C.

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

______________________________________________________________________________________ 21

1/2 MAX5856A

OUTPA

OUTNA

50Ω

DA0–DA7

1/2 MAX5856A

OUTPB

OUTNB

50Ω

DB0–DB7

DDDVDDPVDD

AGND DGND PGND

Figure 9. Application with DC-Coupled Differential Outputs

MAX5856A

The MAX5856A is packaged in a 48-pin TQFP-EP package, providing design flexibility, increased thermal efficiency, and optimized AC performance of the DAC. The EP enables the implementation of grounding techniques necessary to ensure highest performance.

In this package, the data converter die is attached to an EP lead frame with the back of this frame exposed at the package bottom surface, facing the PC board side of the package. This allows a solid attachment of the package to the PC board with standard infrared (IR)-flow soldering techniques. A specially created land pattern on the PC board, matching the size of the EP, ensures the proper attachment and grounding of the DAC. Designing vias into the land area and implementing large ground planes in the PC board design achieve optimal DAC performance. Use an array of 3 x 3 (or greater) vias (≤0.3mm diameter per via hole and

1.2mm pitch between via holes) for this 48-pin TQFPEP package.

Dynamic Performance

Parameter Definitions

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of all essential harmonics (within a Nyquist window) of the input signal to the fundamental itself. This can be expressed as:

where V1is the fundamental amplitude, and V2through VNare the amplitudes of the 2nd through Nth order harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value of the next-largest spectral component. SFDR is usually measured in dBc with respect to the carrier frequency amplitude or in dBFS with respect to the DAC’s fullscale range. Depending on its test condition, SFDR is observed within a predefined window or to Nyquist.

Multitone Power Ratio (MTPR)

A series of equally spaced tones are applied to the DAC with one tone removed from the center of the range. MTPR is defined as the worst-case distortion (usually a 3rd-order harmonic product of the fundamental frequencies), which appears as the largest spur at the frequency of the missing tone in the sequence. This test can be performed with any number of input tones; however, four and eight tones are among the most

common test conditions for CDMA- and GSM/EDGEtype applications.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc of either output tone to the worst 3rd-order (or higher) IMD products.

Static Performance Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every individual step.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between an actual step height and the ideal value of 1 LSB. A DNL error specification ≥ -1 LSB guarantees a monotonic transfer function.

Offset Error

Offset error is the current flowing from positive DAC output when the digital input code is set to zero. Offset error is expressed in LSBs.

Gain Error

A gain error is the difference between the ideal and the actual full-scale output current on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. The ideal current is defined by reference voltage at V

REFO

/ I

REF

x 32.

Settling Time

The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value (within the converter’s specified accuracy).

Glitch Impulse

A glitch is generated when a DAC switches between two codes. The largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011…111 to 100…000. This occurs due to timing variations between the bits. The glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. The glitch impulse is usually specified in pV-s.

Chip Information

TRANSISTOR COUNT: 178,376 PROCESS: CMOS

THD V V V V V

=× + + +

()

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Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

22 ______________________________________________________________________________________

MAX5856A

Dual 8-Bit, 300Msps DAC with 4x/2x/1x

Interpolation Filters and PLL

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

48L,TQFP.EPS

MAXIM MAX5856A Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual