MAXIM MAX5856A Technical data
General Description
The MAX5856A dual, 8-bit, 300Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The MAX5856A
integrates two 8-bit DAC cores, 4x/2x/1x programmable
digital interpolation filters, phase-lock loop (PLL) clock
multiplier, and a 1.24V reference. The MAX5856A supports single-ended and differential modes of operation.
The MAX5856A dynamic performance is maintained over
the entire power-supply operating range of 2.7V to 3.3V.
The analog outputs support a compliance voltage of
-1.0V to +1.25V.
The 4x/2x/1x programmable interpolation filters feature
excellent passband distortion and noise performance.
Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and
the clock speeds of the digital interface. The PLL multiplier
generates all internal synchronized high-speed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity
and lower cost. To reduce the I/O pin count, the DAC can
also operate in interleave data mode. This allows the
MAX5856A to be updated on a single 8-bit bus.
The MAX5856A features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on-chip
1.24V bandgap reference includes a control amplifier
that allows external full-scale adjustments of both channels through a single resistor. The internal reference can
be disabled and an external reference may be applied
for high-accuracy applications.
The MAX5856A features full-scale current outputs of
2mA to 20mA and operates from a 2.7V to 3.3V single
supply. The DAC supports three modes of power-control
operation: normal, low-power standby, and complete
power-down. In power-down mode, the operating current is reduced to 1µA.
The MAX5856A is packaged in a 48-pin TQFP with
exposed paddle (EP) for enhanced thermal dissipation
and is specified for the extended (-40°C to +85°C) operating temperature range.
Applications
Communications
SATCOM, LMDS, MMDS, HFC, DSL, WLAN,
Point-to-Point Microwave Links
Wireless Base Stations
Direct Digital Synthesis
Instrumentation/ATE
Features
♦ 8-Bit Resolution, Dual DAC
♦ 300Msps Update Rate
♦ Integrated 4x/2x/1x Interpolating Filters
♦ Internal PLL Multiplier
♦ 2.7V to 3.3V Single Supply
♦ Full Output Swing and Dynamic Performance at
2.7V Supply
♦ Superior Dynamic Performance: 68dBc SFDR at
f
OUT
= 20MHz
♦ Programmable Channel Gain Matching
♦ Integrated 1.24V Low-Noise Bandgap Reference
♦ Single-Resistor Gain Control
♦ Interleave Data Mode
♦ Differential Clock Input Modes
♦ EV Kit Available—MAX5858AEVKIT
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
________________________________________________________________ Maxim Integrated Products 1
TQFP-EP
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43EP42 41 40 39 38 37
DB7
DB6
DB5
DB4
DB3
DV
DD
DGND
CLK
IDE
DB2
DB1
DB0
DV
DD
DGND
AVDDOUTPA
OUTNA
AGND
OUTPB
OUTNB
AVDDREFR
N.C.
N.C.
DA7/PD
DA6/DACEN
DA5/F2EN
DA4/F1EN
DA3/G3
DGND
DV
DD
DA2/G2
DA1/G1
DA0/G0
N.C.
N.C.
REF0
PLLF
PGND
PV
DD
CLKXN
CLKXP
PLLEN
LOCK
N.C.
N.C.
CW
REN
NOTE: EXPOSED PADDLE CONNECTED TO GND.
MAX5856A
TOP VIEW
Pin Configuration
Ordering Information
19-3019; Rev 1; 3/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX5856AECM
-40°C to +85°C 48 TQFP-EP*
*EP = Exposed paddle.
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD, PVDDto AGND, DGND, PGND ..........-0.3V to +4V
DA7–DA0, DB7–DB0,
CW, REN, PLLF, PLLEN to AGND,
DGND, PGND........................................................-0.3V to +4V
IDE to AGND, DGND, PGND...................-0.3V to (DV
DD
+ 0.3V)
CLKXN, CLKXP to PGND .........................................-0.3V to +4V
OUTP_, OUTN_ to AGND.......................-1.25V to (AV
DD
+ 0.3V)
CLK, LOCK to DGND...............................-0.3V to (DV
DD
+ 0.3V)
REFR, REFO to AGND .............................-0.3V to (AV
DD
+ 0.3V)
AGND to DGND, DGND to PGND,
AGND to PGND.................................................-0.3V to +0.3V
Maximum Current into Any Pin
(excluding power supplies)..........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP-EP (derate 36.2mW/°C above +70°C) ....2.899W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T
MIN
to T
MAX
, unless otherwise noted. TA> +25°C,
guaranteed by production test. T
A
< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution 8 Bits
Integral Nonlinearity INL RL = 0
LSB
Differential Nonlinearity DNL Guaranteed monotonic, RL = 0
LSB
Offset Error V
OS
LSB
Internal reference (Note 1) -10
Gain Error (See the Parameter
Definitions Section)
GE
External reference
%
DYNAMIC PERFORMANCE
Maximum DAC Update Rate f
DAC
4x/2x interpolation modes
Msps
Glitch Impulse 5
pV-s
f
OUT
= 5MHz,
T
A
≥ +25°C
65 67
f
OUT
= 20MHz 68
f
OUT
= 50MHz 63
f
DAC
= 165Msps
f
OUT
= 70MHz 56
f
OUT
= 5MHz 68
f
OUT
= 40MHz 65
Spurious-Free Dynamic Range to
Input Update Rate Nyquist
SFDR
f
DAC
= 300Msps,
2x interpolation
f
OUT
= 60MHz 67
dBc
f
DAC
= 200Msps, 2x interpolation,
f
OUT
= 40MHz, span = 20MHz
67
Spurious-Free Dynamic Range
Within a Window
SFDR
f
DAC
= 165Msps, f
OUT
= 5MHz,
span = 4MHz
68 72
dBc
Multitone Power Ratio, 8 Tones,
~300kHz Spacing
MTPR f
DAC
= 165Msps, f
OUT
= 20MHz 65 dBc
Total Harmonic Distortion to
Nyquist
THD f
DAC
= 165Msps, f
OUT
= 5MHz 70 dBc
-0.4 ±0.15 +0.4
-0.2 ±0.07 +0.2
-0.1 ±0.03 +0.1
-6.5 ±0.8 +6.5
300
±1.2 +10
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T
MIN
to T
MAX
, unless otherwise noted. TA> +25°C,
guaranteed by production test. T
A
< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Noise Spectral Density n
D
f
DAC
= 165Msps, f
OUT
= 5MHz
dBm/Hz
Output Channel-to-Channel
Isolation
f
OUT
= 5MHz 80 dB
Gain Mismatch Between
Channels
f
OUT
= 5MHz
dB
Phase Mismatch Between
Channels
f
OUT
= 5MHz
Degrees
Wideband Output Noise 50
pA/√Hz
ANALOG OUTPUT
Full-Scale Output Current Range
I
FS
220mA
Output Voltage Compliance
Range
V
Output Leakage Current Power-down or standby mode -5 +5 µA
REFERENCE
Reference Output Voltage V
REFO
REN = AGND
V
Output-Voltage Temperature Drift
ppm/°C
Reference Output Drive
Capability
50 µA
Reference Input Voltage Range REN = AV
DD
0.1
V
Reference Supply Rejection 0.2
mV/V
Current Gain
32
mA/mA
INTERPOLATION FILTER (2x interpolation)
-0.005dB
-0.01dB
-0.1dB
Passband Width
f
OUT
/
-3dB
MHz/
MHz
0.604f
DAC
/ 2 to 1.396f
DAC
/ 2 74
0.600f
DAC
/ 2 to 1.400f
DAC
/ 2 62
0.594f
DAC
/ 2 to 1.406f
DAC
/ 2 53
Stopband Rejection
0.532f
DAC
/ 2 to 1.468f
DAC
/ 2 14
dB
Group Delay 18
Data
clock
cycles
Impulse Response Duration 22
Data
clock
cycles
TCV
REF
IFS/I
REF
0.5f
DAC
-133
±0.05
±0.15
-1.0 +1.25
1.14 1.24 1.34
±50
0.398
0.402
0.419
0.478
1.32
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T
MIN
to T
MAX
, unless otherwise noted. TA> +25°C,
guaranteed by production test. T
A
< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
INTERPOLATION FILTER (4x interpolation)
-0.005dB 0.2
-0.01dB
-0.1dB
Passband Width
f
OUT
/
-3dB
MHz/
MHz
0.302f
DAC
/ 2 to 1.698f
DAC
/ 2 74
0.300f
DAC
/ 2 to 1.700f
DAC
/ 2 63
0.297f
DAC
/ 2 to 1.703 f
DAC
/ 2 53
Stopband Rejection
0.266f
DAC
/ 2 to 1.734f
DAC
/ 2 14
dB
Group Delay 22
Data
clock
cycles
Impulse Response Duration 27
Data
clock
cycles
LOGIC INPUTS (IDE, CW, REN, DA7–DA0, DB7–DB0, PLLEN)
Digital Input Voltage High V
IH
2V
Digital Input Voltage Low V
IL
0.8 V
Digital Input Current High I
H
VIH = 2V -1 +1 µA
Digital Input Current Low I
IL
VIL = 0.8V -1 +1 µA
Digital Input Capacitance C
IN
3pF
DIGITAL OUTPUTS (CLK, LOCK)
Digital Output-Voltage High V
OH
I
SOURCE
= 0.5mA, Figure 1
0.9 ×
V
Digital Output-Voltage Low V
OL
I
SINK
= 0.5mA, Figure 1
0.1 ×
V
DIFFERENTIAL CLOCK INPUT (CLKXP, CLKXN)
Clock Input Internal Bias
V
Differential Clock Input Swing 0.5
V
P-P
Clock Input Impedance Single-ended clock drive 5 kΩ
TIMING CHARACTERISTICS
No interpolation 165
PLL disabled 150
2x interpolation
PLL enabled 75 150
PLL disabled 75
Input Data Rate f
DATA
4x interpolation
PLL enabled
75
Msps
SYMBOL
0.5f
DAC
MIN TYP MAX
0.201
0.21
0.239
DV
DD
PV
DD
DV
DD
/ 2
37.5
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T
MIN
to T
MAX
, unless otherwise noted. TA> +25°C,
guaranteed by production test. T
A
< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
No interpolation, PLL enabled 165
2x interpolation, PLL enabled 75 150Clock Frequency at CLK Input f
CLK
4x interpolation, PLL enabled
75
MHz
Output Settling Time t
s
To ±0.1% error band (Note 2) 11 ns
Output Rise Time 10% to 90% (Note 2) 2.5 ns
Output Fall Time 90% to 10% (Note 2) 2.5 ns
PLL disabled 1.5
Data-to-CLK Rise Setup Time
(Note 3)
t
DCSR
PLL enabled 2.2
ns
PLL disabled 0.4
Data-to-CLK Rise Hold Time
(Note 3)
t
DCHR
PLL enabled 1.4
ns
PLL disabled 1.8
Data-to-CLK Fall Setup Time
(Note 3)
t
DCSF
PLL enabled 2.4
ns
PLL disabled 1.2
Data-to-CLK Fall Hold Time
(Note 3)
t
DCHF
PLL enabled 1.3
ns
Control Word to CW Fall Setup
Time
t
CWS
2.5 ns
Control Word to CW Fall Hold
Time
t
CWH
2.5 ns
CW High Time 5ns
CW Low Time 5ns
DACEN Rise-to-V
OUT
Stable t
STB
0.7 µs
PD Fall-to-V
OUT
Stable t
PDSTB
External reference 0.5 ms
Clock Frequency at
CLKXP/CLKXN Input
Differential clock, PLL disabled 300
MHz
CLKXP/CLKXN Differential Clock
Input to CLK Output Delay
t
CXD
PLL disabled 4.6 ns
Minimum CLKXP/CLKXN Clock
High Time
t
CXH
1.5 ns
Minimum CLKXP/CLKXN Clock
Low Time
t
CXL
1.5 ns
POWER REQUIREMENTS
Analog Power-Supply Voltage AV
DD
2.7 3.3 V
Analog Supply Current I
AVDD
(Note 4) 44 47 mA
Digital Power-Supply Voltage DV
DD
2.7 3.3 V
SYMBOL
f
CLKDIFF
MIN TYP MAX
37.5
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, f
DAC
= 165Msps, no interpolation, PLL disabled, external reference,
V
REFO
= 1.2V, IFS= 20mA, output amplitude = 0dB FS, differential output, TA= T
MIN
to T
MAX
, unless otherwise noted. TA> +25°C,
guaranteed by production test. T
A
< +25°C, guaranteed by design and characterization. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
No interpolation 43
2x interpolation 99f
DAC
= 60Msps
4x interpolation
No interpolation 53 58
2x interpolation
f
DAC
= 165Msps
4x interpolation
2x interpolation
178
Digital Supply Current (Note 4) I
DVDD
f
DAC
= 200Msps
4x interpolation
175
mA
PLL Power-Supply Voltage PV
DD
2.7 3.3 V
f
DAC
= 60Msps 16
f
DAC
= 165Msps 47 50
PLL Supply Current (Note 4) I
PVDD
f
DAC
= 200Msps, 2x interpolation or 4x
interpolation
55 60
mA
Standby Current
(Note 5) 4.4 4.8 mA
Power-Down Current I
PD
(Note 5) 1 µA
No interpolation
2x interpolation
f
DAC
= 60Msps
4x interpolation
No interpolation
456
2x interpolation
f
DAC
= 165Msps
4x interpolation
2x interpolation
Total Power Dissipation
(Note 4)
P
TOT
f
DAC
= 200Msps
4x interpolation
mW
Note 1: Including the internal reference voltage tolerance.
Note 2: Measured single ended with 50Ω load and complementary output connected to ground.
Note 3: Guaranteed by design, not production tested.
Note 4: Tested with an output frequency of f
OUT
= 5MHz.
Note 5: All digital inputs at 0 or DV
DD
. Clock signal disabled.
1.6V
5pF
TO OUTPUT PIN
0.5mA
0.5mA
Figure 1. Load Test Circuit for CLK Outputs
SYMBOL
MIN TYP MAX
104
I
STANDBY
147
147
165
162
309
477
492
432
714
714
792
783
MAX5856A
Dual 8-Bit, 300Msps DAC with 4x/2x/1x
Interpolation Filters and PLL
_______________________________________________________________________________________ 7
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(NO INTERPOLATION, f
DAC
= 165MHz)
MAX5856A toc01
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
807050 6020 30 4010
10
20
30
40
50
60
70
80
90
100
0
090
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL DISABLED
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(NO INTERPOLATION, f
DAC
= 65MHz)
MAX5856A toc02
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
3020 255 10 15
10
20
30
40
50
60
70
80
90
100
0
035
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL DISABLED
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(2x INTERPOLATION, f
DAC
= 300MHz)
MAX5856A toc04
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
706040 5010 20 30
10
20
30
40
50
60
70
80
90
100
0
080
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL ENABLED
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(2x INTERPOLATION, f
DAC
= 300MHz)
MAX5856A toc03
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
706040 5010 20 30
10
20
30
40
50
60
70
80
90
100
0
080
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL DISABLED
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(2x INTERPOLATION, f
DAC
= 165MHz)
MAX5856A toc05
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
403525 3010 15 205
10
20
30
40
50
60
70
80
90
100
0
045
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL DISABLED
Typical Operating Characteristics
(AVDD= DVDD= PVDD= 3V, AGND = DGND = PGND = 0, external reference = 1.2V, no interpolation, PLL disabled, IFS= 20mA,
differential output, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(4x INTERPOLATION, f
DAC
= 300MHz)
MAX5856A toc06
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
353020 255 10 15
10
20
30
40
50
60
70
80
90
100
0
040
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL DISABLED
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(4x INTERPOLATION, f
DAC
= 300MHz)
MAX5856A toc07
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
353020 255 10 15
10
20
30
40
50
60
70
80
90
100
0
040
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL ENABLED
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
(4x INTERPOLATION, f
DAC
= 165MHz)
MAX5856A toc08
OUTPUT FREQUENCY (MHz)
SFDR (dBc)
1812 153 6 9
10
20
30
40
50
60
70
80
90
100
0
021
A
OUT
= -6dBFS
A
OUT
= 0dBFS
A
OUT
= -12dBFS
PLL DISABLED
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