MAXIM MAX5854 Technical data

General Description

The MAX5854 dual, 10-bit, 165Msps digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte­grates two 10-bit DAC cores, and a 1.24V reference. The
MAX5854 supports single-ended and differential modes
of operation. The dynamic performance is maintained
over the entire 2.7V to 3.6V power-supply operating
range. The analog outputs support a -1.0V to +1.25V
compliance voltage.

The MAX5854 can operate in interleaved data mode to
reduce the I/O pin count. This allows the converter to
be updated on a single, 10-bit bus.

The MAX5854 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on­chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref­erence can be disabled and an external reference may
be applied for high-accuracy applications.

The MAX5854 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single sup­ply. The DAC supports three modes of power-control
operation: normal, low-power standby, and complete
power-down. In power-down mode, the operating
current is reduced to 1µA.

The MAX5854 is packaged in a 40-pin thin QFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.

Pin-compatible, lower speed, and lower resolution ver­sions are also available. Refer to the MAX5853 (10-bit,
80Msps), the MAX5852** (8-bit, 165Msps), and the
MAX5851** (8-bit, 80Msps) data sheets for more informa­tion. See Table 4 at the end of the data sheet.

Applications

Communications

SatCom, LMDS, MMDS, HFC, DSL, WLAN,

Point-to-Point Microwave Links
Wireless Base Stations
Quadrature Modulation
Direct Digital Synthesis (DDS)
Instrumentation/ATE

Features

♦ 10-Bit, 165Msps Dual DAC
♦ Low Power

190mW with IFS= 20mA at f

CLK

= 165MHz

♦ 2.7V to 3.6V Single Supply
♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

73dBc SFDR at f

OUT

= 40MHz

UMTS ACLR = 65.5dB at f

OUT

= 30.7MHz

♦ Programmable Channel Gain Matching
♦ Integrated 1.24V Low-Noise Bandgap Reference
♦ Single-Resistor Gain Control
♦ Interleaved Data Mode
♦ Single-Ended and Differential Clock Input Modes
♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm
♦ EV Kit Available—MAX5854 EV Kit

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3197; Rev 0; 2/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5854ETL -40°C to +85°C

40 Thin QFN-EP*

40 36373839

EP

18

21

23
22

24

25

19 2016 17

6

5

4

3

2

1

7
8
9
10

11

12

13

14

15

26

27

28

29

30

3132

33

3435

DA0

DB8

AGND

MAX5854

THIN QFN

TOP VIEW

AVDDOUTPA

OUTNA

AGND

OUTPB

OUTNB

AV

DD

REFR

REFO

DB9

DB6

DB7

DV

DD

DB5

DB4

DGND

DB2

DB3

CV

DD

CGND
CLK
CV

DD

CLKXN
CLKXP
DCE
CW
DB0
DB1

DA1

DA2/G0

DA3/G1

DA4/G2

DA5/G3

DA6/REN

DA7/IDE

DA8/DACEN

DA9/PD

Pin Configuration

*EP = Exposed paddle.

**Future product—contact factory for availability.

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, differential clock, external reference, V

REF

= 1.2V,

I

FS

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA≥ +25°C guaranteed by

production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDD, CVDDto AGND, DGND, CGND .........-0.3V to +4V

DA9–DA0, DB9–DB0,

CW, DCE to AGND,

DGND, CGND .......................................................-0.3V to +4V

CLKXN, CLKXP to CGND.........................................-0.3V to +4V

OUTP_, OUTN_ to AGND.......................-1.25V to (AV

DD

+ 0.3V)

CLK to DGND ..........................................-0.3V to (DVDD+ 0.3V)

REFR, REFO to AGND .............................-0.3V to (AVDD+ 0.3V)

AGND to DGND, DGND to CGND,

AGND to CGND..................................................-0.3V to +0.3V

Maximum Current into Any Pin

(excluding power supplies) ............................................±50mA

Continuous Power Dissipation (T

A

= +70°C)
40-Pin Thin QFN-EP (derate 23.3mW/°C

above +70°C)...............................................................1.860W

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

PARAMETER

CONDITIONS

UNITS

STATIC PERFORMANCE

Resolution N 10 Bits
Integral Nonlinearity INL RL = 0

LSB

Differential Nonlinearity DNL Guaranteed monotonic, RL = 0

LSB

Offset Error V

OS

LSB

Internal reference (Note1)

Gain Error (See Also Gain Error
Definition Section)

GE

External reference

%FSR

Internal reference

Gain-Error Temperature Drift

External reference

ppm/°C

DYNAMIC PERFORMANCE

f

OUT

= 10MHz

78

f

OUT

= 20MHz 77

f

CLK

= 165MHz,

A

OUT

= -1dBFS

f

OUT

= 40MHz 73

f

OUT

= 10MHz 77

f

OUT

= 20MHz 77

f

CLK

= 100MHz,

A

OUT

= -1dBFS

f

OUT

= 30MHz 76

Spurious-Free Dynamic Range to
Nyquist

SFDR

f

CLK

= 25MHz,

A

OUT

= -1dBFS

f

OUT

= 1MHz 79

dBc

f

CLK

= 165MHz, f

OUT

= 10MHz,

A

OUT

= -1dBFS, span = 10MHz

83

f

CLK

= 100MHz, f

OUT

= 5MHz,

A

OUT

= -1dBFS, span = 4MHz

84

Spurious-Free Dynamic Range
Within a Window

SFDR

f

CLK

= 25MHz, f

OUT

= 1MHz,

A

OUT

= -1dBFS, span = 2MHz

82

dBc

MTPR

8 tones at 400kHz spacing, f

CLK

= 78MHz,

f

OUT

= 15MHz to 18.2MHz

74 dBc

Multitone Power Ratio to Nyquist

SYMBOL

MIN TYP MAX

-1.0 ±0.25 +1.0

-0.5 ±0.2 +0.5

-0.5 ±0.1 +0.5

-11.0 ±1.5 +6.8

-6.25 ±0.7 +4.10
±150
±100

69.4

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, differential clock, external reference, V

REF

= 1.2V,

I

FS

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA≥ +25°C guaranteed by

production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

Multitone Spurious-Free Dynamic
Range Within a Window

8 tones at 2.1M H z sp aci ng ,
f

C LK

= 165M H z, f

OU T

= 28.3M H z to 45.2M H z,

sp an = 50M H z

70 dBc

Adjacent Channel Power Ratio
with UMTS

ACLR

f

OUT

= 30.72MHz, RBW = 30kHz,

f

CLK

= 122.88MHz

dB

f

OUT

= 10MHz -76

f

OUT

= 20MHz -74

f

CLK

= 165MHz,

A

OUT

= -1dBFS

f

OUT

= 40MHz -71

f

OUT

= 10MHz -75

f

OUT

= 20MHz -74

f

CLK

= 100MHz,

A

OUT

= -1dBFS

f

OUT

= 30MHz -73

Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)

THD

f

CLK

= 25MHz,

A

OUT

= -1dBFS

f

OUT

= 1MHz -76

dBc

Output Channel-to-Channel
Isolation

f

OUT

= 10MHz 90 dB

Channel-to-Channel Gain
Mismatch

f

OUT

= 10MHz, G[3:0] = 1000

dB

Channel-to-Channel Phase
Mismatch

f

OUT

= 10MHz

Degrees

f

C LK

= 165M Hz, f

OU T

= 10M H z, I

FS

= 20m A

f

CLK

= 165MHz, f

OUT

= 10MHz, I

FS

= 5mA 61

f

CLK

= 65MHz, f

OUT

= 10MHz, I

FS

= 20mA 62

Signal-to-Noise Ratio to Nyquist

SNR

f

CLK

= 65MHz, f

OUT

= 10MHz, I

FS

= 5mA 62

dB

Interleaved mode disabled, IDE = 0

Maximum DAC Conversion Rate

f

DAC

Interleaved mode enabled, IDE = 1

Msps

Glitch Impulse 5 pV-s
Output Settling Time t

S

To ±0.1% error band (Note 3) 12 ns
Output Rise Time 10% to 90% (Note 3) 2.2 ns
Output Fall Time 90% to 10% (Note 3) 2.2 ns

ANALOG OUTPUT

Full-Scale Output Current Range

I

FS

220mA

Output Voltage Compliance
Range

V

Output Leakage Current Shutdown or standby mode -5 +5 µA

REFERENCE

Internal-Reference Output
Voltage

V

REFO

REN = 0

V

SYMBOL

MIN TYP MAX

165 200

82.5 100

-1.00 +1.25

1.13 1.24 1.32

65.5

0.025

0.05

60.5

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, differential clock, external reference, V

REF

= 1.2V,

I

FS

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA≥ +25°C guaranteed by

production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

Internal-Reference Supply
Rejection

AV

DD

varied from 2.7V to 3.6V 0.5

mV/V

Internal-Reference Output­Voltage Temperature Drift

REN = 0

ppm/°C

Internal-Reference Output Drive
Capability

REN = 0 50 µA

External-Reference Input Voltage
Range

REN = 1

1.2

V

Current Gain

32

mA/mA

LOGIC INPUTS (DA9–DA0, DB9–DB0, CW)

Digital Input-Voltage High V

IH

0.65 x
V

Digital Input-Voltage Low V

IL

0.3 x
V

Digital Input Current I

IN

-1 +1 µA

Digital Input Capacitance C

IN

3pF

SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)

Digital Input-Voltage High V

IH

DCE = 1

0.65 x
V

Digital Input-Voltage Low V

IL

DCE = 1

0.3 x
V

Digital Input Current I

IN

DCE = 1 -1 +1 µA

Digital Input Capacitance C

IN

DCE = 1 3 pF

Digital Output-Voltage High V

OH

DCE = 0, I

SOURCE

= 0.5mA, Figure 1

V

Digital Output-Voltage Low V

OL

DCE = 0, I

SINK

= 0.5mA, Figure 1

0.1 x
V

DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal

Bias

V

Differential Clock Input Swing 0.5 V
Clock Input Impedance Measured single ended 5 kΩ

POWER REQUIREMENTS

Analog Power-Supply Voltage AV

DD

2.7 3 3.6 V

Digital Power-Supply Voltage DV

DD

2.7 3 3.6 V

Clock Power-Supply Voltage CV

DD

2.7 3 3.6 V

SYMBOL

MIN TYP MAX

TCV

REFO

IFS/I

REF

±50

0.10

DV

DD

CV

DD

0.9 x

CV

DD

1.32

DV

DD

CV

DD

CV

DD

CVDD/2

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, differential clock, external reference, V

REF

= 1.2V,

I

FS

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA≥ +25°C guaranteed by

production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

I

FS

= 20mA (Note 2), single-ended clock

mode

46

5

Analog Supply Current I

AVDD

I

FS

= 2mA (Note 2), differential clock mode 5

mA

I

FS

= 20mA (Note 2), single-ended clock

mode

6.2 7.5

Digital Supply Current I

DVDD

6.2

mA

Clock Supply Current I

CVDD

Differential clock mode (DCE = 0) (Note 2) 24

mA

Total Standby Current

I

AVDD

+ I

DVDD

+ I

CVDD

3.1 3.7 mA

Total Shutdown Current I

SHDNIAVDD

+ I

DVDD

+ I

CVDD

1µA

I

FS

= 20mA (Note 2)

Single-ended clock
mode (DCE = 1)

I

FS

= 2mA (Note 2) 75

I

FS

= 20mA (Note 2)

Differential clock
mode (DCE = 0)

I

FS

= 2mA (Note 2)

Standby 9.3

Total Power Dissipation P

TOT

Shutdown

mW

TIMING CHARACTERISTICS (Figure 5, Figure 6)

Propagation Delay 1

Clock

cycles

1.2

DAC Data to CLK Rise/Fall Setup
Time

t

DCS

Differential clock mode (DCE = 0) (Note 4) 2.7

ns

0.8

DAC Data to CLK Rise/Fall Hold
Time

t

DCH

Differential clock mode (DCE = 0) (Note 4)

ns

Control Word to CW Rise Setup
Time

t

CS

2.5 ns

Control Word to CW Rise Hold
Time

t

CW

2.5 ns

CW High Time t

CWH

5ns

CW Low Time t

CWL

5ns

DACEN = 1 to V

OUT

Stable Time

(Coming Out of Standby)

t

STB

3µs

SYMBOL

I

= 20mA (Note 2), differential clock mode 43.2

FS

I

= 2mA (Note 2), single-ended clock mode

FS

I

= 20mA (Note 2), differential clock mode

FS

Single-ended clock mode (DCE = 1) (Note 2) 13.7 16.5

I

STANDBY

Single-ended clock mode (DCE = 1) (Note 4)

Single-ended clock mode (DCE = 1) (Note 4)

MIN TYP MAX

43.2

190 210

220
106

11.1

0.003

-0.5

MAX5854

Dual, 10-Bit, 165Msps, Current-Output DAC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 165Msps, differential clock, external reference, V

REF

= 1.2V,

I

FS

= 20mA, output amplitude = 0dB FS, differential output, TA= T

MIN

to T

MAX

, unless otherwise noted. TA≥ +25°C guaranteed by

production test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PD = 0 to V

OUT

Stable Time

(Coming Out of Power-Down)

t

SHDN

µs

Maximum Clock Frequency at
CLKXP/CLKXN Input

f

CLK

MHz

Clock High Time t

CXH

CLKXP or CLKXN input 1.5 ns

Clock Low Time t

CXL

CLKXP or CLKXN input 1.5 ns

CLKXP Rise to CLK Output Rise
Delay

t

CDH

DCE = 0 2.7 ns

CLKXP Fall to CLK Output Fall
Delay

t

CDL

DCE = 0 2.7 ns

Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: f

DAC

= 165Msps, f

OUT

= 10MHz.

Note 3: Measured single-ended with 50Ω load and complementary output connected to AGND.
Note 4: Guaranteed by design, not production tested.

TO OUTPUT

PIN

5pF

0.5mA

0.5mA

1.6V

Figure 1. Load Test Circuit for CLK Outputs

500

165 200