MAXIM MAX5851 Technical data

General Description

The MAX5851 dual, 8-bit, 80Msps, digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte­grates two 8-bit DAC cores, and a 1.24V reference. The
converter supports single-ended and differential modes
of operation. The MAX5851 dynamic performance is
maintained over the entire 2.7V to 3.6V power-supply
operating range. The analog outputs support a -1.0V to
+1.25V compliance voltage.

The MAX5851 can also operate in interleave data mode
to reduce the I/O pin count. This allows the converter to
be updated on a single, 8-bit bus.

The MAX5851 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on­chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref­erence can be disabled and an external reference may
be applied for high-accuracy applications.

The MAX5851 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single supply.
The DAC supports three modes of power-control opera­tion: normal, low-power standby, and complete power­down. In power-down mode, the operating current is
reduced to 1µA.

The MAX5851 is packaged in a 40-pin thin QFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.

Pin-compatible, higher speed, and higher resolution
versions are also available. Refer to the MAX5852
(8 bit, 165Msps), the MAX5854 (10 bit, 165Msps), and
the MAX5853 (10 bit, 80Msps) data sheets for more
information. See Table 4.

Applications

Communications

VSAT, LMDS, MMDS, WLAN,

Point-to-Point Microwave Links
Wireless Base Stations
Quadrature Modulation
Direct Digital Synthesis (DDS)
Instrumentation/ATE

Features

♦ 8-Bit, 80Msps Dual DAC
♦ Low Power

58mW with IFS= 2mA at f

CLK

= 80MHz

♦ 2.7V to 3.6V Single Supply
♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

66dBc SFDR at f

OUT

= 20MHz

♦ Programmable Channel Gain Matching
♦ Integrated 1.24V Low-Noise Bandgap Reference
♦ Single-Resistor Gain Control
♦ Interleaved Data Mode
♦ Single-Ended and Differential Clock Input Modes
♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm
♦ EV Kit Available—MAX5852 EV Kit

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3231; Rev 0; 4/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5851ETL -40°C to +85°C

40 Thin QFN-EP*

40 36373839

EP

18

21

23
22

24

25

19 2016 17

6

5

4

3

2

1

7
8
9

10

11

12

13

14

15

26

27

28

29

30

3132

33

3435

N.C.

DB6

AGND

MAX5851

THIN QFN

TOP VIEW

AVDDOUTPA

OUTNA

AGND

OUTPB

OUTNB

AV

DD

REFR

REFO

DB7

DB4

DB5

DV

DD

DB3

DB2

DGND

DB0

DB1

CV

DD

CGND
CLK
CV

DD

CLKXN
CLKXP
DCE
CW
N.C.
N.C.

N.C.

DA0/G0

DA1/G1

DA2/G2

DA3/G3

DA4/REN

DA5/IDE

DA6/DACEN

DA7/PD

Pin Configuration

*EP = Exposed paddle.

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto AGND .........................................................-0.3V to +4V

DV

DD

to DGND.........................................................-0.3V to +4V

CV

DD

to CGND.........................................................-0.3V to +4V

AV

DD

to DVDD.............................................................-4V to +4V

AV

DD

to CVDD..........................................................-0.4V to +4V

DV

DD

to CVDD..........................................................-0.4V to +4V

AGND to DGND.....................................................-0.3V to +0.3V

AGND to CGND.....................................................-0.3V to +0.3V

DGND to CGND ....................................................-0.3V to +0.3V

DA7–DA0, DB7–DB0,

CW, DCE to DGND ...............-0.3V to +4V

CLK to CGND ..........................................-0.3V to (CV

DD

+ 0.3V)

CLKXN, CLKXP to CGND.........................................-0.3V to +4V

REFR, REFO to AGND .............................-0.3V to (AV

DD

+ 0.3V)

OUTPA, OUTNA to AGND..........(AV

DD

- 4.8V) to (AVDD+ 0.3V)

OUTPB, OUTNB to AGND..........(AV

DD

- 4.8V) to (AVDD+ 0.3V)

Maximum Current into Any Pin

(excluding power supplies)..........................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

40-Pin Thin QFN (derate 26.3mW/°C above +70°C)....2105mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution N 8 Bits
Integral Nonlinearity INL RL = 0

LSB

Differential Nonlinearity DNL Guaranteed monotonic, RL = 0

LSB

Offset Error V

OS

LSB

Internal reference (Note1) -10

+8

Gain Error (See Also Gain Error
Definition Section)

GE

External reference

%FSR

Internal reference

Gain-Error Temperature Drift

External reference

ppm/°C

DYNAMIC PERFORMANCE

f

OUT

= 10MHz

f

OUT

= 20MHz 66

f

CLK

= 80MHz,

A

OUT

= -1dBFS

f

OUT

= 30MHz 65

f

CLK

= 44MHz,

A

OUT

= -1dBFS

f

OUT

= 10MHz 63

Spurious-Free Dynamic Range to
Nyquist

SFDR

f

CLK

= 25MHz,

A

OUT

= -1dBFS

f

OUT

= 1MHz 64

dBc

f

CLK

= 80MHz, f

OUT

= 10MHz,

A

OUT

= -1dBFS, span = 10MHz

70

f

CLK

= 65MHz, f

OUT

= 5MHz,

A

OUT

= -1dBFS, span = 2.5MHz

68

Spurious-Free Dynamic Range
Within a Window

SFDR

f

CLK

= 25MHz, f

OUT

= 1MHz,

A

OUT

= -1dBFS, span = 2MHz

67

dBc

Multitone Power Ratio to Nyquist

MTPR

8 tones at 400kHz spacing, f

CLK

= 78MHz,

f

OUT

= 15MHz to 18.2MHz

63 dBc

-0.25 ±0.05 +0.25

-0.15 ±0.05 +0.15

-0.1 ±0.2 +0.1
±1.5

-5.5 ±0.7 +5.0

±150
±100

63.3 66.5

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

Multitone Spurious-Free Dynamic
Range Within a Window

8 tones at 811kH z sp aci ng , f

C LK

= 80M H z,

61 dBc

f

OUT

= 10MHz -72

f

OUT

= 20MHz -74

f

CLK

= 80MHz,

A

OUT

= -1dBFS

f

OUT

= 30MHz -69

f

CLK

= 44MHz,

A

OUT

= -1dBFS

f

OUT

= 10MHz -73

Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)

THD

f

CLK

= 25MHz,

A

OUT

= -1dBFS

f

OUT

= 1MHz -69

dBc

Output Channel-to-Channel
Isolation

f

OUT

= 10MHz 90 dB

Channel-to-Channel Gain
Mismatch

f

OUT

= 10MHz, G[3:0] = 1000

dB

Channel-to-Channel Phase
Mismatch

f

OUT

= 10MHz

Degrees

f

CLK

= 80MHz, f

OUT

= 5MHz, I

FS

= 20mA 51

Signal-to-Noise Ratio to Nyquist SNR

f

CLK

= 80MHz, f

OUT

= 5MHz, I

FS

= 5mA

dB

Interleaved mode disabled, IDE = 0 80

Maximum DAC Conversion Rate

f

DAC

Interleaved mode enabled, IDE = 1 80

Msps

Glitch Impulse 5

pV•s

Output Settling Time t

S

To ±0.1% error band (Note 3) 12 ns
Output Rise Time 10% to 90% (Note 3) 2.2 ns
Output Fall Time 90% to 10% (Note 3) 2.2 ns

ANALOG OUTPUT

Full-Scale Output Current Range

I

FS

220mA

Output Voltage Compliance
Range

V

Output Leakage Current Shutdown or standby mode -5 +5 µA

REFERENCE

Internal-Reference Output
Voltage

V

REFO

REN = 0

V

Internal-Reference Supply
Rejection

AV

DD

varied from 2.7V to 3.6V 0.5

mV/V

Internal-Reference Output­Voltage Temperature Drift

REN = 0

ppm/°C

SYMBOL

f

OU T

TCV

REFO

= 10.8M H z to 17.2M H z, sp an = 15M H z

MIN TYP MAX

0.025

0.05

50.3

-1.00 +1.25

1.13 1.24 1.32

±50

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Internal-Reference Output Drive
Capability

REN = 0 50 µA

External-Reference Input Voltage
Range

REN = 1

1.2

V

Current Gain

32

mA/mA

LOGIC INPUTS (DA7–DA0, DB7–DB0, CW)

Digital Input-Voltage High V

IH

V

Digital Input-Voltage Low V

IL

0.3 x
V

Digital Input Current I

IN

-1 +1 µA

Digital Input Capacitance C

IN

3pF

SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)

Digital Input-Voltage High V

IH

DCE = 1

0.65 x
V

Digital Input-Voltage Low V

IL

DCE = 1

0.3 x
V

Digital Input Current I

IN

DCE = 1 -1 +1 µA

Digital Input Capacitance C

IN

DCE = 1 3 pF

Digital Output-Voltage High V

OH

DCE = 0, I

SOURCE

= 0.5mA, Figure 1

V

Digital Output-Voltage Low V

OL

DCE = 0, I

SINK

= 0.5mA, Figure 1

V

DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal

Bias

CV

DD

/ 2 V

Differential Clock Input Swing 0.5 V
Clock Input Impedance Measured single ended 5 kΩ

POWER REQUIREMENTS

Analog Power-Supply Voltage AV

DD

2.7 3 3.6 V

Digital Power-Supply Voltage DV

DD

2.7 3 3.6 V

Clock Power-Supply Voltage CV

DD

2.7 3 3.6 V

I

FS

= 20mA, single-ended clock mode 43 46

I

FS

= 20mA, differential clock mode 43

I

FS

= 2mA, single-ended clock mode 5

Analog Supply Current (Note 2) I

AVDD

I

FS

= 2mA, differential clock mode 5

mA

IFS/I

REF

0.10

0.65 x
DV

DD

CV

DD

0.9 x

CV

DD

1.32

DV

CV

0.1 x

CV

DD

DD

DD

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

I

FS

= 20mA, single-ended clock mode 3 3.8

Digital Supply Current (Note 2) I

DVDD

I

FS

= 20mA, differential clock mode 3

mA

Single-ended clock mode (DCE = 1)

Clock Supply Current (Note 2) I

CVDD

Differential clock mode (DCE = 0)

mA

Total Standby Current

I

AVDD

+ I

DVDD

+ I

CVDD

3.1 3.7 mA

Total Shutdown Current I

SHDNIAVDD

+ I

DVDD

+ I

CVDD

1µA

I

FS

= 20mA

190

Single-ended clock
mode (DCE = 1)

I

FS

= 2mA 58

I

FS

= 20mA

Differential clock
mode (DCE = 0)

I

FS

= 2mA 74

Standby 9.3

Total Power Dissipation (Note 2)

P

TOT

Shutdown

mW

TIMING CHARACTERISTICS (Figures 5 and 6)

Propagation Delay 1

Clock

cycles

Single-ended clock mode (DCE = 1) 1.2

DAC Data to CLK Rise/Fall
Setup Time (Note 4)

t

DCS

Differential clock mode (DCE = 0) 2.7

ns

Single-ended clock mode (DCE = 1) 0.8

DAC Data to CLK Rise/Fall
Hold Time (Note 4)

t

DCH

Differential clock mode (DCE = 0)

ns

Control Word to CW Rise
Setup Time

t

CS

2.5 ns

Control Word to CW Rise
Hold Time

t

CW

2.5 ns

CW High Time t

CWH

5ns

CW Low Time t

CWL

5ns

SYMBOL

I

STANDBY

MIN TYP MAX

11.2 13.5

16.5

172

188

11.1

0.003

-0.5

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

DACEN = 1 to V

OUT

Stable Time

(Coming Out of Standby)

t

STB

3µs

PD = 0 to V

OUT

Stable Time

(Coming Out of Power-Down)

t

SHDN

µs

Maximum Clock Frequency at
CLKXP/CLKXN Input

f

CLK

80

MHz

Clock High Time t

CXH

CLKXP or CLKXN input 3 ns

Clock Low Time t

CXL

CLKXP or CLKXN input 3 ns

CLKXP Rise to CLK Output
Rise Delay

t

CDH

DCE = 0 2.7 ns

CLKXP Fall to CLK Output
Fall Delay

t

CDL

DCE = 0 2.7 ns

Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: f

DAC

= 80Msps, f

OUT

= 10MHz.

Note 3: Measured single ended with 50Ω load and complementary output connected to ground.
Note 4: Guaranteed by design, not production tested.

TO OUTPUT

PIN

5pF

0.5mA

0.5mA

1.6V

Figure 1. Load Test Circuit for CLK Outputs

SYMBOL

MIN TYP MAX

500

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

_______________________________________________________________________________________ 7

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 80MHz)

MAX5851 toc01

f

OUT

(MHz)

SFDR (dBc)

353020 2510 155

35

40

45

50

55

60

65

70

75

80

30

040

0dBFS

-6dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 65MHz)

MAX5851 toc02

f

OUT

(MHz)

SFDR (dBc)

302515 20105

35

40

45

50

55

60

65

70

75

80

30

035

0dBFS

-6dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 44MHz)

MAX5851 toc03

f

OUT

(MHz)

SFDR (dBc)

201814 164 6 8 10 122

35

40

45

50

55

60

65

70

75

80

30

022

0dBFS

-6dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 25MHz)

MAX5851 toc04

f

OUT

(MHz)

SFDR (dBc)

12106 842

35

40

45

50

55

60

65

70

75

80

30

014

0dBFS

-6dBFS

-12dBFS

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 80MHz)

MAX5851 toc05

f

OUT

(MHz)

SFDR (dBc)

353020 2510 155

35

40

45

50

55

60

65

70

75

80

30

040

IFS = 20mA

IFS = 5mA

IFS = 10mA

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 80MHz)

MAX5851 toc06

f

OUT

(MHz)

SFDR (dBc)

363224 288 12 16 204

35

40

45

50

55

60

65

70

75

80

30

040

AVDD = DVDD = CVDD = 2.7V

AVDD = DVDD = CVDD = 3.6V

AVDD = DVDD = CVDD = 3.3V

AVDD = DVDD = CVDD = 3V

SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE (f

CLK

= 80MHz)

MAX5851 toc07

TEMPERATURE (°C)

SFDR (dBc)

603510-15

35

40

45

50

55

60

65

70

75

80

30

-40 85

Typical Operating Characteristics

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, external reference, IFS= 20mA, differential output, differential clock,
TA= +25°C, unless otherwise noted.)

TWO-TONE INTERMODULATION DISTORTION

(f

CLK

= 80MHz, 2.5MHz WINDOW)

MAX5851 toc08

f

OUT

(MHz)

AMPLITUDE (dBm)

5.85.34.84.3

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-100

3.8 6.3

f

OUT1

= 4.904MHz

f

OUT2

= 5.021MHz

f

OUT2

f

OUT1

2f

OUT1

- f

OUT2

2f

OUT2

- f

OUT1

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, external reference, IFS= 20mA, differential output, differential clock,
TA= +25°C, unless otherwise noted.)

SINGLE-TONE SFDR

(f

CLK

= 80MHz, 10MHz WINDOW)

MAX5851 toc10a

f

OUT

(MHz)

AMPLITUDE (dBm)

141311 12789106

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-100
515

f

OUT

= 9.941MHz

A

OUT

= -1dBFS

SINGLE-TONE SFDR

(f

CLK

= 80MHz, NYQUIST WINDOW)

MAX5851 toc10b

f

OUT

(MHz)

AMPLITUDE (dBm)

4MHz/div

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-120
040

f

OUT

= 9.9359MHz

A

OUT

= -1dBFS

SINGLE-TONE SFDR

(f

CLK

= 25MHz, 2MHz WINDOW)

MAX5851 toc12

f

OUT

(MHz)

AMPLITUDE (dBm)

1.91.61.1 1.40.6 0.90.4

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-100

0.1 2.1

f

OUT

= 0.9949MHz

A

OUT

= -1dBFS

SINGLE-TONE SFDR

(f

CLK

= 44MHz, 2.5MHz WINDOW)

MAX5851 toc11

f

OUT

(MHz)

AMPLITUDE (dBm)

5.85.34.84.3

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-100

3.8 6.3

f

OUT

= 4.9736MHz

A

OUT

= -1dBFS

EIGHT-TONE SFDR PLOT

(f

CLK

= 80MHz, 15MHz WINDOW)

MAX5851 toc09

f

OUT

(MHz)

AMPLITUDE (dBm)

18.515.512.59.5

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

-100

6.5 21.5

f

T4

f

T3

f

T2

f

T1

f

T5

f

T6

f

T7

f

T8

fT1 = 10.6836MHz
f

T2

= 11.5820MHz

f

T3

= 12.3292MHz

f

T4

= 13.2227MHz

f

T5

= 14.8633MHz

f

T6

= 15.5664MHz

f

T7

= 16.3867MHz

f

T8

= 17.2461MHz

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

_______________________________________________________________________________________ 9

REFERENCE VOLTAGE

vs. TEMPERATURE

MAX5851 toc18

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

603510-15

1.242

1.244

1.246

1.248

1.250

1.252

1.254

1.256

1.258

1.260

1.240

-40 85

DYNAMIC RESPONSE RISE TIME

MAX5851 toc19

10ns/div

100mV/div

DYNAMIC RESPONSE FALL TIME

MAX5851 toc20

10ns/div

100mV/div

SPURIOUS-FREE DYNAMIC RANGE

vs. OUTPUT FREQUENCY (f

CLK

= 80MHz)

MAX5851 toc21

f

OUT

(MHz)

SFDR (dBc)

353020 2510 155

35

40

45

50

55

60

65

70

75

80

30

040

0dBFS

-6dBFS

-12dBFS

SINGLE-ENDED
CLOCK DRIVE

Typical Operating Characteristics (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, external reference, IFS= 20mA, differential output, differential clock,
TA= +25°C, unless otherwise noted.)

INTEGRAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5851 toc13

DIGITAL INPUT CODE

INL (LSB)

22419232 64 96 128 160

-0.15

-0.10

-0.05

0

0.05

0.10

0.15

0.20

-0.20
0 256

DIFFERENTIAL NONLINEARITY

vs. DIGITAL INPUT CODE

MAX5851 toc14

DIGITAL INPUT CODE

DNL (LSB)

22419232 64 96 128 160

-0.08

-0.05

-0.03

0

0.03

0.05

0.08

0.10

-0.10
0 256

POWER DISSIPATION vs. CLOCK FREQUENCY

(f

OUT

= 10MHz, A

OUT

= 0dBFS)

MAX5815 toc15

f

CLK

(MHz)

POWER DISSIPATION (mW)

7060504030

155

160

165

170

175

180

185

190

195

200

150

20 80

DIFFERENTIAL

CLOCK DRIVE

SINGLE-ENDED
CLOCK DRIVE

POWER DISSIPATION vs. SUPPLY VOLTAGES

(f

CLK

= 80MHz, f

OUT

= 10MHz)

MAX5851 toc16

SUPPLY VOLTAGES (V)

POWER DISSIPATION (mW)

3.453.303.153.002.85

160

170

180

190

200

210

220

150

2.70 3.60

DIFFERENTIAL

CLOCK DRIVE

SINGLE-ENDED
CLOCK DRIVE

REFERENCE VOLTAGE

vs. SUPPLY VOLTAGES

MAX5851 toc17

SUPPLY VOLTAGES (V)

REFERENCE VOLTAGE (V)

3.453.303.153.002.85

1.25120

1.25130

1.25140

1.25150

1.25160

1.25110

2.70 3.60

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 DA7/PD Channel A Input Data Bit 7 (MSB)/Power-Down
2

Channel A Input Data Bit 6/DAC Enable Control

3 DA5/IDE Channel A Input Data Bit 5/Interleaved Data Enable

4

Channel A Input Data Bit 4/Reference Enable. Setting REN = 0 enables the internal reference. Setting
REN = 1 disables the internal reference.

5 DA3/G3 Channel A Input Data Bit 3/Channel A Gain Adjustment Bit 3
6 DA2/G2 Channel A Input Data Bit 2/Channel A Gain Adjustment Bit 2
7 DA1/G1 Channel A Input Data Bit 1/Channel A Gain Adjustment Bit 1
8 DA0/G0 Channel A Input Data Bit 0 (LSB)/Channel A Gain Adjustment Bit 0

9, 10,

21, 22

N.C. No Connection. Do not connect to these pins.

11 DB7 Channel B Input Data Bit 7 (MSB)
12 DB6 Channel B Input Data Bit 6
13 DB5 Channel B Input Data Bit 5
14 DB4 Channel B Input Data Bit 4
15 DB3 Channel B Input Data Bit 3
16 DV

DD

D i g i tal P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.
17 DGND Digital Ground
18 DB2 Channel B Input Data Bit 2
19 DB1 Channel B Input Data Bit 1
20 DB0 Channel B Input Data Bit 0 (LSB)
23 CW Active-Low Control Word Write Pulse. The control word is latched on the rising edge of CW.

24 DCE

Active-Low Differential Clock Enable Input. Drive DCE low to enable differential clock inputs

CLKXP and CLKXN. Drive DCE high to disable the differential clock inputs and enable the single-

ended CLK input.

25 CLKXP

Positive Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP

and CLKXN are disabled. Connect CLKXP to CGND when the differential clock is disabled.

26 CLKXN

Negative Differential Clock Input. With DCE = 0, CLKXP and CLKXN are enabled. With DCE = 1, CLKXP

and CLKXN are disabled. Connect CLKXN to CV

DD

when the differential clock is disabled.

27, 30 CV

DD

C l ock P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.

28 CLK

Single-Ended Clock Input/Output. With the differential clock disabled (DCE = 1), CLK becomes a

single-ended conversion clock input. With the differential clock enabled (DCE = 0), CLK is a single-

ended output that mirrors differential clock inputs CLKXP and CLKXN. See the Clock Modes section for

more information on CLK.
29 CGND Clock Ground

31 REFO

Reference Input/Output. REFO serves as a reference input when the internal reference is disabled. If the

internal 1.24V reference is enabled, REFO serves as an output for the internal reference. When the

internal reference is enabled, bypass REFO to AGND with a 0.1µF capacitor.

DA6/DACEN

DA4/REN

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

______________________________________________________________________________________ 11

Detailed Description

The MAX5851 dual, high-speed, 8-bit, current-output
DAC provides superior performance in communication
systems requiring low-distortion analog-signal recon­struction. The MAX5851 combines two DACs and an on­chip 1.24V reference (Figure 2). The current outputs of
the DACs can be configured for differential or single­ended operation. The full-scale output current range is
adjustable from 2mA to 20mA to optimize power dissi­pation and gain control.

The MAX5851 accepts an input data and a DAC con­version rate of 80MHz. The inputs are latched on the
rising edge of the clock whereas the output latches on
the following rising edge.

The MAX5851 features three modes of operation: normal,
standby, and power-down (Table 2). These modes allow
efficient power management. In power-down, the
MAX5851 consumes only 1µA of supply current. Wake­up time from standby mode to normal DAC operation
is 3µs.

Programming the DAC

An 8-bit control word routed through channel A’s data
port programs the gain matching, reference, and the
operational mode of the MAX5851. The control word is
latched on the rising edge of CW. CW is independent
of the DAC clock. The DAC clock can always remain
running when the control word is written to the DAC.
Table 1 and Table 2 represent the control word format
and function.

The gain on channel A can be adjusted to achieve gain
matching between two channels in a user’s system.
The gain on channel A can be adjusted from -0.4dB to
+0.35dB in steps of 0.05dB by using bits G3 to G0 (see
Table 3).

Pin Description (continued)

PIN NAME FUNCTION

32 REFR

Full-Scale Current Adjustment. To set the output full-scale current, connect an external resistor R

SET

between REFR and AGND. The output full-scale current is equal to 32 x V

REFO/RSET

.

33, 39 AV

DD

Anal og P ow er Inp ut. S ee the P ow er S up p l i es, Byp assi ng , D ecoup l i ng , and Layout secti on for m or e d etai l s.

34 OUTNB Channel B Negative Analog Current Output
35 OUTPB Channel B Positive Analog Current Output

36, 40 AGND Analog Ground

37 OUTNA Channel A Negative Analog Current Output
38 OUTPA Channel A Positive Analog Current Output

—EPExposed Paddle. Connect EP to the common point of all ground planes.

Figure 2. Simplified Diagram

DV

DD

DGND

CW

DA0/G0
DA1/G1
DA2/G2
DA3/G3

DA4/REN

DA5/IDE

DA6/DACEN

DA7/PD

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DCE
CLKXP
CLKXN

CLK

CV

DD

CGND

DIGITAL
POWER

MANAGEMENT

MAX5851

8-BIT

DACA

CONTROL WORD

DACA INPUT REGISTER

INPUT DATA

INTERLEAVER

DACB INPUT REGISTER

CLOCK

DISTRIBUTION

CLOCK
POWER

MANAGEMENT

CHANNEL A

GAIN

CONTROL

OPERATING

MODE

CONTROLLER

8-BIT

DACB

ANALOG

POWER

MANAGEMENT

IDE

1.24V REFERENCE
AND CONTROL

AMPLIFIER

REN

G0
G1
G2
G3

DACEN
PD

OUTPA
OUTNA

OUTPB
OUTNB

REFO

REFR

AV

AGND

AGND

DD

R

SET

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

12 ______________________________________________________________________________________

Device Power-Up and

States of Operation

At power-up, the MAX5851’s default configuration is inter­nal reference, noninterleaved input mode with a gain of
0dB and a fully operational converter. In shutdown, the
MAX5851 consumes only 1µA of supply current, and in
standby the current consumption is 3.1mA. Wake-up time
from standby mode to normal operation is 3µs.

Clock Modes

The MAX5851 allows both single-ended CMOS and dif­ferential clock mode operation, and supports update
rates of up to 80Msps. These modes are selected
through an active-low control line called DCE. In single­ended clock mode (DCE = 1), the CLK pin functions as
an input, which accepts a user-provided single-ended
clock signal. Data is written to the converter on the rising
edge of the clock. The DAC outputs (previous data) are
updated simultaneously on the same edge.

If the DCE pin is pulled low, the MAX5851 operates in
differential clock mode. In this mode, the clock signal
has to be applied to differential clock input pins
CLKXP/CLKXN. The differential input accepts an input
range of ≥0.5V

P-P

and a common-mode range of 1V to
(CVDD- 0.5V), making the part ideal for low-input ampli­tude clock drives. CLKXP/CLKXN also help to minimize
the jitter, and allow the user to connect a crystal oscilla­tor directly to the MAX5851.

The CLK pin now becomes an output, and provides a sin­gle-ended replica of the differential clock signal, which
may be used to synchronize the input data. Data is writ­ten to the device on the rising edge of the CLK signal.

CONTROL WORD

FUNCTION

PD Power-Down. The part enters power-down mode if PD = 1.

DACEN DAC Enable. When DACEN = 0 and PD = 0, the part enters standby mode.

IDE

Interleaved Data Mode. IDE = 1 enables the interleaved data mode. In this mode, digital data for both
channels is applied through channel A in a multiplexed fashion. Channel B data is written on the falling edge
of the clock signal and channel A data is written on the rising edge of the clock signal.

REN

Reference Enable Bit. REN = 0 activates the internal reference. REN = 1 disables the internal reference and
requires the user to apply an external reference between 0.1V to 1.32V.

G3 Bit 3 (MSB) of Gain Adjust Word
G2 Bit 2 of Gain Adjust Word
G1 Bit 1 of Gain Adjust Word
G0 Bit 0 (LSB) of Gain Adjust Word

Table 1. Control Word Format and Function

GAIN ADJUSTMENT ON

CHANNEL A (dB)

G3G2G1

G0

+0.4 0000

0 1000

-0.35 1111

Table 3. Gain Difference Setting

X = Don’t care.

MSB LSB

PD DACEN IDE REN G3 G2 G1 G0

Table 2. Configuration Modes

MODE

REN

Normal operation;
noninterleaved inputs;
internal reference active

0100

Normal operation;
noninterleaved inputs;
internal reference disabled

0101

Normal operation;
interleaved inputs;
internal reference disabled

0111

Standby 0 0

X

Power-down 1 X

X

Power-up 0 1

X

PD DACEN IDE

X
X
X

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

______________________________________________________________________________________ 13

I

FS

C

COMP

*

REFR

I

REF

REFO

MAX4040

1.24V

BANDGAP

REFERENCE

CURRENT-

SOURCE

ARRAY

*COMPENSATION CAPACITOR (C

COMP

≈ 100nF)

OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS

MAX5851

I

REF

=

V

REF

R

SET

R

SET

AGND

AGND

REN = 0

Figure 3. Setting IFSwith the Internal 1.24V Reference and the
Control Amplifier

Internal Reference and Control Amplifier

The MAX5851 provides an integrated 50ppm/°C, 1.24V,
low-noise bandgap reference that can be disabled and
overridden with an external reference voltage. REFO
serves either as an external reference input or an inte­grated reference output. If REN = 0, the internal refer­ence is selected and REFO provides a 1.24V (50µA)
output. Buffer REFO with an external amplifier when dri­ving a heavy load.

The MAX5851 also employs a control amplifier
designed to simultaneously regulate the full-scale out­put current (IFS) for both outputs of the devices.
Calculate the output current as:

IFS= 32 ✕ I

REF

where I

REF

is the reference output current (I

REF

=

V

REFO

/ R

SET

) and IFSis the full-scale output current. R

SET

is the reference resistor that determines the amplifier out­put current of the MAX5851 (Figure 3). This current is mir­rored into the current-source array where IFSis equally
distributed between matched current segments and
summed to valid output current readings for the DACs.

External Reference

To disable the internal reference of the MAX5851, set
REN = 1. Apply a temperature-stable, external reference
to drive the REFO pin and set the full-scale output
(Figure 4). For improved accuracy and drift performance,
choose a fixed-output voltage reference such as the

1.2V, 25ppm/°C MAX6520 bandgap reference.

Detailed Timing

The MAX5851 accepts an input data and DAC con­version rate of up to 80Msps. The input latches on the
rising edge of the clock, whereas the output latches
on the following rising edge.

Figure 5 depicts the write cycle of the two DACs in non­interleaved mode.

The MAX5851 can also operate in an interleaved data
mode. Programming the IDE bit with a high level activates
this mode (Tables 1 and 2). In interleaved mode, data for
both DAC channels is written through input port A.
Channel B data is written on the falling edge of the clock
signal and then channel A data is written on the following
rising edge of the clock signal. Both DAC outputs (chan­nel A and B) are updated simultaneously on the next fol­lowing rising edge of the clock. The interleaved data
mode is attractive for applications where lower data rates
are acceptable and interfacing on a single 8-bit bus is
desired (Figure 6).

AV

DD

EXTERNAL

1.2V

REFERENCE

MAX6520

AGND

0.1µF10µF

AV

DD

AGND

I

FS

REFR

I

REF

REFO

1.24V

BANDGAP

REFERENCE

CURRENT-

SOURCE

ARRAY

MAX5851

R

SET

AGND

REN = 1

Figure 4. MAX5851 with External Reference

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

14 ______________________________________________________________________________________

CLKXN

CLKXP

CLK

OUTPUT

CW

DA0–DA7

OUTPA

OUTNA

OUTPB

OUTNB

t

CXL

t

CXH

t

CDH

t

CDL

t

DCStDCH

t

DCStDCH

tCSt

CW

t

CWL

DACA DACB + 1 DACA + 1

CONTROL

WORD

DACB + 2 DACA + 2

DACA - 1

DACB - 1

DACA

DACB

DACA + 1

DACB + 1

Figure 6. Timing Diagram for Interleaved Data Mode (IDE = 1)

CLKXN

CLKXP

CLK

OUTPUT

CW

DA0–DA7

OUTPA

OUTNA

DB0–DB7

OUTPB

OUTNB

DACA - 1

DACB - 1

DACA

DACB

DACA + 1

DACB + 1

DACA + 2

DACB + 2

CONTROL

WORD

XXXX

DACA + 3

DACB + 3

DACA - 1

DACB - 1

DACA

DACB

DACA + 1

DACB + 1

DACA + 2

DACB + 2

XXXX

(CONTROL WORD DATA)

XXXX

DACA + 3

DACB + 3

t

CXHtCXL

t

CDH

t

CDL

t

DCStDCH

t

DCStDCH

t

CWL

tCSt

CW

Figure 5. Timing Diagram for Noninterleaved Data Mode (IDE = 0)

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

______________________________________________________________________________________ 15

DA0–DA7

8

MAX5851

1/2

50Ω

100Ω

50Ω

OUTPA

OUTNA

V

OUTA

,

SINGLE ENDED

DB0–DB7

8

MAX5851

1/2

50Ω

100Ω

50Ω

OUTPB

OUTNB

V

OUTB

,

SINGLE ENDED

CV

DD

DV

DD

AV

DD

CGNDDGNDAGND

Figure 7. Application with Output Transformer (Coilcraft
TTWB3010-1) Performing Differential-to-Single-Ended Conversion

DA0–DA7

8

MAX5851

1/2

1/2

50Ω

50Ω

CV

DD

DV

DD

AV

DD

CGNDDGNDAGND

OUTPA

OUTNA

DB0–DB7

8

MAX5851

50Ω

50Ω

OUTPB

OUTNB

Figure 8. Application with DC-Coupled Differential Outputs

Applications Information

Differential-to-Single-Ended Conversion

The MAX5851 exhibits excellent dynamic performance
to synthesize a wide variety of modulation schemes,
including high-order QAM modulation with OFDM.

Figure 7 shows a typical application circuit with output
transformers performing the required differential-to­single-ended signal conversion. In this configuration,
the MAX5851 operates in differential mode, which
reduces even-order harmonics, and increases the
available output power.

Differential DC-Coupled Configuration

Figure 8 shows the MAX5851 output operating in differ­ential, DC-coupled mode. This configuration can be
used in communication systems employing analog
quadrature upconverters and requiring a baseband
sampling, dual-channel, high-speed DAC for I/Q syn-

thesis. In these applications, information bandwidth can
extend from 10MHz down to several hundred kilohertz.
DC-coupling is desirable to eliminate long discharge
time constants that are problematic with large, expen­sive coupling capacitors. Analog quadrature upcon­verters have a DC common-mode input requirement of
typically 0.7V to 1.0V. The MAX5851 differential I/Q out­puts can maintain the desired full-scale level at the
required 0.7V to 1.0V DC common-mode level when
powered from a single 2.85V (±5%) supply. The
MAX5851 meets this low-power requirement with mini­mal reduction in dynamic range while eliminating the
need for level-shifting resistor networks.

Power Supplies, Bypassing,

Decoupling, and Layout

Grounding and power-supply decoupling strongly influ­ence the MAX5851 performance. Unwanted digital
crosstalk can couple through the input, reference,

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

16 ______________________________________________________________________________________

*Vias connect the land pattern to internal or external copper planes.

power-supply, and ground connections, which can
affect dynamic specifications, like signal-to-noise ratio
or spurious-free dynamic range. In addition, electro­magnetic interference (EMI) can either couple into or
be generated by the MAX5851. Observe the grounding
and power-supply decoupling guidelines for high­speed, high-frequency applications. Follow the power­supply and filter configuration to realize optimum
dynamic performance.

Use of a multilayer printed circuit (PC) board with sepa­rate ground and power-supply planes is recommend­ed. Run high-speed signals on lines directly above the
ground plane. The MAX5851 has separate analog and
digital ground buses (AGND, CGND, and DGND,
respectively). Provide separate analog, digital, and
clock ground sections on the PC board with only one
point connecting the three planes. The ground connec­tion points should be located underneath the device
and connected to the exposed paddle. Run digital sig­nals above the digital ground plane and analog/clock
signals above the analog/clock ground plane. Digital
signals should be kept away from sensitive analog,
clock, and reference inputs. Keep digital signal paths
short and metal trace lengths matched to avoid propa­gation delay and data skew mismatch.

The MAX5851 includes three separate power-supply
inputs: analog (AV

DD

), digital (DVDD), and clock

(CV

DD

). Use a single linear regulator power source to
branch out to three separate power-supply lines (AVDD,
DV

DD

, CVDD) and returns (AGND, DGND, CGND).
Filter each power-supply line to the respective return
line using LC filters comprising ferrite beads and 10µF
capacitors. Filter each supply input locally with 0.1µF
ceramic capacitors to the respective return lines.

Note: To maintain the dynamic performance of the
Electrical Characteristics, ensure the voltage differ­ence between DV

DD

, AVDD, and CVDDdoes not

exceed 150mV.

Thermal Characteristics and Packaging

Thermal Resistance

40-lead thin QFN-EP:

θ

JA

= 38°C/W

The MAX5851 is packaged in a 40-pin thin QFN-EP
package, providing greater design flexibility, increased
thermal efficiency, and optimized AC performance of
the DAC. The EP enables the implementation of
grounding techniques, which are necessary to ensure
highest performance operation.

In this package, the data converter die is attached to an
EP lead frame with the back of this frame exposed at the
package bottom surface, facing the PC board side of
the package. This allows a solid attachment of the pack­age to the PC board with standard infrared (IR) flow sol­dering techniques. A specially created land pattern on
the PC board, matching the size of the EP (4.1mm

✕

4.1mm), ensures the proper attachment and grounding
of the DAC. Designing vias* into the land area and
implementing large ground planes in the PC board
design allows for highest performance operation of the
DAC. Use an array of 3

✕ 3 vias (≤0.3mm diameter per

via hole and 1.2mm pitch between via holes) for this 40­pin thin QFN-EP package (package code: T4066-1).

Dynamic Performance

Parameter Definitions

Total Harmonic Distortion (THD)

THD is the ratio of the RMS sum of all essential harmon­ics (within a Nyquist window) of the input signal to the
fundamental itself. This can be expressed as:

where V1is the fundamental amplitude, and V2through
VNare the amplitudes of the 2nd through Nth order har­monics. The MAX5851 uses the first seven harmonics
for this calculation.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the carrier fre­quency (maximum signal component) to the RMS value
of their next-largest spectral component. SFDR is usu­ally measured in dBc with respect to the carrier fre­quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR
is observed within a predefined window or to Nyquist.

Multitone Power Ratio (MTPR)

A series of equally spaced tones are applied to the DAC
with one tone removed from the center of the range.
MTPR is defined as the worst-case distortion (usually a
3rd-order harmonic product of the fundamental frequen­cies), which appears as the largest spur at the frequency
of the missing tone in the sequence. This test can be per­formed with any number of input tones; however, four and
eight tones are among the most common test conditions
for CDMA- and GSM/EDGE-type applications.

THD

VVV V

V

N

=×

++ +



























log

... ...

20

22324

22

1

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

______________________________________________________________________________________ 17

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in dBc of either out­put tone to the worst 3rd-order (or higher) IMD products.

Static Performance Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. For a DAC,
the deviations are measured at every individual step.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A
DNL error specification no more negative than -1 LSB
guarantees monotonic transfer function.

Offset Error

Offset error is the current flowing from positive DAC
output when the digital input code is set to zero. Offset
error is expressed in LSBs.

Gain Error

A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step. The ideal current is
defined by reference voltage at 32 x V

REFO

/ R

SET

.

Settling Time

The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value to within the converter’s specified
accuracy.

Glitch Impulse

A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu­ally specified in pV-s.

Chip Information

TRANSISTOR COUNT: 9035
PROCESS: CMOS

Table 4. Part Selection Table

PART SPEED (Msps) RESOLUTION

MAX5851 80 8 bit, dual
MAX5852 165 8 bit, dual
MAX5853 80 10 bit, dual
MAX5854 165 10 bit, dual

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

QFN THIN 6x6x0.8.EPS

e e

LL

A1 A2

A

E/2

E

D/2

D

E2/2

E2

(NE-1) X e

(ND-1) X e

e

D2/2

D2

b

k

k

L

C

L

C

L

C

L

C

L

E

1

2

21-0141

PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm

L1

L

e

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

3. N IS THE TOTAL NUMBER OF TERMINALS.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

E

2

2

21-0141

PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm