MAXIM MAX5851 Technical data

General Description

The MAX5851 dual, 8-bit, 80Msps, digital-to-analog
converter (DAC) provides superior dynamic performance
in wideband communication systems. The device inte­grates two 8-bit DAC cores, and a 1.24V reference. The
converter supports single-ended and differential modes
of operation. The MAX5851 dynamic performance is
maintained over the entire 2.7V to 3.6V power-supply
operating range. The analog outputs support a -1.0V to
+1.25V compliance voltage.

The MAX5851 can also operate in interleave data mode
to reduce the I/O pin count. This allows the converter to
be updated on a single, 8-bit bus.

The MAX5851 features digital control of channel gain
matching to within ±0.4dB in sixteen 0.05dB steps.
Channel matching improves sideband suppression in
analog quadrature modulation applications. The on­chip 1.24V bandgap reference includes a control
amplifier that allows external full-scale adjustments of
both channels through a single resistor. The internal ref­erence can be disabled and an external reference may
be applied for high-accuracy applications.

The MAX5851 features full-scale current outputs of 2mA
to 20mA and operates from a 2.7V to 3.6V single supply.
The DAC supports three modes of power-control opera­tion: normal, low-power standby, and complete power­down. In power-down mode, the operating current is
reduced to 1µA.

The MAX5851 is packaged in a 40-pin thin QFN with
exposed paddle (EP) and is specified for the extended
(-40°C to +85°C) temperature range.

Pin-compatible, higher speed, and higher resolution
versions are also available. Refer to the MAX5852
(8 bit, 165Msps), the MAX5854 (10 bit, 165Msps), and
the MAX5853 (10 bit, 80Msps) data sheets for more
information. See Table 4.

Applications

Communications

VSAT, LMDS, MMDS, WLAN,

Point-to-Point Microwave Links
Wireless Base Stations
Quadrature Modulation
Direct Digital Synthesis (DDS)
Instrumentation/ATE

Features

♦ 8-Bit, 80Msps Dual DAC
♦ Low Power

58mW with IFS= 2mA at f

CLK

= 80MHz

♦ 2.7V to 3.6V Single Supply
♦ Full Output Swing and Dynamic Performance at

2.7V Supply

♦ Superior Dynamic Performance

66dBc SFDR at f

OUT

= 20MHz

♦ Programmable Channel Gain Matching
♦ Integrated 1.24V Low-Noise Bandgap Reference
♦ Single-Resistor Gain Control
♦ Interleaved Data Mode
♦ Single-Ended and Differential Clock Input Modes
♦ Miniature 40-Pin Thin QFN Package, 6mm x 6mm
♦ EV Kit Available—MAX5852 EV Kit

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3231; Rev 0; 4/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX5851ETL -40°C to +85°C

40 Thin QFN-EP*

40 36373839

EP

18

21

23
22

24

25

19 2016 17

6

5

4

3

2

1

7
8
9

10

11

12

13

14

15

26

27

28

29

30

3132

33

3435

N.C.

DB6

AGND

MAX5851

THIN QFN

TOP VIEW

AVDDOUTPA

OUTNA

AGND

OUTPB

OUTNB

AV

DD

REFR

REFO

DB7

DB4

DB5

DV

DD

DB3

DB2

DGND

DB0

DB1

CV

DD

CGND
CLK
CV

DD

CLKXN
CLKXP
DCE
CW
N.C.
N.C.

N.C.

DA0/G0

DA1/G1

DA2/G2

DA3/G3

DA4/REN

DA5/IDE

DA6/DACEN

DA7/PD

Pin Configuration

*EP = Exposed paddle.

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto AGND .........................................................-0.3V to +4V

DV

DD

to DGND.........................................................-0.3V to +4V

CV

DD

to CGND.........................................................-0.3V to +4V

AV

DD

to DVDD.............................................................-4V to +4V

AV

DD

to CVDD..........................................................-0.4V to +4V

DV

DD

to CVDD..........................................................-0.4V to +4V

AGND to DGND.....................................................-0.3V to +0.3V

AGND to CGND.....................................................-0.3V to +0.3V

DGND to CGND ....................................................-0.3V to +0.3V

DA7–DA0, DB7–DB0,

CW, DCE to DGND ...............-0.3V to +4V

CLK to CGND ..........................................-0.3V to (CV

DD

+ 0.3V)

CLKXN, CLKXP to CGND.........................................-0.3V to +4V

REFR, REFO to AGND .............................-0.3V to (AV

DD

+ 0.3V)

OUTPA, OUTNA to AGND..........(AV

DD

- 4.8V) to (AVDD+ 0.3V)

OUTPB, OUTNB to AGND..........(AV

DD

- 4.8V) to (AVDD+ 0.3V)

Maximum Current into Any Pin

(excluding power supplies)..........................................±50mA

Continuous Power Dissipation (T

A

= +70°C)

40-Pin Thin QFN (derate 26.3mW/°C above +70°C)....2105mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE

Resolution N 8 Bits
Integral Nonlinearity INL RL = 0

LSB

Differential Nonlinearity DNL Guaranteed monotonic, RL = 0

LSB

Offset Error V

OS

LSB

Internal reference (Note1) -10

+8

Gain Error (See Also Gain Error
Definition Section)

GE

External reference

%FSR

Internal reference

Gain-Error Temperature Drift

External reference

ppm/°C

DYNAMIC PERFORMANCE

f

OUT

= 10MHz

f

OUT

= 20MHz 66

f

CLK

= 80MHz,

A

OUT

= -1dBFS

f

OUT

= 30MHz 65

f

CLK

= 44MHz,

A

OUT

= -1dBFS

f

OUT

= 10MHz 63

Spurious-Free Dynamic Range to
Nyquist

SFDR

f

CLK

= 25MHz,

A

OUT

= -1dBFS

f

OUT

= 1MHz 64

dBc

f

CLK

= 80MHz, f

OUT

= 10MHz,

A

OUT

= -1dBFS, span = 10MHz

70

f

CLK

= 65MHz, f

OUT

= 5MHz,

A

OUT

= -1dBFS, span = 2.5MHz

68

Spurious-Free Dynamic Range
Within a Window

SFDR

f

CLK

= 25MHz, f

OUT

= 1MHz,

A

OUT

= -1dBFS, span = 2MHz

67

dBc

Multitone Power Ratio to Nyquist

MTPR

8 tones at 400kHz spacing, f

CLK

= 78MHz,

f

OUT

= 15MHz to 18.2MHz

63 dBc

-0.25 ±0.05 +0.25

-0.15 ±0.05 +0.15

-0.1 ±0.2 +0.1
±1.5

-5.5 ±0.7 +5.0

±150
±100

63.3 66.5

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

Multitone Spurious-Free Dynamic
Range Within a Window

8 tones at 811kH z sp aci ng , f

C LK

= 80M H z,

61 dBc

f

OUT

= 10MHz -72

f

OUT

= 20MHz -74

f

CLK

= 80MHz,

A

OUT

= -1dBFS

f

OUT

= 30MHz -69

f

CLK

= 44MHz,

A

OUT

= -1dBFS

f

OUT

= 10MHz -73

Total Harmonic Distortion to
Nyquist (2nd- Through 8th-Order
Harmonics Included)

THD

f

CLK

= 25MHz,

A

OUT

= -1dBFS

f

OUT

= 1MHz -69

dBc

Output Channel-to-Channel
Isolation

f

OUT

= 10MHz 90 dB

Channel-to-Channel Gain
Mismatch

f

OUT

= 10MHz, G[3:0] = 1000

dB

Channel-to-Channel Phase
Mismatch

f

OUT

= 10MHz

Degrees

f

CLK

= 80MHz, f

OUT

= 5MHz, I

FS

= 20mA 51

Signal-to-Noise Ratio to Nyquist SNR

f

CLK

= 80MHz, f

OUT

= 5MHz, I

FS

= 5mA

dB

Interleaved mode disabled, IDE = 0 80

Maximum DAC Conversion Rate

f

DAC

Interleaved mode enabled, IDE = 1 80

Msps

Glitch Impulse 5

pV•s

Output Settling Time t

S

To ±0.1% error band (Note 3) 12 ns
Output Rise Time 10% to 90% (Note 3) 2.2 ns
Output Fall Time 90% to 10% (Note 3) 2.2 ns

ANALOG OUTPUT

Full-Scale Output Current Range

I

FS

220mA

Output Voltage Compliance
Range

V

Output Leakage Current Shutdown or standby mode -5 +5 µA

REFERENCE

Internal-Reference Output
Voltage

V

REFO

REN = 0

V

Internal-Reference Supply
Rejection

AV

DD

varied from 2.7V to 3.6V 0.5

mV/V

Internal-Reference Output­Voltage Temperature Drift

REN = 0

ppm/°C

SYMBOL

f

OU T

TCV

REFO

= 10.8M H z to 17.2M H z, sp an = 15M H z

MIN TYP MAX

0.025

0.05

50.3

-1.00 +1.25

1.13 1.24 1.32

±50

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Internal-Reference Output Drive
Capability

REN = 0 50 µA

External-Reference Input Voltage
Range

REN = 1

1.2

V

Current Gain

32

mA/mA

LOGIC INPUTS (DA7–DA0, DB7–DB0, CW)

Digital Input-Voltage High V

IH

V

Digital Input-Voltage Low V

IL

0.3 x
V

Digital Input Current I

IN

-1 +1 µA

Digital Input Capacitance C

IN

3pF

SINGLE-ENDED CLOCK INPUT/OUTPUT AND DCE INPUT (CLK, DCE)

Digital Input-Voltage High V

IH

DCE = 1

0.65 x
V

Digital Input-Voltage Low V

IL

DCE = 1

0.3 x
V

Digital Input Current I

IN

DCE = 1 -1 +1 µA

Digital Input Capacitance C

IN

DCE = 1 3 pF

Digital Output-Voltage High V

OH

DCE = 0, I

SOURCE

= 0.5mA, Figure 1

V

Digital Output-Voltage Low V

OL

DCE = 0, I

SINK

= 0.5mA, Figure 1

V

DIFFERENTIAL CLOCK INPUTS (CLKXP/CLKXN)
Differential Clock Input Internal

Bias

CV

DD

/ 2 V

Differential Clock Input Swing 0.5 V
Clock Input Impedance Measured single ended 5 kΩ

POWER REQUIREMENTS

Analog Power-Supply Voltage AV

DD

2.7 3 3.6 V

Digital Power-Supply Voltage DV

DD

2.7 3 3.6 V

Clock Power-Supply Voltage CV

DD

2.7 3 3.6 V

I

FS

= 20mA, single-ended clock mode 43 46

I

FS

= 20mA, differential clock mode 43

I

FS

= 2mA, single-ended clock mode 5

Analog Supply Current (Note 2) I

AVDD

I

FS

= 2mA, differential clock mode 5

mA

IFS/I

REF

0.10

0.65 x
DV

DD

CV

DD

0.9 x

CV

DD

1.32

DV

CV

0.1 x

CV

DD

DD

DD

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

I

FS

= 20mA, single-ended clock mode 3 3.8

Digital Supply Current (Note 2) I

DVDD

I

FS

= 20mA, differential clock mode 3

mA

Single-ended clock mode (DCE = 1)

Clock Supply Current (Note 2) I

CVDD

Differential clock mode (DCE = 0)

mA

Total Standby Current

I

AVDD

+ I

DVDD

+ I

CVDD

3.1 3.7 mA

Total Shutdown Current I

SHDNIAVDD

+ I

DVDD

+ I

CVDD

1µA

I

FS

= 20mA

190

Single-ended clock
mode (DCE = 1)

I

FS

= 2mA 58

I

FS

= 20mA

Differential clock
mode (DCE = 0)

I

FS

= 2mA 74

Standby 9.3

Total Power Dissipation (Note 2)

P

TOT

Shutdown

mW

TIMING CHARACTERISTICS (Figures 5 and 6)

Propagation Delay 1

Clock

cycles

Single-ended clock mode (DCE = 1) 1.2

DAC Data to CLK Rise/Fall
Setup Time (Note 4)

t

DCS

Differential clock mode (DCE = 0) 2.7

ns

Single-ended clock mode (DCE = 1) 0.8

DAC Data to CLK Rise/Fall
Hold Time (Note 4)

t

DCH

Differential clock mode (DCE = 0)

ns

Control Word to CW Rise
Setup Time

t

CS

2.5 ns

Control Word to CW Rise
Hold Time

t

CW

2.5 ns

CW High Time t

CWH

5ns

CW Low Time t

CWL

5ns

SYMBOL

I

STANDBY

MIN TYP MAX

11.2 13.5

16.5

172

188

11.1

0.003

-0.5

MAX5851

Dual, 8-Bit, 80Msps, Current-Output DAC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(AVDD= DVDD= CVDD= 3V, AGND = DGND = CGND = 0, f

DAC

= 80Msps, differential clock, external reference, V

REF

= 1.2V, IFS=

20mA, differential output, output amplitude = 0dBFS, T

A

= T

MIN

to T

MAX

, unless otherwise noted. TA ≥ +25°C, guaranteed by produc-

tion test. T

A

< +25°C guaranteed by design and characterization. Typical values are at TA= +25°C.)

PARAMETER

CONDITIONS

UNITS

DACEN = 1 to V

OUT

Stable Time

(Coming Out of Standby)

t

STB

3µs

PD = 0 to V

OUT

Stable Time

(Coming Out of Power-Down)

t

SHDN

µs

Maximum Clock Frequency at
CLKXP/CLKXN Input

f

CLK

80

MHz

Clock High Time t

CXH

CLKXP or CLKXN input 3 ns

Clock Low Time t

CXL

CLKXP or CLKXN input 3 ns

CLKXP Rise to CLK Output
Rise Delay

t

CDH

DCE = 0 2.7 ns

CLKXP Fall to CLK Output
Fall Delay

t

CDL

DCE = 0 2.7 ns

Note 1: Including the internal reference voltage tolerance and reference amplifier offset.
Note 2: f

DAC

= 80Msps, f

OUT

= 10MHz.

Note 3: Measured single ended with 50Ω load and complementary output connected to ground.
Note 4: Guaranteed by design, not production tested.

TO OUTPUT

PIN

5pF

0.5mA

0.5mA

1.6V

Figure 1. Load Test Circuit for CLK Outputs

SYMBOL

MIN TYP MAX

500