MAXIM MAX5590, MAX5595 User Manual
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
General Description
The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-output digital-to-analog converters (DACs) offer buffered
outputs and a 3µs maximum settling time at the 12-bit
level. The DACs operate from a +2.7V to +5.25V analog
supply and a separate +1.8V to +5.25V digital supply.
The 20MHz 3-wire serial interface is compatible with
SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct-access or
daisy-chained configuration. The MAX5590–MAX5595
provide two multifunction, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
The MAX5590/MAX5591 are 12-bit DACs, the MAX5592/
MAX5593 are 10-bit DACs, and the MAX5594/
MAX5595 are 8-bit DACs. The MAX5590/MAX5592/
MAX5594 provide unity-gain-configured output buffers,
while the MAX5591/MAX5593/MAX5595 provide forcesense-configured output buffers. The MAX5590–
MAX5595 are specified over the extended -40°C to
+85°C temperature range, and are available in spacesaving 24-pin and 28-pin TSSOP packages.
Applications
Portable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
Features
o Octal, 12/10/8-Bit Serial DACs in TSSOP Packages
o 3µs (max) 12-Bit Settling Time to 1/2 LSB
o Integral Nonlinearity:
1 LSB (max) MAX5590/MAX5591 A-Grade (12-Bit)
1 LSB (max) MAX5592/MAX5593 (10-Bit)
1/2 LSB (max) MAX5594/MAX5595 (8-Bit)
o Guaranteed Monotonic, ±1 LSB (max) DNL
o Two User-Programmable Digital I/O Ports
o Single +2.7V to +5.25V Analog Supply
o +1.8V to AV
DD
Digital Supply
o 20MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-/DSP-
Compatible Serial Interface
o Glitch-Free Outputs Power Up to Zero Scale,
Midscale, or Full Scale Controlled by PU Pin
o Unity-Gain or Force-Sense-Configured Output
Buffers
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-2983; Rev 3; 1/10
*
Future product—contact factory for availability. Specifications
are preliminary.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide and Pin Configurations appear at end of data
sheet.
EVALUATION KIT
AVAILABLE
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP RANGE PIN-PACKAGE
MAX5590AEUG+* -40°C to +85°C 24 TSSOP
MAX5590BEUG+ -40°C to +85°C 24 TSSOP
MAX5591AEUI+* -40°C to +85°C 28 TSSOP
MAX5591BEUI+ -40°C to +85°C 28 TSSOP
MAX5592EUG+ -40°C to +85°C 24 TSSOP
MAX5593EUI+ -40°C to +85°C 28 TSSOP
MAX5594EUG+ -40°C to +85°C 24 TSSOP
MAX5595EUI+ -40°C to +85°C 28 TSSOP
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, V
AGND
= 0V, V
DGND
= 0V, V
REF
= 2.5V (for AVDD= 2.7V to 5.25V), V
REF
= 4.096V (for
AV
DD
= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto DVDD........................................................................±6V
AGND to DGND ..................................................................±0.3V
AV
DD
to AGND, DGND.............................................-0.3V to +6V
DV
DD
to AGND, DGND ............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AV
DD
+ 0.3V) or +6V
SCLK, DIN, CS, PU,
DSP to DGND .......-0.3V to the lower of (DV
DD
+ 0.3V) or +6V
UPIO1, UPIO2
to DGND ...............-0.3V to the lower of (DV
DD
+ 0.3V) or +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW
28-Pin TSSOP (derate 14mW/°C above +70°C) ........1117mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
STATIC ACCURACY
MAX5590/MAX5591 12
MAX5592/MAX5593 10Resolution N
MAX5594/MAX5595 8
V
REF
AV
Integral Nonlinearity INL
Differential Nonlinearity DNL Guaranteed monotonic (Note 2) ±1 LSB
Offset Error V
Offset-Error Drift 5
Gain Error GE Full-scale output
Gain-Error Drift 1
OS
DD
V
REF
AV
DD
(Note 2)
M AX 5590A/M AX 5591A ( 12- b i t) , d eci m al cod e = 40 ±5
M AX 5590B/M AX 5591B ( 12- b i t) , d eci m al cod e = 40 ±5 ±25
MAX5592/MAX5593 (10-bit), decimal code = 10 ±5 ±25
MAX5594/MAX5595 (8-bit), decimal code = 3 ±5 ±25
= 2.5V at
= 2.7V and
= 4.096V at
= 5.25V
MAX5590A/MAX5591A (12-bit) ±1
MAX5590B/MAX5591B (12-bit) ±2 ±4
MAX5592/MAX5593 (10-bit) ±0.5 ±1
MAX5594/MAX5595 (8-bit) ±0.125 ±0.5
MAX5590A/MAX5591A (12-bit) ±4
MAX5590B/MAX5590B (12-bit) ±20 ±40
MAX5592/MAX5593 (10-bit) ±5 ±10
MAX5594/MAX5595 (8-bit) ±2 ±3
Bits
LSB
mV
ppm of
FS/°C
LSB
ppm of
FS/°C
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, V
AGND
= 0V, V
DGND
= 0V, V
REF
= 2.5V (for AVDD= 2.7V to 5.25V), V
REF
= 4.096V (for
AV
DD
= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Rejection
Ratio
REFERENCE INPUT
Reference Input Range V
Reference Input
Resistance
Reference Leakage
Current
DAC OUTPUT CHARACTERISTICS
Output Voltage Noise
Output Voltage Range
(Note 3)
DC Output Impedance 38 Ω
Short-Circuit Current
Power-Up Time From VDD applied until interface is functional 30 60 µs
Wake-Up Time Coming out of shutdown, outputs settled 40 µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
DIGITAL OUTPUTS (UPIO_)
Output High Voltage V
Output Low Voltage V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
Input Capacitance C
PSRR Full-scale output, AV
REF
R
REF
OH
OL
IH
IL
IN
IN
Normal operation (no code dependence) 145 200 kΩ
Shutdown mode 0.5 1 µA
SLOW mode, full scale
FAST mode, full scale
Unity-gain output 0 AV
Force-sense output 0 AV
AVDD = 5V, OUT_ to AGND, full scale, FAST mode 57
AV
DD
Programmed in shutdown mode, force-sense
outputs only
I
SOURCE
I
SINK
DVDD ≥ 2.7V 2.4
DV
DD
DV
DD
2.7V ≤ DV
DV
DD
= 3V, OUT_ to AGND, full scale, FAST mode 45
= 2mA 0.4 V
< 2.7V
> 3.6V 0.8
< 2.7V 0.2
= 2mA
≤ 3.6V 0.6
DD
= 2.7V to 5.25V 200 µV/V
DD
Unity gain 85
Force sense 67
Unity gain 140
Force sense 110
0.25 AV
-
DV
DD
0.5
0.7 x
DV
DD
DD
DD
/ 2
DD
0.01 µA
±0.1 ±1 µA
10 pF
µV
V
RMS
V
mA
V
V
V
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, V
AGND
= 0V, V
DGND
= 0V, V
REF
= 2.5V (for AVDD= 2.7V to 5.25V), V
REF
= 4.096V (for
AV
DD
= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PU INPUT
Input High Voltage V
Input Low Voltage V
Input Leakage Current I
DYNAMIC PERFORMANCE
Voltage-Output Slew
Rate
Voltage-Output Settling
Time (Note 5)
FB_ Input Voltage 0V
FB_ Input Current 0.1 µA
Reference -3dB
Bandwidth (Note 6)
Digital Feedthrough
Digital-to-Analog Glitch
Impulse
DAC-to-DAC Crosstalk (Note 4) 15 nV-s
IH-PU
IL-PU
IN-PU
SR
PU still considered unconnected when connected to
a tri-state bus
FAST mode 3.6
SLOW mode 1.6
FAST
mode
SLOW
mode
Unity gain 200
Force sense 150
CS = DV
from 0 to DV
Major carry transition 2 nV-s
DD
M AX 5590/M AX 5591 fr om cod e 322 to
cod e 4095 to 1/2 LS B
M AX 5592/M AX 5593 fr om cod e 10 to
cod e 1023 to 1/2 LS B
MAX5594/MAX5595 fr om cod e 3 to
code 255 to 1/2 LSB
M AX 5590/M AX 5591 fr om cod e 322 to
cod e 4095 to 1/2 LS B
MAX5592/MAX5593 fr om cod e 10 to
code 1023 1/2 LSB
MAX5594/MAX5595 fr om cod e 3 to
code 255 to 1/2 LSB
, code = zero scale, any digital input
and DVDD to 0, f = 100kHz
DD
DV
-
DD
200mV
23
1.5 3
12
36
2.5 6
24
0.1 nV-s
V
200 mV
±200 nA
V/µs
µs
/ 2 V
REF
kHz
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, V
AGND
= 0V, V
DGND
= 0V, V
REF
= 2.5V (for AVDD= 2.7V to 5.25V), V
REF
= 4.096V (for
AV
DD
= 4.5V to 5.25V), RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
(Note 1)
PARAMETER
CONDITIONS
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Range
AV
DD
V
Digital Supply Voltage
Range
DV
DD
1.8
V
Unity gain 1.5 3.2
SLOW mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 4.096V
Force sense 2.4 4.8
Unity gain 2.5 8
Operating Supply
Current
I
AVDD
+
I
DVDD
FAST mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 4.096V
Force sense 3.4 8
mA
Shutdown Supply
Current
I
AV D D ( S H D N )
+
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode
0.5 1 µA
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. V
OUT
(max) = V
REF
/ 2, unless otherwise noted.
Note 2: Linearity guaranteed from decimal code 40 to code 4095 for the MAX5590B/MAX5591B (12-bit, B-grade), code 10 to code
1023 for the MAX5592/MAX5593 (10-bit), and code 3 to code 255 for the MAX5594/MAX5595 (8-bit).
Note 3: Represents the functional range. The linearity is guaranteed at V
REF
= 2.5V (for AVDDfrom 2.7V to 5.25V), and V
REF
=
4.096V (for AVDD= 4.5V to 5.25V). See the
Typical Operating Characteristics
section for linearity at other voltages.
Note 4: DC crosstalk is measured as follows: outputs of DACA–DACH are set to full scale and the output of DACH is measured.
While keeping DACH unchanged, the outputs of DACA–DACG are transitioned to zero scale and the ∆V
OUT
of DACH is
measured.
Note 5: Guaranteed by design.
Note 6: The reference -3dB bandwidth is measured with a 0.1V
P-P
sine wave on V
REF
and with full-scale input code.
SYMBOL
I
D V D D ( S H D N )
MIN TYP MAX
2.70 5.25
AV
DD
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DVDD= 2.7V to 5.25V, V
AGND
= 0V, V
DGND
= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Hold Time t
SCLK Rise to CS Fall Setup t
DIN to SCLK Rise Setup Time t
DIN to SCLK Rise Hold Time t
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Rise Hold Time t
CS Pulse-Width High t
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, and UPIO
Modes
SCLK
CSS
CSH
CS0
t
DO1
t
DO2
CS1
CSW
t
DOZ
CH
DH
CL
DS
2.7V < DVDD < 5.25V 20 MHz
(Note 7) 20 ns
(Note 7) 20 ns
CL = 20pF, UPIO_ = DOUTDC1 mode 30 ns
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
MICROWIRE and SPI modes 0 and 3 10 ns
CL = 20pF, from end of write cycle to UPIO_
in high impedance
10 ns
5ns
10 ns
12 ns
5ns
45 ns
30 ns
100 ns
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 20 ns
Figure 6 100 ns
Figure 5 20 ns
Figure 6 100 ns
0ns
20 ns
100 ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 7
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD= 1.8V to 5.25V, V
AGND
= 0V, V
DGND
= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Setup Time t
SCLK Rise to CS Rise Hold Time t
SCLK Rise to CS Fall Setup t
DIN to SCLK Rise Setup Time t
DIN to SCLK Rise Hold Time t
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Rise Hold Time t
CS Pulse-Width High t
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
SCLK
CSS
CSH
CS0
t
DO1
t
DO2
CS1
CSW
t
DOZ
t
DRBZ
t
ZEN
LDL
LDS
CMS
t
GPZ
CH
CL
DS
DH
GP
1.8V < DVDD < 5.25V 10 MHz
(Note 7) 40 ns
(Note 7) 40 ns
CL = 20pF, UPIO_ = DOUTDC1 mode 60 ns
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
MICROWIRE and SPI modes 0 and 3 20 ns
CL = 20pF, from end of write cycle to UPIO_
in high impedance
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 40 ns
Figure 6 200 ns
Figure 5 40 ns
Figure 6 200 ns
20 ns
0ns
10 ns
20 ns
5ns
90 ns
0ns
60 ns
200 ns
40 ns
200 ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
8 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2)
(DVDD= 2.7V to 5.25V, V
AGND
= 0V, V
DGND
= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Fall Setup Time t
DSP Fall to SCLK Fall Setup Time t
SCLK Fall to CS Rise Hold Time t
SCLK Fall to CS Fall Delay t
SCLK Fall to DSP Fall Delay t
DIN to SCLK Fall Setup Time t
DIN to SCLK Fall Hold Time t
SCLK Rise to DOUT_ Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Fall Hold Time t
CS Pulse-Width High t
DSP Pulse-Width High t
DSP Pulse-Width Low t
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
SCLK
CSS
DSS
CSH
CS0
DS0
t
DO1
t
DO2
CS1
CSW
DSW
DSPWL
t
DOZ
CH
DH
CL
DS
2.7V < DVDD < 5.25V 20 MHz
(Note 7) 20 ns
(Note 7) 20 ns
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
CL = 20pF, UPIO_ = DOUTDC0 mode 30 ns
MICROWIRE and SPI modes 0 and 3 10 ns
(Note 8) 20 ns
CL = 20pF, from end of write cycle to UPIO_
in high impedance
10 ns
10 ns
5ns
10 ns
10 ns
12 ns
5ns
45 ns
20 ns
30 ns
100 ns
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 20 ns
Figure 6 100 ns
Figure 5 20 ns
Figure 6 100 ns
0ns
20 ns
100 ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 9
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD= 1.8V to 5.25V, V
AGND
= 0V, V
DGND
= 0V, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
operation.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Frequency f
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Fall Setup Time t
DSP Fall to SCLK Fall Setup Time t
SCLK Fall to CS Rise Hold Time t
SCLK Fall to CS Fall Delay t
SCLK Fall to DSP Fall Delay t
DIN to SCLK Fall Setup Time t
DIN to SCLK Fall Hold Time t
SCLK Rise to DOUT_ Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Fall Hold Time t
CS Pulse-Width High t
DSP Pulse-Width High t
DSP Pulse-Width Low t
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
SCLK
CSS
DSS
CSH
CS0
DS0
t
DO1
t
DO2
CS1
CSW
DSW
DSPWL
t
DOZ
CH
DH
CL
DS
1.8V < DVDD < 5.25V 10 MHz
(Note 7) 40 ns
(Note 7) 40 ns
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
CL = 20pF, UPIO_ = DOUTDC0 mode 60 ns
MICROWIRE and SPI modes 0 and 3 20 ns
(Note 8) 40 ns
CL = 20pF, from end of write cycle to UPIO_
in high impedance
20 ns
20 ns
0ns
10 ns
15 ns
20 ns
5ns
90 ns
40 ns
60 ns
200 ns
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
LDAC Pulse-Width Low t
LDAC Effective Delay t
CLR, MID, SET Pulse-Width Low t
GPO Output Settling Time t
GPO Output High-Impedance
Time
t
DRBZ
t
ZEN
LDL
LDS
CMS
GP
t
GPZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
Figure 5 40 ns
Figure 6 200 ns
Figure 5 40 ns
Figure 6 200 ns
0ns
40 ns
200 ns
MAX5590–MAX5595
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
Voltage-Output DACs
10 ______________________________________________________________________________________
Typical Operating Characteristics
(AVDD= DVDD= 5V, V
REF
= 4.096V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = unconnected, TA= +25°C, unless otherwise
noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
4
3
2
1
0
INL (LSB)
-1
-2
-3
B-GRADE
-4
0 1024 2048 3072 4095
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
0.50
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
0
0 64 128 192 255
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5590-95 toc01
INL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0 256 512 768 1023
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
0.2
MAX5590-95 toc02
0.50
0.25
INL (LSB)
-0.25
-0.50
0.050
MAX5590-95 toc03
DIGITAL INPUT CODE
0.25
0
DNL (LSB)
-0.25
-0.50
0 1024 2048 3072 4095
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (12-BIT)
4
3
2
1
0
INL (LSB)
-1
-2
-3
B-GRADE
MIDSCALE
-4
1.0 2.0 2.51.5 3.0 3.5 4.0 4.5 5.0
V
(V)
REF
B-GRADE
MAX5590-95 toc04
DNL (LSB)
MAX5590-95 toc07
0.1
0
-0.1
-0.2
0 256 512 768 1023
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. REFERENCE VOLTAGE (12-BIT)
0.5
0.4
0.3
0.2
0.1
0
DNL (LSB)
-0.1
-0.2
-0.3
-0.4
-0.5
1.0 20 2.51.5 3.0 3.5 4.0 4.5 5.0
V
(V)
REF
B-GRADE
MIDSCALE
MAX5590-95 toc05
-0.025
-0.050
MAX5590-95 toc08
0.025
0
DNL (LSB)
0 64 128 192 255
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
4
3
2
1
0
INL (LSB)
-1
-2
-3
B-GRADE
MIDSCALE
-4
-40 10-15 35 60 85
TEMPERATURE (°C)
MAX5590-95 toc06
MAX5590-95 toc09
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