MAXIM MAX5556 Technical data

________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Cost Stereo Audio DAC
MAX5556
The MAX5556 stereo audio sigma-delta digital-to-analog converter (DAC) offers a simple and complete stereo digital-to-analog solution for media servers, set-top boxes, video-game hardware, automotive rear-seat entertainment, and other general consumer audio appli­cations. This DAC features built-in digital interpolation/fil­tering, sigma-delta digital-to-analog conversion, and analog output filtering. Control logic and mute circuitry minimize audible pops and clicks during power-up, power-down, clock changes, or when invalid clock con­ditions occur.
The MAX5556 receives input data over a 3-wire I2S-compatible interface with left-justified audio data. Data can be clocked by either an external or internal serial clock. The internal serial clock frequency is pro­grammable by selection of a master clock (MCLK) and sample clock (LRCLK) ratio. Sampling rates from 2kHz to 50kHz are supported.
The MAX5556 operates from a single +4.75V to +5.5V analog supply with total harmonic distortion plus noise below -87dB. This device is available in an 8-pin SO package and is specified over the -40°C to +85°C industrial temperature range.
Applications
Digital Video Recorders and Media Servers
Set-Top Boxes
Video-Game Hardware
Automotive Rear-Seat Entertainment
Features
o Simple and Complete Stereo Audio DAC
Solutions, No Controls to Set
o Sigma-Delta Stereo DACs with Built-In
Interpolation and Analog Output Filters
o I2S-Compatible Digital Audio Interface
o Clickless/Popless Operation
o 3.5V
P-P
Output Voltage Swing
o -87dB THD+N
o +87dB Dynamic Range
o Sample Frequencies (fS) from 2kHz to 50kHz
o Master Clock (MCLK) up to 25MHz
o Automatic Detection of Clock Ratio (MCLK/
LRCLK)
Ordering Information
Typical Operating Circuit
+Denotes a lead(Pb)-free/RoHS-compliant package. For lead­ed version, contact factory.
/V denotes an automotive-qualified part.
Pin Configuration
19-0550; Rev 1; 2/11
PART
MAX5556ESA+
MAX5556ESA/V+
TEMP
RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
8 SO
8 SO
DATA FORMAT
Left-justified I data
Left-justified I data
2
S
2
S
+5V
TOP VIEW
V
AUDIO
DECOMPRESSION
CLOCK
SDATA
SCLK
LRCLK
MCLK
SERIAL
INTERFACE
GND
DD
OUTL
OUTR
FILTER
FILTER
DAC
MAX5556
DAC
LINE-LEVEL
BUFFER
LINE-LEVEL
BUFFER
LEFT
OUTPUT
RIGHT
OUTPUT
SDATA
SCLK
LRCLK
+
1
2
MAX5556
3
4
87OUTL
V
DD
GND
6
OUTRMCLK
5
SO
Low-Cost Stereo Audio DAC
MAX5556
2 _______________________________________________________________________________________
VDDto GND...........................................................-0.3V to +6.0V
OUTL, OUTR, SDATA to GND................... -0.3V to (V
DD
+ 0.3V)
Current Any Pin (excluding V
DD
and GND)......................±10mA
OUTL, OUTR Shorted to GND....................................Continuous
SCLK, LRCLK, MCLK to GND ...............................-0.3V to +6.0V
Continuous Power Dissipation (T
A
= +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C)...............471mW
Package Thermal Resistance (θ
JA
) ...............................170°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +4.75V to +5.5V, V
GND
= 0V, R
OUT
_ = 10k, C
OUT
_ = 10pF, 0dBFS sine-wave signal at 997Hz, f
LRCLK(fS
) = 48kHz, f
MCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA= -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical values at V
DD
= +5V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
POWER SUPPLY
Supply Voltage V
Supply Current I
Power Dissipation
DYNAMIC PERFORMANCE (Note 2)
Dynamic Range, 16-Bit
Dynamic Range, 18-Bit to 24-Bit
Total Harmonic Distortion Plus Noise, 16-Bit
Total Harmonic Distortion Plus Noise, 18-Bit to 24-Bit
Interchannel Isolation 1kHz full-scale output (crosstalk) 94 dB
COMBINED DIGITAL AND INTEGRATED ANALOG FILTER FREQUENCY RESPONSE (Note 3)
Passband
Frequency Response/Passband Ripple
Stopband 0.5465 f
Stopband Attenuation 52 dB
Group Delay
Passband Group-Delay Variation ∆t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DD
DD
THD+N
THD+N
t
gd
gd
Up to 48ksps 13 15
Static digital 6 8.5
Up to 48ksps 65 82.5
Static digital 30 44
Unweighted 84 86
A-weighted 86 90
Unweighted 87
A-weighted 91
0dBFS -86 -81
-20dBFS -67
-60dBFS -26 -24
0dBFS -87
-20dBFS -68
-60dBFS -27
-0.5dB corner 0.46
-3dB corner 0.49
-6dB corner 0.50
10Hz to 20kHz (fS = 48kHz) -0.025 +0.08
10Hz to 20kHz (fS = 44.1kHz) -0.025 +0.08
10Hz to 16kHz (f
20Hz to 20kHz ±0.4/f
= 32kHz) -6.000 +0.073
S
20/f
S
S
4.75 5.0 5.50 V
mA
mW
dB
dB
dB
dB
f
S
dB
S
s
s
Low-Cost Stereo Audio DAC
MAX5556
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +4.75V to +5.5V, V
GND
= 0V, R
OUT
_ = 10k, C
OUT
_ = 10pF, 0dBFS sine-wave signal at 997Hz, f
LRCLK(fS
) = 48kHz, f
MCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA= -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical values at V
DD
= +5V, TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC CHARACTERISTICS
Interchannel Gain Mismatch 0.1 0.4 dB
Gain Error -5 +5 %
Gain Drift 100 ppm/°C
ANALOG OUTPUTS
Full-Scale Output Voltage
DC Quiescent Output Voltage V
Minimum Load Resistance R
Maximum Load Capacitance C
Power-Supply Rejection Ratio PSRR
POP AND CLICK SUPPRESSION
Mute Attenuation 100 dB
Power-Up Until Bias Established Figure 11 360 ms
Valid Clock to Normal Operation Soft-start ramp time, Figure 12 (Note 5) 20 ms
DIGITAL AUDIO INTERFACE (SCLK, SDATA, MCLK, LRCLK)
Input-Voltage High V
Input-Voltage Low V
Input Leakage Current I
Input Capacitance 8pF
TIMING CHARACTERISTICS
Input Sample Rate f
MCLK Pulse-Width High t
EXTERNAL SCLK MODE
LRCLK Duty Cycle (Note 6) 25 75 %
SCLK Pulse-Width Low t
SCLK Pulse-Width High t
SCLK Period t
LRCLK Edge to SCLK Rising
LRCLK Edge to SCLK Rising
SDATA Valid to SCLK Rising
SCLK Rising to SDATA Hold Time t
V
OU T R
MCLKL
MCLKH
SCLKL
SCLKH
t
t
, V
OU T L
Q
L
L
IH
IL
IN
S
SCLK
SLRS
SLRH
t
SDS
SDH
3.25 3.5 3.75 V
Input code = 0 2.4 V
3k
100 pF
V
RIPPLE
= 100mV
, frequency = 1kHz
P-P
66 dB
2.0 V
0.8 V
-10 +10 µA
2 50 kHz
MCLK/LRCLK = 512 10
MCLK/LRCLK = 384 20MCLK Pulse-Width Low t
MCLK/LRCLK = 256 20
MCLK/LRCLK = 512 10
MCLK/LRCLK = 384 20
MCLK/LRCLK = 256 20
20 ns
20 ns
1/(128
x f
)
S
20 ns
20 ns
20 ns
20 ns
P-P
ns
ns
ns
Low-Cost Stereo Audio DAC
MAX5556
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +4.75V to +5.5V, V
GND
= 0V, R
OUT
_ = 10k, C
OUT
_ = 10pF, 0dBFS sine-wave signal at 997Hz, f
LRCLK(fS
) = 48kHz, f
MCLK
= 12.288MHz, measurement bandwidth 10Hz to 20kHz, TA= -40°C to +85°C, outputs are unloaded, unless otherwise noted. Typical values at V
DD
= +5V, TA= +25°C.) (Note 1)
Note 1: 100% production tested at T
A
= +85°C. Limits to -40°C are guaranteed by design.
Note 2: 0.5 LSB of triangular PDF dither added to data. Note 3: Guaranteed by design, not production tested. Note 4: PSRR test block diagram shown in Figure 1 denotes the test setup used to measure PSRR. Note 5: Volume ramping interval starts from establishment of a valid MCLK to LRCLK ratio. Total time is proportional to the sample
rate (f
S
). 20ms based on 48ksps operation.
Note 6: In external SCLK mode, LRCLK duty cycles are not limited, provided all data formatting requirements are met. See Figure 4. Note 7: The LRCLK duty cycle must be 50% ±1/2 MCLK period in internal SCLK mode. Note 8: The SCLK/LRCLK ratio can be set to 32, 48, or 64, depending on the MCLK/LRCLK ratio selected. See Figure 4.
Figure 1. PSRR Test Block Diagram
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INTERNAL SCLK MODE
LRCLK Duty Cycle (Note 7) 50 %
Internal SCLK Period t
LRCLK Edge to Internal SCLK
SDATA Valid to Internal SCLK Rising Setup Time
ISCLK
t
ISCLKR
t
ISDS
t
ISDH
(Note 8) 1/f
t
MCLK period = t
MCLK
MCLK
SCLK
t
MCLK
+ 10
t
ISCLK
/2 ns
ns
ns
V
DD
LOUT, ROUT
SPECTRUM
ANALYZER
AUDIO SIGNAL
GENERATOR
AT 1kHz)
(100mV
P-P
DC POWER SUPPLY
(5VDC)
Z
G
SCLK
LRCLK
MCLK
ACTIVE CLOCKS
+
-
SD ATA
MAX5556
GND
Low-Cost Stereo Audio DAC
MAX5556
_______________________________________________________________________________________ 5
(VDD= +5V, V
GND
= 0V, R
OUT_
= 10k, C
OUT_
= 10pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
-0.25
-0.15
-0.20
-0.05
-0.10
0.05
0
0.10
0.20
0.15
0.25
0 0.1 0.2 0.3 0.4 0.5
PASSBAND RIPPLE
MAX5556 toc04
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-130
-120
-140 0 2 4 6 8 101214161820
FREQUENCY (kHz)
AMPLITUDE (dBr)
0dBFS FFT
MAX5556 toc05
16,000-SAMPLE FFT USING 1kHz INPUT
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-130
-120
-140 0 2 4 6 8 101214161820
FREQUENCY (kHz)
AMPLITUDE (dBr)
-60dBFS FFT
MAX5556 toc06
16,000-SAMPLE FFT USING 1kHz INPUT
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0 0.2 0.3 0.40.1 0.5 0.6 0.7 0.90.8 1.0
STOPBAND REJECTION
MAX5556 toc01
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
-100
-80
-90
-60
-70
-40
-50
-30
-10
-20
0
0.40 0.44 0.48 0.52 0.56 0.60
TRANSITION BAND
MAX5556 toc02
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
-10
-7
-8
-9
-6
-5
-4
-3
-2
-1
0
0.40 0.440.42 0.46 0.48 0.50 0.52
TRANSITION BAND DETAIL
MAX5556 toc03
FREQUENCY (NORMALIZED TO fS)
AMPLITUDE (dB)
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-130
-120
-140 0 2 4 6 8 101214161820
FREQUENCY (kHz)
AMPLITUDE (dBr)
IDLE-CHANNEL NOISE FFT
MAX5556 toc07
16,000-SAMPLE FFT WITH NO INPUT
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-130
-120
-140 0 2 4 6 8 101214161820
FREQUENCY (kHz)
AMPLITUDE (dBr)
TWIN-TONE IMD FFT
MAX5556 toc08
16,000-SAMPLE FFT WITH 13kHz AND 14kHz INPUT SIGNALS
-110
-100
-80
-90
-70
-60
-60 -40-50 -30 -20 -10 0
THD+N vs. AMPLITUDE
MAX5556 toc09
AMPLITUDE (dBFS)
THD+N (dBr)
UNWEIGHTED
A-WEIGHTED
INPUT = 1kHz 18-BIT SIGNAL
INTEGRATION BANDWIDTH = 20Hz TO 20kHz
Low-Cost Stereo Audio DAC
MAX5556
6 _______________________________________________________________________________________
(VDD= +5V, V
GND
= 0V, R
OUT_
= 10k, C
OUT_
= 10pF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
-110
-100
-90
-80
-70
-60
0810462 1214161820
UNWEIGHTED THD+N
vs. FREQUENCY
MAX5556 toc10
FREQUENCY (kHz)
THD+N (dBr)
INPUT = 1kHz 18-BIT SIGNAL, INTEGRATION BANDWIDTH = 20Hz TO 20kHz
0
20
10
40
30
60
50
70
02010 30 40 50
POWER DISSIPATION
vs. SAMPLE FREQUENCY
MAX5556 toc11
SAMPLE FREQUENCY (kHz)
POWER DISSIPATION (mW)
VDD = +5V INPUT = 1kHz, 0dBFS SIGNAL
5
8
7
6
9
10
11
12
13
14
15
4.75 5.054.90 5.20 5.35 5.50
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5556 toc12
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
INPUT = 1kHz, 0dBFS SIGNAL NORMAL OPERATION
STATIC DIGITAL INPUT MUTE OPERATION
5
7
6
10
9
8
11
12
14
13
15
0 1.0 1.50.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE (V
DIG
)
MAX5556 toc13
DIGITAL INPUT VOLTAGE (V
DIG
) (V)
SUPPLY CURRENT (mA)
V
IH
V
DIG
< V
IH
MUTE ENGAGED
VDD = +5.5V DC OUTPUT
V
DIG
< V
IH
NORMAL OPERATION
5ms/div
CLOCK-LOSS MUTE RECOVERY
V
OUT
1V/div
2.4V
MAX5556 toc14
CLOCK RESTORED
LOSS OF CLOCK
100ms/div
POWER-UP RESPONSE
V
OUT
1V/div
0V
MAX5556 toc15
Detailed Description
The MAX5556 stereo audio sigma-delta DAC offers a complete stereo digital-to-analog system for consumer audio applications. The MAX5556 features built-in digital interpolation/filtering, sigma-delta digital-to-analog con­version and analog output filters (Figure 2). Control logic and mute circuitry minimize audible pops and clicks dur­ing power-up, power-down, and whenever invalid clock conditions occur.
This stereo audio DAC receives input data over a 3-wire I2S-compatible interface. The MAX5556 accepts left­justified I2S data of 16 or 24 bits. This DAC also sup­ports a wide range of sample rates from 2kHz to 50kHz. Direct analog output data is routed to the right or left output by driving LRCLK high or low. See the
Clock and
Data Interface
section.
The MAX5556 supports MCLK/LRCLK ratios of 256, 384, or 512. This device allows a change to the clock speed ratio without causing glitches on the analog out­puts by internally muting the audio during invalid clock conditions. The internal mute function ramps down the audio amplitude and forces the analog outputs to a
2.4V quiescent voltage immediately upon clock loss or
change of ratio. A soft-start routine is then engaged when a valid clock ratio is re-established, producing clickless and popless continuous operation.
The MAX5556 operates from a +4.75V to +5.5V analog supply and features +87dB dynamic range with total harmonic distortion typically below -87dB.
Interpolator
The digital interpolation filter eliminates images of the baseband audio signal that exist at multiples of the input sample rate (fS). The resulting upsampled frequency spectrum has images of the input signal at multiples of 8 x fS. An additional upsampling sinc filter further reduces upsampling images up to 64 x fS. These images are ulti­mately removed through the internal analog lowpass filter and the external analog output filter.
Sigma-Delta Modulator/DAC
The MAX5556 uses a multibit sigma-delta DAC with an oversampling ratio (OSR) of 64 to achieve a wide dynam­ic range. The sigma-delta modulator accepts a 3-bit data stream from the interpolation filter at a rate of 64 x fS(fS= LRCLK frequency) and provides an analog voltage rep­resentation of that data stream.
Pin Description
Low-Cost Stereo Audio DAC
MAX5556
_______________________________________________________________________________________ 7
PIN NAME FUNCTION
Serial Audio Data Input. Data is clocked into the MAX5556 on the rising edge of the internal or
1 SDATA
2 SCLK External Serial-Clock Input. Data is strobed on the rising edge of SCLK.
3 LRCLK
4 MCLK Master Clock Input. The MCLK/LRCLK ratio must equal to 256, 384, or 512.
5 OUTR Right-Channel Analog Output
6 GND Ground
7V
8 OUTL Left-Channel Analog Output
DD
external SCLK. Data is input in two’s complement format, MSB first. The state of LRCLK determines whether data is directed to OUTL or OUTR.
Left-/Right-Channel Select Clock. Drive LRCLK low to direct data to OUTL or LRCLK high to direct data to OUTR.
Power-Supply Input. Bypass VDD to GND with a 0.1µF capacitor in parallel with a 4.7µF capacitor as close to V
as possible. Place the 0.1µF capacitor closest to V
DD
DD.
Low-Cost Stereo Audio DAC
MAX5556
8 _______________________________________________________________________________________
Integrated Analog Lowpass Filter
The DAC output of the sigma-delta modulator is fol­lowed by an analog smoothing filter that attenuates high-frequency quantization noise. The corner frequen­cy of the filter is approximately 2 x fS.
Integrated Analog Output Buffer
Following the analog lowpass filter, the analog signal is routed through internal buffers to OUTR and OUTL. The buffer can directly drive load resistances larger than 3kand load capacitances up to 100pF (Figure 3).
Figure 2. Functional Diagram
Figure 3. Load-Impedance Operating Region
V
DD
SDATA
SCLK
LRCLK
MCLK
SERIAL
INTERFACE
MAX5556
(pF)
L
125
100
INTERPOLATOR
INTERPOLATOR
75
SIGMA-DELTA
MODULATOR
SIGMA-DELTA
MODULATOR
GND
DAC
INTERNAL
REFERENCE
DAC
ANALOG
LOWPASS
FILTER
ANALOG
LOWPASS
FILTER
OUTL
BUFFER
OUTR
BUFFER
LOAD CAPACITANCE C
50
25
3
5101520
LOAD RESISTANCE RL (k)
SAFE OPERATING REGION
25
Low-Cost Stereo Audio DAC
MAX5556
_______________________________________________________________________________________ 9
Clock and Data Interface
The MAX5556 strobes serial data (SDATA) in on the ris­ing edge of SCLK. LRCLK routes data to the left or right outputs and, along with SCLK, defines the number of bits per sample transferred. The digital interpolators fil­ter data at internal clock rates derived from the MCLK frequency. Each device supports both internal and external serial clock (SCLK) modes.
SDATA Input
The serial interface strobes data (SDATA) in on the ris­ing edge of SCLK, MSB first. The MAX5556 supports four different data formats, as detailed in Figure 4.
Serial Clock (SCLK)
SCLK strobes the individual data bits at SDATA into the DAC. The MAX5556 operates in one of two modes: internal serial clock mode or external serial clock mode.
External SCLK Mode
The MAX5556 operates in external serial clock mode when SCLK activity is detected. The device returns to internal serial clock mode if no SCLK signal is detected for one LRCLK period. Figure 5 details the external serial clock mode timing parameters.
Figure 4. MAX5556 Data Format Timing
Figure 5. External SCLK Serial Timing Diagram
LRCLK
SCLK
SDATA
-1
-2 -3 -4 -5 +5 +4 +3 +2 +1 -1 -2 -3 -4 +5 +4 +3 +2 +1
MSB
INTERNAL SERIAL CLOCK MODE EXTERNAL SERIAL CLOCK MODE
2
• I
S, 16-BIT DATA AND INTERNAL SCLK =
IF MCLK/ LRCLK = 256 OR 512
32 x f
S
2
S, UP TO 24 BITS OF DATA AND INTERNAL
• I SCLK = 48 X f
DATA DIRECTED TO OUTL
IF MCLK/ LRCLK = 384
S
DATA DIRECTED TO OUTR
MSBLSB LSB
• I2S, UP TO 24 BITS OF DATA
• DATA VALID ON RISING EDGE OF SCLK
LRCLK
SCLK
SD ATA
t
SLRH
t
t
SLRS
t
SDS
SCLK
t
SCLKLtSCLKH
t
SDH
Low-Cost Stereo Audio DAC
MAX5556
10 ______________________________________________________________________________________
Internal SCLK Mode
The MAX5556 transitions from external serial clock mode to internal serial clock mode if no SCLK signal is detected for one LRCLK period. In internal clock mode, SCLK is derived from and is synchronous with MCLK
and LRCLK (operation in internal clock mode is identi­cal to an external clock mode when LRCLK is synchro­nized with MCLK). Figure 6 details the internal serial clock mode timing parameters. Figure 7 details the generation of the internal clock.
Figure 6. Internal SCLK Serial Timing Diagram
Figure 7. Internal Serial Clock Generation
LRCLK
SD ATA
INTERNAL
SCLK
t
ISCLKR
t
ISDS
t
ISDH
t
ISCLK
LRCLK
MCLK
N*
INTERNAL
SCLK
SD ATA
1
*N = MCLK/SCLK.
N/2*
Low-Cost Stereo Audio DAC
MAX5556
______________________________________________________________________________________ 11
Left/Right Clock Input (LRCLK)
LRCLK is the left/right clock input signal for the 3-wire interface and sets the sample frequency (fS). On the MAX5556, drive LRCLK low to direct data to OUTL or LRCLK high to direct data to OUTR (Figure 4). The MAX5556 accepts data at LRCLK audio sample rates from 2kHz to 50kHz.
Master Clock (MCLK)
MCLK accepts the master clock signal from an external clocking device and is used to derive internal clock fre­quencies. Set the MCLK/LRCLK ratio to 256, 384, or 512 to achieve the internal serial clock frequencies list­ed in Table 1. Table 2 details the MCLK/LRCLK ratios for three sample audio rates.
The MAX5556 detects the MCLK/LRCLK ratio during the initialization sequence by counting the number of MCLK transitions during a single LRCLK period. MCLK, SCLK, and LRCLK must be synchronous signals.
Data Formats
MAX5556 I2S Left-Justified Data Format
The MAX5556 accepts data with an I2S left-justified data format, accepting 16 or 24 bits of data. SDATA accepts data in two’s complement format with the MSB first. The MSB is valid on the second SCLK rising edge after LRCLK transitions low to high or high to low (Figure 4). Drive LRCLK low to direct data to OUTL. Drive LRCLK high to direct data to OUTR. The number of SCLK pulses with LRCLK high or low determines the number of bits transferred per sample. If fewer than 24 bits of data are written, the remaining LSBs are set to 0. If more than 24 bits are written, any bits after the LSB are ignored.
The MAX5556 accepts up to 24 bits of data in external serial clock mode or when the MCLK/LRCLK ratio is 384 (internal serial clock = 48 x f
S
) in internal serial clock mode. The DAC also accepts 16 bits of data in internal serial clock mode when the MCLK/LRCLK ratio is 256 or 512 (internal serial clock = 32 x f
S
).
External Analog Filter
Use an external lowpass analog filter to further reduce harmonic images, noise, and spurs. The external analog filter can be either active or passive depending upon performance and design requirements. For example fil­ters, see Figures 8 and 9 and the
Applications
Information
section. Careful attention should be paid when selecting capacitors for audio signal path applica­tions. NPO and C0G types are recommended as are alu­minum electrolytics and low-ESR tantalum varieties. Use of generic ceramic types is not recommended and may result in degraded THD performance. Always consult manufacturers’ data sheets and applications information.
Table 1. Internal and External Clock Frequencies
Table 2. MCLK/LRCLK Ratios
Figure 8. Passive Component Analog Output Filter
INTERNAL SERIAL
CLOCK FREQUENCY
M C L K /L R C L K
= 2 5 6 O R 51 2
32 x f
S
M C L K /L R C L K
= 3 8 4
48 x f
S
EXTERNAL SERIAL
CLOCK FREQUENCY
User defined
(Figure 4)
LRCLK
(kHz)
44.1 11.2896 16.9344 22.5792
MCLK/LRCLK
= 256
32 8.1920 12.2880 16.3840
48 12.2880 18.4320 24.5760
MCLK (MHz)
MCLK/LRCLK
= 384
MCLK/LRCLK
= 512
R = 560Ω
OUTL
100kΩ
MAX5556
C = 1.5nF
R = 560Ω
OUTR
100kΩ
C = 1.5nF
Low-Cost Stereo Audio DAC
MAX5556
12 ______________________________________________________________________________________
Figure 9. Active Component Analog Output Filter
OUTR
33pF
56pF
+5V
24.3k5.23k
MAX5556
OUTL
V
BIAS
2.4V
5.23k 24.3k
33pF
V
BIAS
2.4V
10k 59k
56pF
+5V
10k 59k
Low-Cost Stereo Audio DAC
MAX5556
______________________________________________________________________________________ 13
Pop and Click Suppression
The MAX5556 features a pop and click supression rou­tine to reduce the unwanted audible effects of system transients. This routine produces glitch-free operation
at the outputs during power-on, loss of clock, or invalid clock conditions. See Figure 10 for a detailed state dia­gram during transient conditions.
Figure 10. Internal State Diagram
OUTPUTS HELD
AT CURRENT LEVELS
LofC
QUIESCENT LEVELS (< 1 SECOND)
VALID CLOCK
RATIO RE-ESTABLISHED
VALID CLOCK
RATIO RE-ESTABLISHED
LofC
OUTPUTS IMMEDIATELY
RETURNED TO DC
QUIESCENT LEVELS
LofC
NO POWER APPLIED
POWER-UP
OUTPUTS HELD
AT GROUND
VALID CLOCK
RATIO ESTABLISHED
OUTPUTS LINEARLY
RAMPED TO DC
INTERNAL REGISTERS
INITIALIZED (MUTE)
LOSS-
OF-
POWER
EVENT
SOFT-START
VOLUME RAMPING
LofC = LOSS-OF-CLOCK EVENT
LofC
INVALID RATIO DETECTED MCLK TIME OUT SCLK INT/EXT MODE CHANGED LRCLK LOSS
NORMAL OPERATION
(FULL VOLUME)
OUTPUTS IMMEDIATELY RETURNED TO GROUND
Low-Cost Stereo Audio DAC
MAX5556
14 ______________________________________________________________________________________
Power-Up
Once the MAX5556 recognizes a valid MCLK/LRCLK ratio (256, 384, or 512), the analog outputs (OUTR and OUTL) are enabled in stages using a glitchless ramping routine. First, the outputs ramp up to the quiescent out­put voltage at a rate of 5V/s typ (see Figure 11). After the outputs reach the quiescent voltage, the converted data
stream begins soft-start ramping, achieving the full-scale operation over a 20ms period.
If invalid clock signals are detected while the outputs are DC ramping to their quiescent state, the outputs stop ramping and hold their preset values until valid clock signals are restored (Figure 12).
Figure 11. Power-Up Sequence
Figure 12. Invalid Clock Output Response
OUTPUT
VOLTAGE
(OUTR OR OUTL)
VALID MCLK/LRCLK RATIO
DETECTED
RAMPS UP
V
OUT_
TO QUIESCENT
VOLTAGE AT 5V/s (TYP)
SETTLES AT
V
OUT_
QUIESCENT VOLTAGE (2.4V)
BEGINS TO
V
OUT_
FOLLOW THE DATA. THE AMPLITUDE IS RAMPED
TO FULL SCALE (20ms TYP)
INVALID CLOCK
CONDITION
OUTPUT
VOLTAGE
(OUTR OR OUTL)
TIME
MUTE: V FORCED TO DC QUIESCENT
VALID MCLK/LRCLK
RE-ESTABLISHED AND MCLK
EQUAL OR GREATER THAN
MINIMUM OPERATING FREQUENCY
TIME
IMMEDIATELY
OUT_
LEVEL (2.4V)
SOFT-START
V
OUT_
RAMPING (20ms TYP)
Low-Cost Stereo Audio DAC
MAX5556
______________________________________________________________________________________ 15
Loss of Clock and Invalid Clock Conditions
The MAX5556 mutes both outputs after detecting one of four invalid clock conditions. The device mutes its output to prevent propagation of pops, clicks, or cor­rupted data through the signal path. The MAX5556 forces the outputs to the quiescent DC voltage (2.4V) to prevent clicks in capacitive-coupled systems. Invalid clock conditions include:
1) MCLK/LRCLK ratio changes between 256, 384,
and 512
2) Transition between internal and external serial-
clock mode
3) Invalid MCLK/LRCLK ratio
4) MCLK falls below the minimum operating
frequency 2kHz
When the MCLK/LRCLK ratio returns to 256, 384, or 512 and MCLK is equal or greater than its minimum operating frequency, the MAX5556 output returns to its full-scale setting over a soft-start mute time of 20ms (Figure 12).
Power-Down
When the positive supply is removed from the MAX5556, the output discharges to ground. When power is restored, the power-up ramp routine engages once a valid clock ratio is established (see the
Power-
Up
section).
Avoid violating absolute maximum conditions by sup­plying digital inputs to the part or forcing voltages on the analog outputs during a loss-of-power event.
Applications Information
Low-Cost Line-Level Solution
Connect the MAX5556 output through a passive output filter as detailed in Figure 8 for a low-cost solution. This lowpass filter yields single-pole (20dB/decade) roll-off at a corner frequency (fC) determined by:
In the case of Figure 8, fCis approximately 190kHz.
High-Performance Line-Level Solution
For enhanced performance, connect the MAX5556 output to an active filter by using an operational amplifi­er as shown in Figure 9. The use of an active filter allows for steeper roll-off, more efficient filtering, and also adds the capability of a programmable output gain.
Power-Supply Sequencing
For correct power-up sequencing, apply VDDand then connect the input digital signals. Do not apply digital sig­nals before VDDis applied.
Do not violate any of the absolute maximum ratings by removing power with the digital inputs still connected. To correctly power down the device, first disconnect the digital input signals, and then remove VDD.
Power-Supply Connections and Ground
Management
Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and analog outputs to minimize losses due to parasitic trace resistance. Large traces also aid in mov­ing heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Route the analog paths (GND, VDD, OUTL, and OUTR) away from the digital signals. Connect a 0.1µF capacitor in parallel with a 4.7µF capacitor as close to VDDas possible. Low ESR-type capacitors are recommended for supply decoupling applications. A small value C0G-type bypass capacitor located as close to the device as possible is recommended in parallel with larger values.
f
RC
C
=
1
2π
Low-Cost Stereo Audio DAC
MAX5556
16 ______________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 SO S8+5
21-0041 90-0096
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Low-Cost Stereo Audio DAC
Revision History
REVISION
NUMBER
0 5/06 Initial release
1 2/11
REVISION
DATE
DESCRIPTION
Added lead-free and automotive information, updated the Absolute Maximum Ratings, removed all references to unreleased products MAX5557/MAX5558/MAX5559, updated the Typical Operating Circuit.
MAX5556
PAGES
CHANGED
1–4, 7–19
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
17
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