Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DIGITAL INPUTS
Input High Voltage (Note 4)V
Input Low VoltageV
Low-Level Output VoltageV
Input Leakage CurrentI
Input Capacitance5pF
DYNAMIC CHARACTERISTICS
NONVOLATILE MEMORY
Data RetentionTA = +85°C50Years
Endurance
POWER SUPPLY
Power-Supply VoltageV
Standby CurrentI
Programming Current
LEAK
DD
DD
VDD = 3.4V to 5.25V2.4
IH
VDD < 3.4V0.7 x V
V
IL
OL
= 2.7V to 5.25V (Note 4)0.8V
DD
3mA sink current0.4V
MAX5417_100
MAX5418_50Wiper -3dB Bandwidth (Note 5)
MAX5419_25
TA = +25°C200,000
= +85°C50,000
T
A
Digital inputs = V
= +25°C
T
A
During nonvolatile write;
digital inputs = V
or GND,
DD
or GND (Note 6)
DD
DD
2.705.25V
0.51µA
200400µA
V
±1µA
kHz
Stores
TIMING CHARACTERISTICS
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA=
+25°C. See Figures 1 and 2.) (Note 7)
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA=
+25°C. See Figures 1 and 2.) (Note 7)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Data Setup Timet
Data Hold Timet
SDA, SCL Rise Timet
SDA, SCL Fall Timet
Setup Time for STOP Conditiont
Bus Free Time Between STOP
and START Condition
Pulse Width of Spike Suppressedt
Maximum Capacitive Load for
Each Bus Line
Write NV Register Busy Timet
Note 1: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDDand L = GND. The
Note 2: The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = GND.
Note 3: The wiper resistance is measured using the source currents given in Note 2. For operation to V
Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (V
MAX5417/MAX5418/MAX5419
Note 5: Wiper at midscale with a 10pF load (DC measurement). L = GND; an AC source is applied to H; and the W output is mea-
Note 6: The programming current operates only during power-up and NV writes.
Note 7: SCL clock period includes rise and fall times t
Note 8: Wiper settling time is the worst-case 0% to 50% rise time measured between consecutive wiper positions. H = VDD,
Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to
Note 10: The idle time begins from the initiation of the stop pulse.
wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
For the 5V condition, the wiper terminal is driven with a source current of 80µA for the 50kΩ configuration, 40µA for the
100kΩ configuration, and 20µA for the 200kΩ configuration. For the 3V condition, the wiper terminal is driven with a source
current of 40µA for the 50kΩ configuration, 20µA for the 100kΩ configuration, and 10µA for the 200kΩ configuration.
Resistance vs. Temperature in the Typical Operating Characteristics.
0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.
sured. A 3dB bandwidth occurs when the AC W/H value is 3dB lower than the DC W/H value.
from a voltage level of (V
L = GND, and the wiper terminal is unloaded and measured with a 10pF oscilloscope probe (see the Typical OperatingCharacteristics for the tap-to-tap switching transient).
this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.
SU-DAT
HD-DAT
SU-STO
+ VIH) / 2.
IL
R
F
t
BUF
SP
C
B
BUSY
Minimum power-up rate = 0.2V/ms1.3µs
(Note 9)400pF
(Note 10)12ms
and tF. All digital input signals are specified with tR= tF= 2ns and timed
The MAX5417/MAX5418/MAX5419 nonvolatile, lineartaper, digital potentiometers perform the function of a
mechanical potentiometer by replacing the mechanics
with a simple 2-wire digital interface, allowing communication with multiple devices. Each device performs the
same function as a discrete potentiometer or variable
resistor and has 256 tap points.
The devices feature an internal, nonvolatile EEPROM
used to store the wiper position for initialization during
power-up. The fast-mode I
2
C-compatible serial interface
allows communication at data rates up to 400kbps, minimizing board space and reducing interconnection complexity in many applications. Each device is available with
one of four factory-preset addresses (see the
Selector
Guide
) and features an address input for a total of eight
unique address combinations.
The MAX5417/MAX5418/MAX5419 provide three nomi-
nal resistance values: 50kΩ (MAX5417), 100kΩ
(MAX5418), or 200kΩ (MAX5419). The nominal resistor
temperature coefficient is 35ppm/°C end-to-end, and
only 5ppm/°C ratiometric. This makes the devices ideal
for applications requiring a low-temperature-coefficient
variable resistor, such as low-drift, programmable gainamplifier circuit configurations.
The MAX5417/MAX5418/MAX5419 are available in a
3mm x 3mm 8-pin TDFN package, and are specified
over the extended -40°C to +85°C temperature range.
Applications
Mechanical Potentiometer Replacement
Low-Drift Programmable-Gain Amplifiers
Volume Control
Liquid-Crystal Display (LCD) Contrast Control
Features
o Power-On Recall of Wiper Position from
Nonvolatile Memory
o Tiny 3mm x 3mm 8-Pin TDFN Package
o 35ppm/°C End-to-End Resistance Temperature
Coefficient
o 5ppm/°C Ratiometric Temperature Coefficient
o 50kΩ/100kΩ/200kΩ Resistor Values
o Fast I
2
C-Compatible Serial Interface
o 500nA (typ) Static Supply Current
o Single-Supply Operation: +2.7V to +5.25V
o 256 Tap Positions
o ±0.5 LSB DNL in Voltage-Divider Mode
o ±0.5 LSB INL in Voltage-Divider Mode
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND...........................................................-0.3V to +6.0V
All Other Pins to GND.................................-0.3V to (V
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA= +25°C.)
TIMING CHARACTERISTICS
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA=
+25°C. See Figures 1 and 2.) (Note 7)
DIGITAL INPUTS
V
= 3.4V to 5.25V2.4
Input High Voltage (Note 4)V
Input Low VoltageV
Low-Level Output VoltageV
Input Leakage CurrentI
Input Capacitance5pF
DYNAMIC CHARACTERISTICS
Wiper -3dB Bandwidth (Note 5)
NONVOLATILE MEMORY
Data RetentionTA = +85°C50Years
Endurance
POWER SUPPLY
Power-Supply VoltageV
Standby CurrentI
Programming Current
IH
IL
OL
LEAK
DD
DD
DD
VDD < 3.4V0.7 x V
V
= 2.7V to 5.25V (Note 4)0.8V
DD
3mA sink current0.4V
MAX5417_100
MAX5418_50
MAX5419_25
TA = +25°C200,000
T
= +85°C50,000
A
Digital inputs = V
T
= +25°C
A
During nonvolatile write;
digital inputs = V
or GND,
DD
or GND (Note 6)
DD
DD
±1µA
kHz
Stores
2.705.25V
0.51µA
200400µA
V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
ANALOG SECTION
MAX5417_500
ns
DIGITAL SECTION
SCL Clock Frequencyf
Setup Time for START Conditiont
Hold Time for START Conditiont
CLK High Timet
CLK Low Timet
IL
SCL
SU-STA
HD-STA
HIGH
LOW
MAX5418_600Wiper Settling Time (Note 8)t
MAX5419_1000
400kHz
0.6µs
0.6µs
0.6µs
1.3µs
MAX5417/MAX5418/MAX5419
256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
Note 1: The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDDand L = GND. The
wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 2: The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = GND.
For the 5V condition, the wiper terminal is driven with a source current of 80µA for the 50kΩ configuration, 40µA for the
100kΩ configuration, and 20µA for the 200kΩ configuration. For the 3V condition, the wiper terminal is driven with a source
current of 40µA for the 50kΩ configuration, 20µA for the 100kΩ configuration, and 10µA for the 200kΩ configuration.
Note 3: The wiper resistance is measured using the source currents given in Note 2. For operation to V
DD
= 2.7V, see Wiper
Resistance vs. Temperature in the
Typical Operating Characteristics.
Note 4: The device draws higher supply current when the digital inputs are driven with voltages between (VDD- 0.5V) and (GND +
0.5V). See Supply Current vs. Digital Input Voltage in the
Typical Operating Characteristics.
Note 5: Wiper at midscale with a 10pF load (DC measurement). L = GND; an AC source is applied to H; and the W output is mea-
sured. A 3dB bandwidth occurs when the AC W/H value is 3dB lower than the DC W/H value.
Note 6: The programming current operates only during power-up and NV writes.
Note 7: SCL clock period includes rise and fall times t
R
and tF. All digital input signals are specified with tR= tF= 2ns and timed
from a voltage level of (V
IL
+ VIH) / 2.
Note 8: Wiper settling time is the worst-case 0% to 50% rise time measured between consecutive wiper positions. H = V
DD
,
L = GND, and the wiper terminal is unloaded and measured with a 10pF oscilloscope probe (see the
Typical Operating
Characteristics
for the tap-to-tap switching transient).
Note 9: An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to
this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.
Note 10: The idle time begins from the initiation of the stop pulse.
TIMING CHARACTERISTICS (continued)
(VDD= +2.7V to +5.25V, H = VDD, L = GND, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VDD= +5V, TA=
+25°C. See Figures 1 and 2.) (Note 7)
The MAX5417/MAX5418/MAX5419 contain a resistor
array with 255 resistive elements. The MAX5417 has a
total end-to-end resistance of 50kΩ, the MAX5418 has
an end-to-end resistance of 100kΩ, and the MAX5419
has an end-to-end resistance of 200kΩ. The
MAX5417/MAX5418/MAX5419 allow access to the high,
low, and wiper terminals for a standard voltage-divider
configuration. H, L, and W can be connected in any
desired configuration as long as their voltages fall
between GND and V
DD
.
A simple 2-wire I2C-compatible serial interface moves
the wiper among the 256 tap points. A nonvolatile memory stores the wiper position and recalls the stored wiper
position in the nonvolatile memory upon power-up. The
nonvolatile memory is guaranteed for 50 years for wiper
data retention and up to 200,000 wiper store cycles.
Figure 1. I2C Serial-Interface Timing Diagram
Figure 2. Load Circuit
PINNAMEFUNCTION
1VDDPower-Supply Input. 2.7V to 5.25V voltage range. Bypass with a 0.1µF capacitor from VDD to GND.
2SCLI2C-Interface Clock Input
3SDAI2C-Interface Data Input
4A0Address Input. Sets the A0 bit in the device ID address.
5GNDGround
6LLow Terminal
7WWiper Terminal
8HHigh Terminal
—EP
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical point.
The MAX5417/MAX5418/MAX5419 consist of a resistor
array with 255 resistive elements; 256 tap points are
accessible to the wiper, W, along the resistor string
between H and L. The wiper tap point is selected by
programming the potentiometer through the 2-wire (I
2
C)
interface. Eight data bits, an address byte, and a control byte program the wiper position. The H and L terminals of the MAX5417/MAX5418/MAX5419 are similar to
the two end terminals of a mechanical potentiometer.
The MAX5417/MAX5418/MAX5419 feature power-on
reset circuitry that loads the wiper position from nonvolatile memory at power-up.
Digital Interface
The MAX5417/MAX5418/MAX5419 feature an internal,
nonvolatile EEPROM that stores the wiper state for initialization during power-up. The shift register decodes
the control and address bits, routing the data to the
proper memory registers. Data can be written to a
volatile memory register, immediately updating the
wiper position, or data can be written to a nonvolatile
register for storage.
The volatile register retains data as long as the device
is powered. Once power is removed, the volatile register is cleared. The nonvolatile register retains data even
after power is removed. Upon power-up, the power-on
reset circuitry controls the transfer of data from the nonvolatile register to the volatile register.
Serial Addressing
The MAX5417/MAX5418/MAX5419 operate as a slave
that receives data through an I2C- and SMBus™-compatible 2-wire interface. The interface uses a serial data
access (SDA) line and a serial clock line (SCL) to
achieve communication between master(s) and
slave(s). A master, typically a microcontroller, initiates
all data transfers to the MAX5417/MAX5418/MAX5419,
and generates the SCL clock that synchronizes the
data transfer (Figure 1).
The MAX5417/MAX5418/MAX5419 SDA line operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kΩ, is required on the SDA bus.
The MAX5417/MAX5418/MAX5419 SCL operates only
as an input. A pullup resistor, typically 4.7kΩ, is
required on the SCL bus if there are multiple masters
on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output.
Each transmission consists of a START (S) condition
(Figure 3) sent by a master, followed by the
MAX5417/MAX5418/MAX5419 7-bit slave address plus
the 8th bit (Figure 4), 1 command byte (Figure 7) and 1
data byte, and finally a STOP (P) condition (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START condition by transitioning SDA from
high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP
condition by transitioning the SDA from low to high
while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 5).
Figure 3. Start and Stop Conditions
Figure 4. Slave Address
SMBus is a trademark of Intel Corporation.
SDA
SCL
S
START
CONDITION
SDA
SCL
*See the Ordering Information/Selector Guide section for other address options.
01
MSBLSB
P
STOP
CONDITION
A0
NOP/WACK010*0*
MAX5417/MAX5418/MAX5419
256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure
6). Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse,
so the SDA line is stable low during the high period of the
clock pulse. When the master transmits to the
MAX5417/MAX5418/MAX5419, the devices generate the
acknowledge bit because the MAX5417/MAX5418/
MAX5419 are the recipients.
Slave Address
The MAX5417/MAX5418/MAX5419 have a 7-bit-long
slave address (Figure 4). The 8th bit following the 7-bit
slave address is the NOP/W bit. Set the NOP/W bit low for
a write command and high for a no-operation command.
The MAX5417/MAX5418/MAX5419 are available in one
of four possible slave addresses (Table 1). The first 4
bits (MSBs) of the MAX5417/MAX5418/MAX5419 slave
addresses are always 0101. The next 2 bits are factory
programmed (see Table 1). Connect the A0 input to
either GND or V
DD
to toggle between two unique
device addresses for a part. Each device must have a
unique address to share the bus. Therefore, a maximum of eight MAX5417/MAX5418/MAX5419 devices
can share the same bus.
A write to the MAX5417/MAX5418/MAX5419 consists of
the transmission of the device’s slave address with the
8th bit set to zero, followed by at least 1 byte of information (Figure 7). The 1st byte of information is the
command byte. The bytes received after the command
byte are the data bytes. The 1st data byte goes into the
internal register of the MAX5417/MAX5418/MAX5419 as
selected by the command byte (Figure 8).
Command Byte
Use the command byte to select the source and destination of the wiper data (nonvolatile or volatile memory
registers) and swap data between nonvolatile and
volatile memory registers (see Table 2).
Command Descriptions
VREG: The data byte writes to the volatile memory register and the wiper position updates with the data in the
volatile memory register.
NVREG: The data byte writes to the nonvolatile memory register. The wiper position is unchanged.
NVREGxVREG: Data transfers from the nonvolatile
memory register to the volatile memory register (wiper
position updates).
VREGxNVREG: Data transfers from the volatile memory register into the nonvolatile memory register.
Figure 7. Command Byte Received
Figure 8. Command and Single Data Byte Received
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
SA0SLAVE ADDRESSCONTROL BYTE
NOP/W
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX5417/MAX5418/MAX5419 REGISTERS
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
SAA
0SLAVE ADDRESSCONTROL BYTEDATA BYTE
NOP/W
D15 D14 D13 D12 D11 D10 D9D8D1 D0D3 D2D5 D4D7 D6
D15D14D13D12D11D10D9D8
AP
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
ACKNOWLEDGE FROM
MAX5417/MAX5418/MAX5419
1 BYTE
A
P
MAX5417/MAX5418/MAX5419
256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
The internal EEPROM consists of an 8-bit nonvolatile
register that retains the value written to it before the
device is powered down. The nonvolatile register is
programmed with the midscale value at the factory.
Power-Up
Upon power-up, the MAX5417/MAX5418/MAX5419
load the data stored in the nonvolatile memory register
into the volatile memory register, updating the wiper
position with the data stored in the nonvolatile memory
register. This initialization period takes 10µs.
Standby
The MAX5417/MAX5418/MAX5419 feature a low-power
standby. When the device is not being programmed, it
goes into standby mode and power consumption is
typically 500nA.
Applications Information
The MAX5417/MAX5418/MAX5419 are intended for circuits requiring digitally controlled adjustable resistance, such as LCD contrast control (where voltage
biasing adjusts the display contrast), or for programmable filters with adjustable gain and/or cutoff frequency.
Positive LCD Bias Control
Figures 9 and 10 show an application where the voltage-divider or variable resistor is used to make an
adjustable, positive LCD bias voltage. The op amp provides buffering and gain to the resistor-divider network
made by the potentiometer (Figure 9) or to a fixed
resistor and a variable resistor (see Figure 10).
Programmable Filter
Figure 11 shows the configuration for a 1st-order programmable filter. The gain of the filter is adjusted by
R2, and the cutoff frequency is adjusted by R3. Use the
following equations to calculate the gain (G) and the
3dB cutoff frequency (fC):
Figure 9. Positive LCD Bias Control Using a Voltage-Divider
Figure 10. Positive LCD Bias Control Using a Variable Resistor
12345678 9 1011121314151617 18 19 20 2122232425 26 27 P
A6 A5 A4 A3 A2 A1 A0ACK
TX
NV V R3 R2 R1 R0 ACK D7 D6 D5 D4 D3D2 D1 D0 ACK
R
G
=+
=
f
C
1
1
R
2
××
23π
1
RC
5V
H
MAX5417
MAX5418
MAx5419
W
L
30V
V
OUT
MAX5417
MAX5418
MAX5419
5V
H
W
L
30V
V
OUT
Adjustable Voltage Reference
Figure 12 shows the MAX5417/MAX5418/MAX5419 used
as the feedback resistors in multiple adjustable voltagereference applications. Independently adjust the output
voltage of the MAX6160 from 1.23V to VIN- 0.2V by
changing the wiper positions of the MAX5417/
MAX5418/MAX5419.
Offset Voltage and Gain Adjustment
Connect the high and low terminals of one potentiometer
of a MAX5417 between the NULL inputs of a MAX410
and the wiper to the op amp’s positive supply to nullify
the offset voltage over the operating temperature range.
Install the other potentiometer in the feedback path to
adjust the gain of the MAX410 (see Figure 13).
Figure 13. Offset Voltage and Gain Adjustment Circuit
Figure 11. Programmable Filter
Pin Configuration
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.
8 TDFN-EPT833-1
21-0137
W
V
IN
H
MAX5417
MAX5418
MAX5419
L
R3
MAX6160
MAX5417
MAX5418
MAX5419
+5V
V
GND
5V
87H
6
5
MAX5417
MAX5418
MAX5419
6
WSCL
L
GNDA0
C
R1
H
R2
W
L
V
OUT
7
1
3
8
MAX410
2
W
L
R1
4
-5V
H
TOP VIEW
IN
OUT
W
ADJ
V0 REF
H
L
V
SDA
+
1
DD
2
MAX5417
3
MAX5418
MAX5419
4
TDFN
MAX5417/MAX5418/MAX5419
256-Tap, Nonvolatile, I2C-Interface,
Digital Potentiometers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
33/09Changes to add details about exposed pad, corrections to Table 2, style edits1, 8, 12–15
44/10
REVISION
DATE
DESCRIPTION
Ad d ed l ead - fr ee p ackag es to O r d er i ng Infor m ati on, ad d ed S ol d er i ng Tem p er atur e to
Ab sol ute M axi m um Rati ng s, cor r ected C ond i ti ons for D i ffer enti al Li near i ty i n E l ectr i cal
C har acter i sti cs, cor r ected A
i n P i n D escr i p ti on, cor r ected Fi g ur es 12 and 13
0
PAGES
CHANGED
1, 2, 8, 13
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