Datasheet MAX533BEEE, MAX533BCPE, MAX533AMJE, MAX533AEPE, MAX533AEEE Datasheet (Maxim)

19-1080; Rev 0; 6/96

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

_______________General Description

The MAX533 serial-input, voltage-output, 8-bit quad
digital-to-analog converter (DAC) operates from a sin­gle +2.7V to +3.6V supply. Internal precision buffers
swing rail to rail, and the reference input range includes
both ground and the positive rail. The MAX533 features
a 1µA shutdown mode.

The serial interface is double buffered: a 12-bit input
shift register is followed by four 8-bit buffer registers
and four 8-bit DAC registers. The 12-bit serial word
consists of eight data bits and four control bits (for DAC
selection and special programming commands). Both
the input and DAC registers can be updated indepen­dently or simultaneously with a single software com­mand. Two additional asynchronous control pins, LDAC
and CLR, provide simultaneous updating or clearing of
the input and DAC registers.

The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A
buffered data output allows daisy chaining of serial
devices.

In addition to 16-pin DIP and CERDIP packages, the
MAX533 is available in a 16-pin QSOP that occupies
the same area as an 8-pin SO.

________________________Applications

Digital Gain and Offset Adjustments
Programmable Attenuators
Programmable Current Sources
Portable Instruments

__________________Pin Configuration

TOP VIEW

OUTB
OUTA

REF

UPO

PDE

LDAC

CLR

DOUT

1
2
3
4
5
6
7
8

MAX533

DIP/QSOP

16

OUTC

15

OUTD

14

AGND



13

VDD
DGND

12
11

DIN

10

SCLK

9

CS

____________________________Features

♦ +2.7V to +3.6V Single-Supply Operation
♦ Ultra-Low Supply Current:

0.7mA while Operating
1µA in Shutdown Mode

♦ Ultra-Small 16-Pin QSOP Package
♦ Ground to V

Reference Input Range

DD

♦ Output Buffer Amplifiers Swing Rail to Rail
♦ 10MHz Serial Interface, Compatible with SPI, QSPI

(CPOL = CPHA = 0 or CPOL = CPHA = 1), and
Microwire

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy Chaining
♦ Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

♦ Software Shutdown
♦ Software-Programmable Logic Output
♦ Asynchronous Hardware Clear Resets All Internal

Registers to Zero

______________Ordering Information

PART

MAX533ACPE
MAX533BCPE
MAX533ACEE 0°C to +70°C
MAX533BCEE 0°C to +70°C 16 QSOP
MAX533BC/D 0°C to +70°C Dice*
MAX533AEPE -40°C to +85°C 16 Plastic DIP
MAX533BEPE -40°C to +85°C 16 Plastic DIP
MAX533AEEE -40°C to +85°C 16 QSOP
MAX533BEEE -40°C to +85°C 16 QSOP
MAX533AMJE -55°C to +125°C 16 CERDIP**
MAX533BMJE -55°C to +125°C 16 CERDIP**

*Dice are tested at TA= +25°C.
**Contact factory for availability and processing to MIL-STD-883.

Functional Diagram appears at end of data sheet.

TEMP. RANGE PIN-PACKAGE

0°C to +70°C
0°C to +70°C

16 Plastic DIP
16 Plastic DIP
16 QSOP

INL

(LSB)

±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2

MAX533

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________

Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

ABSOLUTE MAXIMUM RATINGS

VDDto DGND ..............................................................-0.3V, +6V

to AGND...............................................................-0.3V, +6V

V

DD

Digital Input Voltage to DGND ....................................-0.3V, +6V

Digital Output Voltage to DGND....................-0.3V, (V

AGND to DGND..................................................................±0.3V

REF................................................................-0.3V, (V

OUT_ ...........................................................................-0.3V, V

MAX533

Maximum Current into Any Pin............................................50mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DD

DD

+ 0.3V)
+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VDD= +2.7V to +3.6V, V
Typical values are at V

STATIC ACCURACY

Integral Nonlinearity
(Note 1)

Zero-Code-Error Supply
Rejection

Zero-Code Temperature
Coefficient

Full-Scale Error Supply
Rejection

Full-Scale Temperature
Coefficient

REFERENCE INPUTS

Input Voltage Range

DAC OUTPUTS

Output Voltage Range

= 2.5V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= T

REF

= +3V and TA= +25°C.)

DD

MAX533A
MAX533B
Guaranteed monotonic (all codes)
Code = 00 hex

Code = 00 hex, VDD= 2.7V to 3.6V

Code = 00 hex
Code = FF hex mV±30Full-Scale Error
Code = FF hex, VDD= 2.7V to 3.6V

Code = FF hex

(Note 2)
(Note 3)

RL= open
Code = FF hex, RLfrom 10kΩ to ∞

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW

QSOP (derate 8.3mW/°C above +70°C).....................667mW

CERDIP (derate 10.00mW/°C above +70°C)..............800mW

Operating Temperature Ranges

MAX533 _ C_ E..................................................0°C to +70°C

DD

MAX533 _ E_ E ...............................................-40°C to +85°C

MAX533 _ MJE .............................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

to T

MIN

CONDITIONS

, unless otherwise noted.

MAX

UNITSMIN TYP MAXSYMBOLPARAMETER

±1
±2

DD

REF

Bits8Resolution
LSBINL
LSB±1.0DNLDifferential Nonlinearity (Note 1)

mV±20ZCEZero-Code Error

LSB1

µV/°C±10

LSB1

µV/°C±10

V0V
kΩ322 460 598Input Resistance
pF10Input Capacitance
dB-60Channel-to-Channel Isolation
dB-70AC Feedthrough

V0V

LSB0.25Load Regulation

2 _______________________________________________________________________________________

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +2.7V to +3.6V, V
Typical values are at V

DIGITAL INPUTS

Input High Voltage
Input Low Voltage
Input Current
Input Capacitance

DIGITAL OUTPUTS

Output High Voltage
Output Low Voltage

DYNAMIC PERFORMANCE

Digital Feedthrough and
Crosstalk

Signal-to-Noise Plus
Distortion Ratio

POWER SUPPLIES

Power-Supply Voltage
Supply Current

= 2.5V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= T

REF

= +3V and TA= +25°C.)

DD

CONDITIONS

V

IH

V

IL

IN

IN

OH
OL

SINAD

DD

I

DD

VIN= 0V or V
(Note 4)

I

SOURCE

I

SINK

CODE = FF hex
To 1/2LSB, from code 00 to code FF hex

(Note 5)

VREF = 0V, code 00 to code FF hex (Note 6)
Code 80 hex to code 7F hex

V

REF

code = FF hex
V

REF

V

REF

MAX533C/E
MAX533M

DD

= TBDmA

= 1.6mA

= 2.5Vp-p at 1kHz, VDD= 3V,

= 2.5Vp-p at 10kHz
= 0.5Vp-p, 3dB bandwidth

MIN

to T

, unless otherwise noted.

MAX

DD

-70

-62

60Wideband Amplifier Noise

0.68 1.3

0.68 1.5

DD

UNITSMIN TYP MAXSYMBOLPARAMETER

µV

MAX533

V0.7V

V0.3V
µA±1.0I
pF10C

VVDD- 0.5V

V0.4V

V/µs0.6Voltage-Output Slew Rate

µs6Output Settling Time

nV-s5
nV-s50Digital-to-Analog Glitch Impulse

dB

kHz380Multiplying Bandwidth

RMS

V2.7 3.6V

mA

µA110Shutdown Current

TIMING CHARACTERISTICS

(VDD= +2.7V to +3.6V, V
Typical values are at V

VDDRise to CS Fall Setup Time
(Note 4)

LDAC Pulse Width Low

CS Rise to LDAC Fall Setup

Time (Note 7)

CLR Pulse Width Low

CS Pulse Width High

= 2.5V, AGND = DGND = 0V, C

REF

= +3V and TA= +25°C.)

DD

t

VDCS

t

LDAC

t

CLL

t

CLW

t

CSW

_______________________________________________________________________________________ 3

MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M

= 100pF, TA= T

DOUT

CONDITIONS

MIN

to T

, unless otherwise noted.

MAX

40 20
50 25
40
50
40 20
50 25
90

100

UNITSMIN TYP MAXSYMBOLPARAMETER

50
60

µs

ns

ns

ns

ns

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

TIMING CHARACTERISTICS (continued)

(VDD= +2.7V to +3.6V, V
Typical values are at V

PARAMETER SYMBOL MIN TYP MAX UNITS

SERIAL-INTERFACE TIMING

SCLK Clock Frequency (Note 8) f

MAX533

SCLK Pulse Width High t

SCLK Pulse Width Low t

CS Fall to SCLK Rise Setup
Time

SCLK Rise to CS Rise Hold Time

DIN to SCLK Rise to Setup Time t
DIN to SCLK Rise to Hold Time t

SCLK Rise to DOUT Valid
Propagation Delay (Note 9)

SCLK Fall to DOUT Valid
Propagation Delay (Note 10)

SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Setup
Time

= 2.5V, AGND = DGND = 0V, C

REF

= +3V and TA= +25°C.)

DD

CLK

CH

CL

t

CSS

t

CSH

DS

DH

t

DO1

t

DO2

t

CS0

t

CS1

MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M

MAX533C/E
MAX533M

MAX533M

MAX533M
MAX533C/E
MAX533M
MAX533C/E
MAX533M

= 100pF, TA= T

DOUT

CONDITIONS

MIN

to T

, unless otherwise noted.

MAX

40
50
40
50
40
50

0 ns

40
50

0 ns

40
50
40
50

10

8.3

200MAX533C/E
230
210MAX533C/E
250

MHz

ns

ns

ns

ns

ns

ns

ns

Note 1: INL and DNL are measured with R
Note 2: V
Note 3: V

Note 4: Guaranteed by design, not production tested.
Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of V
Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other

Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for t
Note 8: When DOUT is not used. If DOUT is used, f
Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V

4 _______________________________________________________________________________________

or equal to the maximum offset specification to code FF hex (full scale). See

= 2.5Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all

REF

other DAC’s codes to 00 hex.

= 2.5Vp-p, 10kHz. DAC code = 00 hex.

REF

DAC.

referenced to ground. Nonlinearity is measured from the first code that is greater than

L

max is 4MHz, due to the SCLK to DOUT propagation delay.

CLK

LDAC

DAC Linearity and Voltage Offset

’s final value.

OUT

or longer after CS goes high.

DD

DD

section.

).

).

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

__________________________________________Typical Operating Characteristics

(VDD= +3V, TA = +25°C, unless otherwise noted.)

MAX533

MAX533

DAC ZERO-CODE OUTPUT VOLTAGE vs.

1.50

1.25

1.00

0.75

0.50

0.25

DAC ZERO-CODE OUTPUT VOLTAGE (V)

SHUTDOWN SUPPLY CURRENT (µA)

OUTPUT SINK CURRENT

DAC CODE = 00 HEX
LOAD TO V

DD



VDD = V

= 3.0V

REF



0

0

12345

DAC OUTPUT SINK CURRENT (mA)

SHUTDOWN SUPPLY CURRENT vs.

5

3



3

2



1

0

-55

TEMPERATURE

VDD = +5.0V


VDD = +3.0V


-35 -15 52545
TEMPERATURE (°C)

-30

-40

-50

THD + NOISE (dB)

-60

-70





VDD = V

0

_______________________________________________________________________________________

DAC FULL-SCALE OUTPUT VOLTAGE vs.

5.0

MAX533-TOC1

4.5

4.0


3.5

= 5.0V

REF

678

65 85

105

THD + NOISE AT DAC OUTPUT vs.

REFERENCE AMPLITUDE

VDD = +3.0V

= SINE WAVE

V

REF

CENTERED AT 1.2V
DAC C0DE = FF HEX
80kHz LOWPASS FILTER

0.5 1.0 1.5

REFERENCE AMPLITUDE (V

3.0


2.5

DAC FULL-SCALE OUTPUT VOLTAGE (V)

2.0

0

1000

MAX533-TOC4

800



600

400



SUPPLY CURRENT (µA)

200

0

V

REF

V

REF

0

= 20kHz

= 1kHz

p-p

125

OUTPUT SOURCE CURRENT

VDD = V

DAC CODE = FF HEX
LOAD TO GND

VDD = V

246810

DAC OUTPUT SOURCE CODE (mA)

SUPPLY CURRENT vs.

REFERENCE VOLTAGE (V

ALL DAC CODES = FF HEX

ALL DAC CODES = 00 HEX

0.5 1.0 1.5
REFERENCE VOLTAGE (V)

MAX533-TOC7

2.0

)

1000

= 5.0V

REF

REF

= +3.0V)

DD

2.0

THD + NOISE (dB)

MAX533-TOC2

800



600

400



SUPPLY CURRENT (µA)

= 3.0V

2.5

-20

-30

-40

-50

-60

-70
1 0.1 101 100

200

12

3.0

VDD = +3.0V
V
CENTERED AT 1.2V
DAC CODE = FF HEX
500kHz LOWPASS FILTER

0

-55

1000

MAX533-TOC5

800



600

400



SUPPLY CURRENT (µA)

200

0

THD + NOISE AT DAC OUTPUT vs.

REFERENCE FREQUENCY

= SINE WAVE

REF

V

= 1V

REF

P-P

FREQUENCY (kHz)

SUPPLY CURRENT vs.

TEMPERATURE

DAC CODE = FF HEX

VDD = +5.0V

= +4.5V

V

REF

DAC CODE = 00 HEX

-35 -15 52545
TEMPERATURE (°C)

SUPPLY CURRENT vs.

REFERENCE VOLTAGE (V

ALL DAC CODES = FF HEX

ALL DAC CODES = 00 HEX

0

0.5 1.0 1.5

2.0

REFERENCE VOLTAGE (V)

V

= 2V

REF

p-p

V

= 0.5V

REF

p-p

MAX533-TOC3

VDD = +3.0V

= +2.5V

V

REF

65 85

DD

3.0

2.5

3.5

MAX533-TOC8

105

= +5.0V)

4.0

4.5

125

MAX533-TOC6

5.0

5

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

____________________________Typical Operating Characteristics (continued)

(VDD= +3V, TA = +25°C, unless otherwise noted.)



SINE WAVE

p-p

FREQUENCY (MHz)

1

MAX533-TOC11

5

0

MAX533

-5

-10

-15

-20

RELATIVE OUTPUT (dB)

-25

-30

REFERENCE INPUT FREQUENCY RESPONSE

V

= 0.1V

REF

CENTERED AT 2.5V
DAC CODE = FF HEX

= +3.0V

V

DD



0.01 0.1 10

WORST-CASE 1LSB DIGITAL

STEP CHANGE (NEGATIVE)



SINE WAVE

p-p

FREQUENCY (MHz)

1

MAX533-TOC10

MAX533-TOC9

REFERENCE FEEDTHROUGH vs. FREQUENCY

-20

VDD = +3.0V

= 3V

V

REF

-30

DAC CODE = 00 HEX

-40

-50

-60

RELATIVE OUTPUT (dB)

-70

-80

0.01 0.1 10

WORST-CASE 1LSB DIGITAL

STEP CHANGE (POSITIVE)

MAX533-TOC12

CS
2V/div

OUTA
50mV/div

V

= 3.0V

DD

= 2.5V

V

REF



SCLK = 333kHz
SCLK t

R

= 3.0V

V

DD

= tF = 25ns

2µs/div

DAC CODE = 80 TO 7F hex
NO LOAD



CLOCK FEEDTHROUGH

2µs/div

V

= 2.5V

REF

DAC CODE = 80 hex
NO LOAD

MAX533-TOC13

SCLK
2V/div

OUTA
10mV/div

V

= 3.0V

DD

= 2.5V

V

REF

= 3.0V

V

DD

= 2.5V

V

REF



2µs/div

DAC CODE = 7F TO 80 hex
NO LOAD

POSITIVE SETTLING TIME



5µs/div

DAC CODE = 00 TO FF hex
NO LOAD

6 _______________________________________________________________________________________

MAX533-TOC14

CS
2V/div

OUTA
50mV/div

CS
2V/div

OUTA
1V/div

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

____________________________Typical Operating Characteristics (continued)

(VDD= +3V, TA = +25°C, unless otherwise noted.)

POSITIVE SETTLING TIME

5µs/div

= 3.0V

V

DD

= 2.5V

V

REF



MAX533-TOC15

DAC CODE = 01 TO FF hex
NO LOAD

CS
2V/div

OUTA
1V/div

NEGATIVE SETTLING TIME

5µs/div

= 3.0V

V

DD

= 2.5V

V

REF



MAX533-TOC16

DAC CODE = FF TO 00 hex
NO LOAD

CS
2V/div

OUTA
1V/div

______________________________________________________________Pin Description

PIN

13

DAC B Voltage OutputOUTB1
DAC A Voltage OutputOUTA2
Reference-Voltage InputREF3
Software-Programmable Logic OutputUPO4
Power-Down Enable. Must be high to enter software shutdown mode.PDE5

6

LDAC

7

CLR

DOUT8

9

CS

SCLK10

Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents
of each input latch to its respective DAC latch.

Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and
sets all DAC outputs to zero.

Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling
edge of SCLK (Table 1).

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are
executed when CS returns high.

Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising
edge (A0 = A1 = 1, see Table 1).

Serial Data Input. Data is clocked in on the rising edge of SCLK.DIN11
Digital GroundDGND12

DD

Power Supply, +2.7V to +3.6VV
Analog GroundAGND14
DAC D Voltage OutputOUTD15
DAC C Voltage OutputOUTC16

FUNCTIONNAME

MAX533

_______________________________________________________________________________________

7

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

INSTRUCTION

EXECUTED

CS

• • •

SCLK

MAX533

• • •

DIN

C1

DOUT

MODE 1

DOUT

MODE 0

(DEFAULT)

A1

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 D6 D5 D4 D3 D2 D1



A1

C0 D7 D6 D5 D4 D3 D2 D1 D0

A0

DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT

A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 C1 C0 D7

Figure 1. 3-Wire Interface Timing

CS

t

t

CS0

CSS

SCLK

t

DS

DIN

DOUT

MSB LSB

DACA

t

CH

t

CL

t

DH

• • •

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

DACD

• • •

A1

A0 C1 C0 D7

D0

A1

• • •

A1

t

CP

t

D02

t

D01

D6 D5 D4 D3 D2 D1

t

CSH

t

CSW

D0

A1

t

CS1

t

CLL

LDAC

Figure 2. Detailed Serial-Interface Timing Diagram

8 _______________________________________________________________________________________

t

LDAC

2.7V, Low-Power, 8-Bit Quad DAC

LDAC

with Rail-to-Rail Output Buffers

_______________Detailed Description

Serial Interface

At power-on, the serial interface and all digital-to­analog converters (DACs) are cleared and set to code
zero. The serial data output (DOUT) is set to transition
on SCLK's falling edge.

The MAX533 communicates with microprocessors
through a synchronous, full-duplex, 3-wire interface
(Figure 1). Data is sent MSB first and can be transmit­ted in one 4-bit and one 8-bit (byte) packet or in one
12-bit word. If a 16-bit word is used, the first four bits
are ignored. A 4-wire interface adds a line for LDAC
and allows asynchronous updating. The serial clock
(SCLK) synchronizes the data transfer. Data is transmit­ted and received simultaneously.

Figure 2 shows the detailed serial-interface timing.
Please note that the clock should be low if it is stopped
between updates. DOUT does not go into a high­impedance state if the clock idles or CS is high.

Serial data is clocked into the data registers in MSB-first
format, with the address and configuration information
preceding the actual DAC data. Data is clocked in on
SCLK’s rising edge while CS is low. Data at DOUT is
clocked out 12 clock cycles later, either at SCLK’s falling
edge (default or mode 0) or rising edge (mode 1).

Chip select (CS) must be low to enable the DAC. If CS
is high, the interface is disabled and DOUT remains
unchanged. CS must go low at least 40ns before the
first rising edge of the clock pulse to properly clock in
the first bit. With CS low, data is clocked into the
MAX533’s internal shift register on the rising edge of
the external serial clock. Always clock in the full 12 bits
because each time CS goes high the bits currently in
the input shift register are interpreted as a command.
SCLK can be driven at rates up to 10MHz.

The 12-bit serial input format shown in Figure 3 com­prises two DAC address bits (A1, A0), two control bits
(C1, C0), and eight bits of data (D7...D0).

The 4-bit address/control code configures the DAC as
shown in Table 1.

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

Serial Input Data Format and Control Codes

A0

C1

C0

8-Bit Data0 1Address

A1

(LDAC = H)

When performing a single update operation, A1 and A0
select the respective input register. At the rising edge
of CS, the selected input register is loaded with the cur-
rent shift-register data. All DAC outputs remain
unchanged. This preloads individual data in the input
register without changing the DAC outputs.

D1D2D3D4D5D6D7

D0

Load Input and DAC Registers

A0

C1

C0

8-Bit Data1 1Address

A1

(LDAC = H)

This command directly loads the selected DAC register at
CS’s rising edge. A1 and A0 set the DAC address. Current
shift-register data is placed in the selected input and DAC
registers.

For example, to load all four DAC registers simultaneously
with individual settings (DAC A = 0.5V, DAC B = 1V,
DAC C = 1.5V, and DAC D = 2V), four commands are
required. First, perform three single input register
update operations for DACs A, B, and C (C1 = 0). The
final command loads input register D and updates all
four DAC registers from their respective input registers.

D1D2D3D4D5D6D7

D0

MAX533

THIS IS THE FIRST BIT SHIFTED IN

A1 A0 C1 C0 D7 D6

DOUT

CONTROL AND
ADDRESS BITS

Figure 3. Serial Input Format

_______________________________________________________________________________________ 9

MSB

... D1 D0

8-BIT DAC DATA

LSB

DIN

Software “

A0

C1

xxx xx xxx0 00 1

A1

(LDAC = 1)

All DAC registers are updated with the contents of their
respective input registers at CS’s rising edge. With the
exception of using CS to execute, this performs the
same function as the asynchronous LDAC.

” Command

D0D1D2D3D4D5D6D7C0

2.7V, Low-Power, 8-Bit Quad DAC

LDAC

with Rail-to-Rail Output Buffers

12-BIT SERIAL WORD

A1

MAX533

A0

0
0
1
1

0
0
1
1

0
1
0
1

0
1
0
1

1

0
1

1
0 XX X X X X X X X0

1

C1

C0

D7 . . . . . . . . D0

0
0
0
0

1
1
1
1

0

0
0

1
0

1

1
1
1
1

1
1
1
1

0

0
0

0

0

010 XX X X X X X X X1

8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data

8-bit DAC data
8-bit DAC data
8-bit DAC data
8-bit DAC data

Load All DACs with Shift-Register Data

A1 A0 C1 C0 D7

1 0 0 0 8-Bit Data

(LDAC = X)

D6 D5 D4 D3 D2 D1

All four DAC registers are updated with shift-register
data. This command allows all DACs to be set to any
analog value within the reference range. This command
can be used to substitute CLR if code 00 hex is pro­grammed, which clears all DACs.

Software Shutdown

A1 A0 C1 C0 D7

1 1 0 0 xxx xxxxx

(LDAC = X, PDE = H)

D6 D5 D4 D3 D2 D1

Shuts down all output buffer amplifiers, reducing sup­ply current to 10µA max.

D0

D0

FUNCTION

Load input register A; all DAC outputs unchanged.

1

Load input register B; all DAC outputs unchanged.

1

Load input register C; all DAC outputs unchanged.

1

Load input register D; all DAC outputs unchanged.

1

Load input register A; all DAC outputs updated

1

Load input register B; all DAC outputs updated

1

Load input register C; all DAC outputs updated

1

Load input register D; all DAC outputs updated.

1

Software LDAC commands. Update all DACs from

1X X X X X X X X 0

their respective input registers. Also bring the part out
of shutdown mode.

Load all DACs with shift-register data. Also bring the

X8-bit DAC data1

part out of shutdown mode.
Software shutdown (provided PDE is high)

XX X X X X X X X1

UPO goes low.010 XX X X X X X X X0
UPO goes high.0

XX X X X X X X X0

No operation (NOP); shift data in shift registers.
Set DOUT phase—SCLK rising (mode 1). DOUT

clocked out on rising edge of SCLK. All DACs updated

XX X X X X X X X1

from their respective input registers.
Set DOUT phase—SCLK falling (mode 0). DOUT

clocked out on falling edge of SCLK. All DACs up­dated from their respective registers (default).

User-Programmable Output (UPO)

A1 A0 C1 C0 D7

0 0 1 0 xxxxxxxx Low
0 1 1 0 xxxxxxxx High

(LDAC = X)

D6 D5 D4 D3 D2 D1

D0

UPO

Output

User-programmable logic output for controlling another
device across an isolated interface. Example devices
are gain control of an amplifier, a 4mA to 20mA amplifi­er, and a polarity output for a motor speed control.

No Operation (NOP)

A1

A0

(LDAC = X)

C1

C0

xxx xxxxx0 00 0

D1D2D3D4D5D6D7

The NOP command (no operation) allows data to be
shifted through the MAX533 shift register without affect­ing the input or DAC registers. This is useful in daisy
chaining (also see the

Daisy Chaining Devices

section).

D0

10 ______________________________________________________________________________________

2.7V, Low-Power, 8-Bit Quad DAC

CLR

with Rail-to-Rail Output Buffers

For this command, the data bits are “Don't Cares.” As
an example, three MAX533s are daisy chained (A, B,
and C), and devices A and C need to be updated. The
36-bit-wide command would consist of one 12-bit word
for device C, followed by an NOP instruction for device
B and a third 12-bit word with data for device A. At CS’s
rising edge, device B will not change state.

Set DOUT Phase—SCLK Rising (Mode 1)

A1

(LDAC = x)

C1

A0

1 01 1 xxxxxxxx

D0D1D2D3D4D5D6D7C0

Mode 1 resets the serial-output DOUT to transition at
SCLK’s rising edge. Once this command is issued,
DOUT’s phase is latched and will not change except on
power-up or if the specific command to set the phase
to falling edge is issued.

This command also loads all DAC registers with the con­tents of their respective input registers, and is identical to
the “LDAC” command.

Set DOUT Phase—SCLK Falling (Mode 0, Default)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

xxxxxxxx1 0 1 0

(LDAC = x)

This command resets DOUT to transition at SCLK’s falling
edge. The same command also updates all DAC registers
with the contents of their respective input registers, identical
to the “LDAC” command.

LDAC Operation (Hardware)

LDAC is typically used in 4-wire interfaces (Figure 7). This
command is level sensitive, and it allows asynchronous
hardware control of the DAC outputs. With LDAC low, the
DAC registers are transparent, and any time an input regis­ter is updated, the DAC output immediately follows.

Clear DACs with

Strobing the CLR pin low causes an asynchronous
clear of input and DAC registers and sets all DAC out­puts to zero. Similar to the LDAC pin, CLR can be
invoked at any time, typically when the device is not
selected (CS = H). When the DAC data is all zeros, this
function is equivalent to the “Update all DACs from Shift
Registers” command.

DOUT is the internal shift register’s output. DOUT can

Serial Data Output

be programmed to clock out data on SCLK’s falling
edge (mode 0) or rising edge (mode 1). In mode 0, out­put data lags input data by 12.5 clock cycles, maintain­ing compatibility with Microwire and SPI. In mode 1,
output data lags input data by 12 clock cycles. On
power-up, DOUT defaults to mode 0 timing. DOUT
never three-states; it always actively drives either high
or low and remains unchanged when CS is high.

SCLK

MAX533

DIN

CS



Figure 4. Connections for Microwire

MAX533

DIN

SCLK

CS

Figure 5. Connections for SPI/QSPI

SK

SO

MICROWIRE

PORT

I/0

MOSI

SPI/QSPI

PORT

SCK

I/0

CPOL = 0, CPHA = 0

MAX533

______________________________________________________________________________________ 11

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

The MAX533 is Microwire™ and SPI™/QSPI™ compati-

Interfacing to the Microprocessor

ble. For SPI and QSPI, clear the CPOL and CPHA con­figuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL
= CPHA = 1 configuration can also be used if the
DOUT output is ignored.

The MAX533 can interface with Intel’s 80C5X/80C3X
family in mode 0 if the SCLK clock polarity is inverted.

MAX533

More universally, if a serial port is not available, three
lines from one of the parallel ports can be used for bit
manipulation.

Digital feedthrough at the voltage outputs is greatly

The MAX533 uses a matrix decoding architecture for
the DACs, which saves power in the overall system.
The external reference voltage is divided down by a
resistor string placed in a matrix fashion. Row and col­umn decoders select the appropriate tab from the
resistor string to provide the needed analog voltages.
The resistor string presents a code-independent input
impedance to the reference and guarantees a mono­tonic output. Figure 8 shows a simplified diagram of the
four DACs.

minimized by operating the serial clock only to update
the registers. Also see the Clock Feedthrough photo in
the

Typical Operating Characteristics

section. The

clock idle state is low.

Daisy-Chaining Devices

Any number of MAX533s can be daisy-chained by con­necting DOUT of one device to DIN of the following
device in the chain. The NOP instruction (Table 1)
allows data to be passed from DIN to DOUT without
changing the input or DAC registers of the passing

The voltage at REF sets the full-scale output voltage for
all four DACs. The 460kΩ typical input impedance at
REF is code independent. The output voltage for any
DAC can be represented by a digitally programmable
voltage source as follows:

V

= (NB x V

OUT

where NB is the numerical value of the DAC’s binary
input code.

device. A 3-wire interface updates daisy-chained or
individual MAX533s simultaneously by bringing CS
high (Figure 6).

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

SCLK

SCLK

MAX533

SCLK

MAX533

SCLK

MAX533

REF

Analog Section

DAC Operation

Reference Input

) / 256

DIN

CS

SCLK

DIN

CS

Figure 6. Daisy-chained or individual MAX533s are simultaneously updated by bringing CS high. Only three wires are required.

12 ______________________________________________________________________________________

DIN

CS

SCLK

DIN

CS

DOUT DOUT DOUT

DEVICE A

MAX533

DIN

CS

DEVICE B

DIN

CS

DEVICE C

TO OTHER
SERIAL DEVICES

SCLK

LDAC

CS1
CS2
CS3

DIN

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

TO OTHER
SERIAL
DEVICES

MAX533

CS

MAX533

LDAC

SCLK

DIN

Figure 7. Multiple MAX533s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an
individual CS.

Output Buffer Amplifiers

All MAX533 voltage outputs are internally buffered by
precision unity-gain followers that slew at about

0.6V/µs. The outputs can swing from GND to VDD. With
a 0V to +2.5V (or +2.5V to 0V) output transition, the
amplifier outputs will typically settle to 1/2LSB in 6µs
when loaded with 10kΩ in parallel with 100pF.

The buffer amplifiers are stable with any combination of
resistive (≥10kΩ) or capacitive loads.

CS

MAX533

LDAC

SCLK

DIN

__________Applications Information

The output buffer can have a negative input offset volt­age that would normally drive the output negative, but
since there is no negative supply the output stays at 0V
(Figure 9). When linearity is determined using the end­point method, it is measured between zero code (all
inputs 0) and full-scale code (all inputs 1) after offset
and gain error are calibrated out. However, in single-

DAC Linearity and Voltage Offset

CS

LDAC

SCLK

DIN

MAX533

supply operation the next code after zero may not
change the output (Figure 9), so the lowest code that
produces a positive output is the lower endpoint.

______________________________________________________________________________________ 13

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

REF

R0

D7

MAX533

D6

D5

MSB DECODER

D4

DAC A

Figure 8. DAC Simplified Circuit Diagram

R1

LSB DECODER

D2D3

R15

R16

R255

D1 D0

Power Sequencing

The voltage applied to REF should not exceed VDDat
any time. If proper power sequencing is not possible,
connect an external Schottky diode between REF and
VDDto ensure compliance with the absolute maximum
ratings. Do not apply signals to the digital inputs before
the device is fully powered up.

Power-Supply Bypassing

and Ground Management

Connect AGND and DGND together at the IC. This
ground should then return to the highest-quality ground
available. Bypass VDDwith a 0.1µF capacitor, located
as close to VDDand DGND as possible.

Careful PC board layout minimizes crosstalk among
DAC outputs and digital inputs. Figure 10 shows sug­gested circuit board layout to minimize crosstalk.

Unipolar-Output,

Two-Quadrant Multiplication

In unipolar operation, the output voltages and the refer­ence input are the same polarity. Figure 11 shows the
MAX533 unipolar configuration, and Table 2 shows the
unipolar code.

OUTPUT



VOLTAGE



0V

NEGATIVE

OFFSET

Figure 9. Effect of Negative Offset (Single Supply)

DAC CODE

Table 2. Unipolar Code Table

DAC CONTENTS

Note: 1LSB = (V

LSBMSB

1 1 1 11 1 1 1

0 0 0 11 0 0 0

0 0 0 01 0 0 0

1 1 1 10 1 1 1

0 0 0 10 0 0 0

) (2-8) = +V

REF

REF

+V

ANALOG

OUTPUT

+V

REF

+V

REF

(––––)= +

REF

+V

REF

+V

REF

1

(––––)

256

128
256 2

0V0 0 0 00 0 0 0

255

(––––)

256
129

(––––)

256

127

(––––)

256

1

(––––)

256

V

REF

–

–––

14 ______________________________________________________________________________________

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

REFERENCE INPUT

313

REFAB

+3V

V

DD

MAX533

2

SYSTEM GND

OUTC
OUTD

AGND



OUTB
OUTA

REF

Figure 10. Suggested PC Board Layout for Minimizing
Crosstalk (Bottom View)

DAC A

SERIAL

INTERFACE

NOT SHOWN

DAC B

DAC C

DAC D

Figure 11. Unipolar Output Circuit

AGND

14 12

DGND

OUTA

1

OUTB

16

OUTC

15

OUTD

_________________________________________________________Functional Diagram

MAX533

DOUT

REGISTER

CLR

12-BIT

SHIFT

CONTROL

CS DIN

LDAC

UPO

DECODE

CONTROL

SR

SCLK

V

DD

PDE DGND AGND

REF

MAX533

INPUT

REGISTER A

INPUT

REGISTER B

INPUT

REGISTER C

INPUT

REGISTER D

DAC

REGISTER A

DAC

REGISTER B

DAC

REGISTER C

DAC

REGISTER D

DAC A

DAC B

DAC C

DAC D

OUTA

OUTB

OUTC

OUTD

______________________________________________________________________________________ 15

2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers

___________________Chip Information

TRANSISTOR COUNT: 6821

MAX533

________________________________________________________Package Information

INCHES MILLIMETERS

DIM



D

A

e

A1

B

S

H

E

A
A1
A2

B

C

0.0075
D
E

e

H

h

L
N
S

α

MIN

0.061

0.004

0.055

0.008

SEE VARIATIONS



0.150


0.230

0.010

0.016

SEE VARIATIONS




SEE VARIATIONS

0°

MAX

0.068

0.0098

0.061

0.012

0.0098


0.157


0.244

0.016

0.035



8°

MIN

1.55

0.127

1.40

0.20

0.19


3.81

0.635 BSC0.25 BSC



5.84

0.25

0.41



0°

MAX

1.73

0.25

1.55

0.31

0.25

3.99

6.20

0.41

0.89

8°

DIM



D

S

D

S

D



S

D



S




h x 45°

N

A2

α

SMALL-OUTLINE

E

C

L

INCHES MILLIMETERS

PINS

MIN

16

0.189

0.0020

0.337

0.0500

0.337

0.0250

0.386

0.0250

0.196

0.0070

0.344

0.0550

0.344

0.0300

0.393

0.0300

16
20
20
24
24
28
28

QSOP

QUARTER

PACKAGE

MAX

MIN

4.80

0.05

8.56

1.27

8.56

0.64

9.80

0.64

MAX

4.98

0.18

8.74

1.40

8.74

0.76

9.98

0.76

21-0055A

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.