2.7V, Low-Power, 8-Bit Quad DAC
with Rail-to-Rail Output Buffers
_______________General Description
The MAX533 serial-input, voltage-output, 8-bit quad
digital-to-analog converter (DAC) operates from a single +2.7V to +3.6V supply. Internal precision buffers
swing rail to rail, and the reference input range includes
both ground and the positive rail. The MAX533 features
a 1µA shutdown mode.
The serial interface is double buffered: a 12-bit input
shift register is followed by four 8-bit buffer registers
and four 8-bit DAC registers. The 12-bit serial word
consists of eight data bits and four control bits (for DAC
selection and special programming commands). Both
the input and DAC registers can be updated independently or simultaneously with a single software command. Two additional asynchronous control pins, LDAC
and CLR, provide simultaneous updating or clearing of
the input and DAC registers.
The interface is compatible with SPI™, QSPI™ (CPOL =
CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A
buffered data output allows daisy chaining of serial
devices.
In addition to 16-pin DIP and CERDIP packages, the
MAX533 is available in a 16-pin QSOP that occupies
the same area as an 8-pin SO.
________________________Applications
Digital Gain and Offset Adjustments
Programmable Attenuators
Programmable Current Sources
Portable Instruments
__________________Pin Configuration
TOP VIEW
OUTB
OUTA
REF
UPO
PDE
LDAC
CLR
DOUT
1
2
3
4
5
6
7
8
MAX533
DIP/QSOP
16
OUTC
15
OUTD
14
AGND
13
VDD
DGND
12
11
DIN
10
SCLK
9
CS
____________________________Features
♦ +2.7V to +3.6V Single-Supply Operation
♦ Ultra-Low Supply Current:
0.7mA while Operating
1µA in Shutdown Mode
♦ Ultra-Small 16-Pin QSOP Package
♦ Ground to V
Reference Input Range
DD
♦ Output Buffer Amplifiers Swing Rail to Rail
♦ 10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0 or CPOL = CPHA = 1), and
Microwire
♦ Double-Buffered Registers for Synchronous
Updating
♦ Serial Data Output for Daisy Chaining
♦ Power-On Reset Clears Serial Interface and Sets
MAX533ACPE
MAX533BCPE
MAX533ACEE0°C to +70°C
MAX533BCEE0°C to +70°C16 QSOP
MAX533BC/D0°C to +70°CDice*
MAX533AEPE-40°C to +85°C 16 Plastic DIP
MAX533BEPE-40°C to +85°C 16 Plastic DIP
MAX533AEEE-40°C to +85°C 16 QSOP
MAX533BEEE-40°C to +85°C 16 QSOP
MAX533AMJE-55°C to +125°C 16 CERDIP**
MAX533BMJE-55°C to +125°C 16 CERDIP**
*Dice are tested at TA= +25°C.
**Contact factory for availability and processing to MIL-STD-883.
Functional Diagram appears at end of data sheet.
TEMP. RANGEPIN-PACKAGE
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
INL
(LSB)
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
MAX533
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
to AGND...............................................................-0.3V, +6V
V
DD
Digital Input Voltage to DGND ....................................-0.3V, +6V
Digital Output Voltage to DGND....................-0.3V, (V
AGND to DGND..................................................................±0.3V
REF................................................................-0.3V, (V
OUT_ ...........................................................................-0.3V, V
MAX533
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: INL and DNL are measured with R
Note 2: V
Note 3: V
Note 4: Guaranteed by design, not production tested.
Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of V
Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other
Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for t
Note 8: When DOUT is not used. If DOUT is used, f
Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V
Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V