MAXIM MAX5290, MAX5295 User Manual
General Description
The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltageoutput digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at
the 12-bit level. The DACs operate from a 2.7V to 5.25V
analog supply and a separate 1.8V to 3.6V digital supply. The 20MHz 3-wire serial interface is compatible
with SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct access or
daisy-chained configuration. The MAX5290–MAX5295
provide two multifunctional, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
The MAX5290/MAX5291 are 12-bit DACs, the MAX5292/
MAX5293 are 10-bit DACs, and the MAX5294/MAX5295
are 8-bit DACs. The MAX5290/ MAX5292/MAX5294 provide unity-gain-configured output buffers, while the
MAX5291/MAX5293/MAX5295 provide force-sense-configured output buffers. The MAX5290– MAX5295 are
specified over the extended -40°C to +85°C temperature
range, and are available in space-saving 4mm x 4mm,
16-pin thin QFN and 6.5mm x 5mm, 14-pin and 16-pin
TSSOP packages.
Applications
Portable Instrumentation
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Controls
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
Fast Parallel-DAC to Serial-DAC Upgrades
Features
♦ Dual, 12-/10-/8-Bit Serial DACs in 4mm x 4mm
Thin QFN and TSSOP Packages
♦ 3µs (max) 12-Bit Settling Time to 1/2 LSB
♦ Integral Nonlinearity
1 LSB (max) MAX5290/MAX5291 A-Grade (12-Bit)
1 LSB (max) MAX5292/MAX5293 (10-Bit)
1/2 LSB (max) MAX5294/MAX5295 (8-Bit)
♦ Guaranteed Monotonic, ±1 LSB (max) DNL
♦ Two User-Programmable Digital I/O Ports
♦ Single +2.7V to +5.25V Analog Supply
♦ +1.8V to AV
DD
Digital Supply
♦ 20MHz 3-Wire SPI-/QSPI-/MICROWIRE- and
DSP-Compatible Serial Interface
♦ Glitch-Free Outputs Power Up to Zero Scale,
Midscale or Full Scale
♦ Unity-Gain- or Force-Sense-Configured Output
Buffers
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3005; Rev 3; 7/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
*Future product—contact factory for availability. Specifications
are preliminary.
**EP = Exposed paddle.
Selector Guide and Pin Configurations appear at end of data
sheet.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
PART TEMP RANGE PIN-PACKAGE
MAX5290AEUD -40°C to +85°C 14 TSSOP
MAX5290BEUD -40°C to +85°C 14 TSSOP
MAX5290AETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5290BETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5291AEUE -40°C to +85°C 16 TSSOP
MAX5291BEUE -40°C to +85°C 16 TSSOP
MAX5291AETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5291BETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5292EUD -40°C to +85°C 14 TSSOP
MAX5292ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5293EUE -40°C to +85°C 16 TSSOP
MAX5293ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5294EUD -40°C to +85°C 14 TSSOP
MAX5294ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5295EUE -40°C to +85°C 16 TSSOP
MAX5295ETE* -40°C to +85°C 16 Thin QFN-EP**
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto DVDD........................................................................±6V
AGND to DGND ..................................................................±0.3V
AV
DD
to AGND, DGND.............................................-0.3V to +6V
DV
DD
to AGND, DGND ............................................-0.3V to +6V
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AV
DD
+ 0.3V) or +6V
SCLK, DIN, CS, PU,
DSP to DGND.......-0.3V to the lower of (DV
DD
+ 0.3V) or +6V
UPIO1, UPIO2
to DGND ...............-0.3V to the lower of (DV
DD
+ 0.3V) or +6V
Maximum Current into Any Pin .........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
STATIC ACCURACY
MAX5290/MAX5291 12
MAX5292/MAX5293 10Resolution N
MAX5294/MAX5295 8
Bits
±1
±2 ±4
MAX5292/MAX5293 (10-bit)
±1
Integral Nonlinearity INL
V
REF
= 2.5V at
AV
DD
= 2.7V,
V
REF
= 4.096V
at AV
DD
= 5.25V
(Note 2)
MAX5294/MAX5295 (8-bit)
LSB
Differential Nonlinearity
DNL Guaranteed monotonic (Note 2) ±1 LSB
±5
±5
MAX5292/MAX5293 (10-bit), decimal code = 21 ±5
Offset Error V
OS
MAX5294/MAX5295 (8-bit), decimal code = 5 ±5
mV
Offset-Error Drift 5
ppm of
FS/°C
±4
MAX5292/MAX5293 (10-bit) ±3 ±5
Gain Error GE
MAX5294/MAX5295 (8-bit)
±2
LSB
Gain-Error Drift 1
ppm of
FS/°C
SYMBOL
MIN TYP MAX
MAX5290A/MAX5291A (12-bit)
MAX5290B/MAX5291B (12-bit)
MAX5290A/MAX5291A (12-bit), decimal code = 40
MAX5290B/MAX5291B (12-bit), decimal code = 82
MAX5290A/MAX5291A (12-bit)
Full-scale output
MAX5290B/MAX5291B (12-bit) ±10 ±20
±0.5
±0.125 ±0.5
±0.5
±25
±25
±25
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
CONDITIONS
Power-Supply Rejection
Ratio
PSRR Full-scale output, AV
DD
= 2.7V to 3.6V
REFERENCE INPUT
Reference Input Range
V
REF
V
Reference Input
Resistance
R
REF
Normal operation (no code dependence) 145
kΩ
Reference Leakage
Current
I
REF
Shutdown mode 0.5 1 µA
DAC OUTPUT CHARACTERISTICS
Unity gain 85
SLOW mode,
full scale
Force sense 67
Unity gain
Output Voltage Noise
FAST mode,
full scale
Force sense
Unity-gain output 0
Output Voltage Range
(Note 4)
Force-sense output 0
V
DC Output Impedance
38 Ω
Short-Circuit Current AVDD = 3V, OUT_ to AGND, full scale, FAST mode 45 mA
Power-Up Time From DVDD applied, interface is functional 30 60 µs
Wake-Up Time Coming out of shutdown, outputs settled 40 µs
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only
µA
DIGITAL OUTPUTS (UPIO_)
Output High Voltage V
OH
I
SOURCE
= 2mA
DV
DD
-
0.5
V
Output Low Voltage V
OL
I
SINK
= 2mA 0.4 V
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
DVDD ≥ 2.7V 2.4
Input High Voltage V
IH
DVDD < 2.7V
0.7 x
V
DVDD > 3.6V 0.8
2.7V ≤ DVDD ≤ 3.6V 0.6
Input Low Voltage V
IL
DVDD < 2.7V 0.2
V
Input Leakage Current I
IN
±1 µA
Input Capacitance C
IN
10 pF
SYMBOL
MIN TYP MAX UNITS
0.25 AV
DV
DD
200 µV/V
200
140
110
0.01
±0.1
AV
AV
DD
DD
DD
/ 2
µV
RMS
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
CONDITIONS
UNITS
PU INPUT
Input High Voltage V
IH-PU
DVDD -
V
Input Low Voltage V
IL-PU
200 mV
Input Leakage Current I
IN-PU
PU still considered floating when connected to a
tri-state bus
nA
DYNAMIC PERFORMANCE
Fast mode 3.6
Voltage-Output Slew
Rate
SR
Slow mode 1.6
V/µs
M AX 5290/M AX 5291 fr om cod e 322 to
cod e 4095 to 1/2 LS B
23
M AX 5292/M AX 5293 fr om cod e 82 to
cod e 1023 to 1/2 LS B
1.5 3
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB
12
M AX 5290/M AX 5291 fr om cod e 322 to
cod e 4095 to 1/2 LS B
36
MAX5292/MAX5293 from code 82 to
code 1023 to 1/2 LSB
2.5 6
Voltage-Output Settling
Time (Note 5)
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB
24
µs
FB_ Input Voltage 0
V
FB_ Input Current 0.1 µA
Unity gain 200
Reference -3dB
Bandwidth (Note 6)
Force sense 150
kHz
Digital Feedthrough
CS = DV
DD
, code = zero scale, any digital input
from 0 to DV
DD
and DVDD to 0, f = 100kHz
0.1
nV-s
Digital-to-Analog Glitch
Impulse
Major carry transition 2
nV-s
(Note 3) 15
nV-s
SYMBOL
MIN TYP MAX
200mV
±200
DAC-to-DAC Crosstalk
FAST mode
SLOW mode
V
REF
/ 2
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= 2.7V to 5.25V, DVDD= 1.8V to AVDD, AGND = 0, DGND = 0, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, TA= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Range
AV
DD
V
Digital Supply Voltage
Range
DV
DD
1.8
V
Unity gain
0.8 mA
SLOW mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 2.5V
Force sense 0.9 1.2 mA
Unity gain
2
Operating Supply
Current
I
AVDD
+
I
DVDD
FAST mode, all digital inputs
at DGND or DV
DD
, no load,
V
REF
= 2.5V
Force sense 1.2 2
mA
Shutdown Supply
Current
I
AV D D ( S H D N )
+
No clocks, all digital inputs at DGND or DVDD, all
DACs in shutdown mode
0.5 1.0 µA
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
SCLK Frequency f
SCLK
2.7V < DVDD < 5.25V 20
MHz
SCLK Pulse-Width High t
CH
(Note 7) 20 ns
SCLK Pulse-Width Low t
CL
(Note 7) 20 ns
CS Fall to SCLK Rise Setup Time
t
CSS
10 ns
SCLK Rise to CS Rise Hold Time
t
CSH
5ns
SCLK Rise to CS Fall Setup Time
t
CS0
10 ns
DIN to SCLK Rise Setup Time t
DS
12 ns
DIN to SCLK Rise Hold Time t
DH
5ns
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
DO1
CL = 20pF, UPIO_ = DOUTDC1 mode 30 ns
SCLK Fall to DOUT_ Valid
Propagation Delay
t
DO2
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
30 ns
CS Rise to SCLK Rise Hold Time
t
CS1
MICROWIRE and SPI modes 0 and 3 10 ns
CS Pulse-Width High t
CSW
45 ns
I
D V D D ( S H D N )
2.70 5.25
0.55
0.85
AV
DD
SYMBOL
MIN TYP MAX
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
t
DOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
100 ns
DOUTRB Tri-State Time from CS
Rise
t
DRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
20 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
t
ZEN
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
0ns
LDAC Pulse-Width Low t
LDL
Figure 5 20 ns
LDAC Effective Delay t
LDS
Figure 6 100 ns
CLR, MID, SET Pulse-Width Low t
CMS
Figure 5 20 ns
GPO Output Settling Time t
GP
Figure 6 100 ns
GPO Output High-Impedance
Time
t
GPZ
100 ns
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Frequency f
SCLK
1.8V < DVDD < 5.25V 10
MHz
SCLK Pulse-Width High t
CH
(Note 7) 40 ns
SCLK Pulse-Width Low t
CL
(Note 7) 40 ns
CS Fall to SCLK Rise Setup Time
t
CSS
20 ns
SCLK Rise to CS Rise Hold Time
t
CSH
0ns
SCLK Rise to CS Fall Setup Time
t
CS0
10 ns
DIN to SCLK Rise Setup Time t
DS
20 ns
DIN to SCLK Rise Hold Time t
DH
5ns
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
DO1
CL = 20pF, UPIO_ = DOUTDC1 mode 60 ns
SCLK Fall to DOUT_ Valid
Propagation Delay
t
DO2
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
60 ns
CS Rise to SCLK Rise Hold Time
t
CS1
MICROWIRE and SPI modes 0 and 3 20 ns
CS Pulse-Width High t
CSW
90 ns
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 7
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
t
DOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
200 ns
DOUTRB Tri-State Time from CS
Rise
t
DRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
40 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
t
ZEN
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
0ns
LDAC Pulse-Width Low t
LDL
Figure 5 40 ns
LDAC Effective Delay t
LDS
Figure 6 200 ns
CLR, MID, SET Pulse-Width Low
t
CMS
Figure 5 40 ns
GPO Output Settling Time t
GP
Figure 6 200 ns
GPO Output High-Impedance
Time
t
GPZ
200 ns
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
SCLK Frequency f
SCLK
2.7V < DVDD < 5.25V 20
MHz
SCLK Pulse-Width High t
CH
(Note 7) 20 ns
SCLK Pulse-Width Low t
CL
(Note 7) 20 ns
CS Fall to SCLK Fall Setup Time t
CSS
10 ns
DSP Fall to SCLK Fall Setup Time
t
DSS
10 ns
SCLK Fall to CS Rise Hold Time t
CSH
5ns
SCLK Fall to CS Fall Delay t
CS0
10 ns
SCLK Fall to DSP Fall Delay t
DS0
10 ns
DIN to SCLK Fall Setup Time t
DS
12 ns
DIN to SCLK Fall Hold Time t
DH
5ns
SCLK Rise to DOUT_ Valid
Propagation Delay
t
DO1
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
30 ns
SCLK Fall to DOUTDC0 Valid
Propagation Delay
t
DO2
CL = 20pF, UPIO_ = DOUTDC0 mode 30 ns
CS Rise to SCLK Fall Hold Time t
CS1
MICROWIRE and SPI modes 0 and 3 10 ns
CS Pulse-Width High t
CSW
45 ns
DSP Pulse-Width High t
DSW
20 ns
DSP Pulse-Width Low t
DSPWL
(Note 8) 20 ns
SYMBOL
MIN TYP MAX
SYMBOL
MIN TYP MAX
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
8 _______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued)
(DVDD= 2.7V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
t
DOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
100 ns
DOUTRB Tri-State Time from CS
Rise
t
DRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
20 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
t
ZEN
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
0ns
LDAC Pulse-Width Low t
LDL
Figure 5 20 ns
LDAC Effective Delay t
LDS
Figure 6
ns
CLR, MID, SET Pulse-Width Low
t
CMS
Figure 5 20 ns
GPO Output Settling Time t
GP
Figure 6 100 ns
GPO Output High-Impedance
Time
t
GPZ
100 ns
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
SCLK Frequency f
SCLK
1.8V < DVDD < 5.25V 10
MHz
SCLK Pulse-Width High t
CH
(Note 7) 40 ns
SCLK Pulse-Width Low t
CL
(Note 7) 40 ns
CS Fall to SCLK Fall Setup Time t
CSS
20 ns
DSP Fall to SCLK Fall Setup Time
t
DSS
20 ns
SCLK Fall to CS Rise Hold Time t
CSH
0ns
SCLK Fall to CS Fall Delay t
CS0
10 ns
SCLK Fall to DSP Fall Delay t
DS0
15 ns
DIN to SCLK Fall Setup Time t
DS
20 ns
DIN to SCLK Fall Hold Time t
DH
5ns
SCLK Rise to DOUT_ Valid
Propagation Delay
t
DO1
CL = 20pF, UPIO_ = DOUTDC1 or DOUTRB
mode
60 ns
SCLK Fall to DOUTDC0 Valid
Propagation Delay
t
DO2
CL = 20pF, UPIO_ = DOUTDC0 mode 60 ns
CS Rise to SCLK Fall Hold Time t
CS1
MICROWIRE and SPI modes 0 and 3 20 ns
CS Pulse-Width High t
CSW
90 ns
DSP Pulse-Width High t
DSW
40 ns
DSP Pulse-Width Low
t
DSPWL
(Note 8)
40 ns
100
SYMBOL
MIN TYP MAX
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
_______________________________________________________________________________________ 9
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (continued)
(DVDD= 1.8V to 5.25V, DGND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO_ Modes
t
DOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
200 ns
DOUTRB Tri-State Time from CS
Rise
t
DRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
40 ns
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
t
ZEN
CL = 20pF, from 8th falling edge of SCLK to
UPIO_ driven out of tri-state
0ns
LDAC Pulse-Width Low t
LDL
Figure 5 40 ns
LDAC Effective Delay t
LDS
Figure 6
ns
CLR, MID, SET Pulse-Width Low
t
CMS
Figure 5 40 ns
GPO Output Settling Time t
GP
Figure 6 200 ns
GPO Output High-Impedance
Time
t
GPZ
200 ns
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. V
OUT
(max) = V
REF
/ 2, unless otherwise noted.
Note 2: Linearity guaranteed from decimal code 40 to 4095 for the MAX5290A/MAX5291A (12-bit, A-grade), code 82 to 4095 for the
MAX5290B/MAX5291B (12-bit, B-grade), code 21 to 1023 for the MAX5292/MAX5293 (10-bit), and code 5 to 255 for the
MAX5294/MAX5295 (8-bit).
Note 3: DAC-to-DAC crosstalk is measured as follows: outputs of DACA and DACB are set to full scale and the output of DACB is
measured. While keeping DACB unchanged, the output of DACA is transitioned to zero scale and the ∆V
OUT
of DACB is
measured. The procedure is repeated with DACA and DACB interchanged. DAC-to-DAC crosstalk is the maximum ∆V
OUT
measured.
Note 4: Represents the functional range. The linearity is guaranteed at V
REF
= 2.5V. See the Typical Operating Characteristics sec-
tion for linearity at other voltages.
Note 5: Guaranteed by design.
Note 6: The reference -3dB bandwidth is measured with a 0.1V
P-P
sine wave on V
REF
and with the input code at full scale.
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
SYMBOL
MIN TYP MAX
200
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
10 ______________________________________________________________________________________
Typical Operating Characteristics
(AVDD= DVDD= 3V, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = floating, TA= +25°C, unless otherwise noted.)
-0.8
-0.4
-0.6
0
-0.2
0.2
0.4
0 20001000 3000 4000 4096
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (MAX5290A)
MAX5290 toc01
INPUT CODE
INL (LSB)
-0.35
-0.20
-0.25
-0.30
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0 20001000 3000 4000 4096
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (MAX5291A)
MAX5290 toc02
INPUT CODE
INL (LSB)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5290 toc03
DIGITAL INPUT CODE
INL (LSB)
307220481024
-3
-2
-1
0
1
2
3
4
-4
0 4096
UNITY GAIN
B-GRADE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5290 toc04
DIGITAL INPUT CODE
INL (LSB)
768512256
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
01024
UNITY GAIN
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5290 toc05
DIGITAL INPUT CODE
INL (LSB)
19212864
-0.25
0
0.25
0.50
-0.50
0256
UNITY GAIN
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
MAX5290 toc06
DIGITAL INPUT CODE
DNL (LSB)
307220481024
-0.1
0
0.1
0.2
-0.2
0 4096
UNITY GAIN
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
MAX5290 toc07
DIGITAL INPUT CODE
DNL (LSB)
768512256
-0.025
0
0.025
0.050
-0.050
01024
UNITY GAIN
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
MAX5290 toc08
DIGITAL INPUT CODE
DNL (LSB)
19212864
-0.01
0
0.01
0.02
-0.02
0256
UNITY GAIN
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
-40 -15 10 35 60 85
INTEGRAL NONLINEARITY
vs. TEMPERATURE (A-GRADE)
MAX5290 toc09
TEMPERATURE (°C)
INL (LSB)
UNITY GAIN
FORCE
SENSE
MIDSCALE
MAX5290–MAX5295
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 11
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, V
REF
= 2.5V, RL= 10kΩ, CL= 100pF, speed mode = FAST, PU = floating, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5290 toc10
TEMPERATURE (°C)
INL (LSB)
603510-15
-2
0
2
4
-4
-40 85
UNITY GAIN
B-GRADE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
MAX5290 toc11
TEMPERATURE (°C)
DNL (LSB)
603510-15
-0.1
0
0.1
0.2
-0.2
-40 85
UNITY GAIN
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
1.0 2.0 2.51.5 3.0 3.5 4.0 4.5 5.0
MAX5290 toc12
V
REF
(V)
INL (LSB)
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (MAX5290A)
0
0.2
0.1
0.4
0.3
0.6
0.5
0.7
0.9
0.8
1.0
1.0 2.0 2.51.5 3.0 3.5 4.0 4.5 5.0
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE (MAX5291A)
MAX5290 toc13
V
REF
(V)
INL (LSB)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-40 -15 10 35 60 85
OFFSET ERROR vs. TEMPERATURE
(A-GRADE)
MAX5290 toc14
TEMPERATURE (°C)
OFFSET ERROR (mV)
UNITY GAIN
FORCE
SENSE
CODE = 40
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
OFFSET ERROR vs. TEMPERATURE
MAX5290 toc15
TEMPERATURE (°C)
OFFSET ERROR (LSB)
603510-15
-8
-6
-4
-2
0
-10
-40 85
FORCE SENSE
UNITY GAIN
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
-0.35
-0.20
-0.25
-0.30
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
-40 10-15 356085
GAIN ERROR vs. TEMPERATURE
(A-GRADE)
MAX5290 toc16
TEMPERATURE (°C)
GAIN ERROR (LSB)
UNITY GAIN
FORCE
SENSE
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
GAIN ERROR vs. TEMPERATURE
MAX5290 toc17
TEMPERATURE (°C)
GAIN ERROR (LSB)
603510-15
-8
-6
-4
-2
0
-10
-40 85
FORCE SENSE
UNITY GAIN
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
REFERENCE INPUT BANDWIDTH
MAX5290 toc18
FREQUENCY (Hz)
GAIN (dB)
1M100k10k1k
-25
-20
-15
-10
-5
0
5
-30
010M
V
REF
= 0.1V
P-P
AT 2.5V
DC
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