General Description
The MAX5181 is a 10-bit, current-output digital-to-analog converter (DAC) designed for superior performance
in signal reconstruction or arbitrary waveform generation applications requiring analog signal reconstruction
with low distortion and low-power operation. The
MAX5184 provides equal specifications, with on-chip
precision resistors for voltage-output operation. The
MAX5181/MAX5184 are designed for a 10pVs glitch
operation to minimize unwanted spurious signal components at the output. An on-board 1.2V bandgap circuit provides a well-regulated, low-noise reference that
can be disabled for external reference operation.
The devices are designed to provide a high level of signal integrity for the least amount of power dissipation.
They operate from a single 2.7V to 3.3V supply.
Additionally, these DACs have three modes of operation: normal, low-power standby, and full shutdown,
which provides the lowest possible power dissipation
with a 1µA (max) shutdown current. A fast wake-up time
(0.5µs) from standby mode to full DAC operation facilitates power conservation by activating the DAC only
when required.
The MAX5181/MAX5184 are available in 24-pin QSOP
packages and are specified for the extended (-40°C to
+85°C) temperature range. Additionally, the MAX5184
is also available in a 24-pin TQFN with exposed pad
(EP) and is specified for the extended (-40°C to +85°C)
temperature range. For lower resolution, 8-bit versions,
refer to the MAX5187/MAX5190 data sheet.
Applications
Signal Reconstruction
Arbitrary Waveform Generators (AWGs)
Direct Digital Synthesis
Imaging Applications
Features
o 2.7V to 3.3V Single-Supply Operation
o Wide Spurious-Free Dynamic Range:
70dB at f
OUT
= 2.2MHz
o Fully Differential Output
o Low-Current Standby or Full Shutdown Modes
o Internal 1.2V, Low-Noise Bandgap Reference
o Small 24-Pin QSOP and Thin QFN Packages
10-Bit, 40MHz, Current/Voltage-Output DACs
________________________________________________________________
Maxim Integrated Products
1
19-1579; Rev 5; 8/10
Pin Configurations
Ordering Information
MAX5181/MAX5184
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
*
EP = Exposed pad.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configurations continued at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX5181BEEG+ -40°C to +85°C 24 QSOP
MAX5184BEEG+ -40°C to +85°C 24 QSOP
MAX5184ETG+ -40°C to +85°C 24 TQFN-EP*
MAX5184ETG/V+ -40°C to +85°C 24 TQFN-EP*
TOP VIEW
CREF
OUTP
OUTN
AGND
AV
DACEN
CLK
REN
+
1
2
3
4
MAX5181
5
DD
PD
D0
MAX5184
6
7
8
9
10
11
12
QSOP
24
REFO
23
REFR
22
DGND
21
DV
DD
20
D9
19
D8
18
D7
17
D6CS
16
D5
15
D4
14
D3
13
D2D1
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= 3V, V
AGND
= V
DGND
= 0V, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDDto AGND, DGND .................................-0.3V to +6V
Digital Inputs to DGND.............................................-0.3V to +6V
OUTP, OUTN, CREF to AGND .................................-0.3V to +6V
V
REF
to AGND ..........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AV
DD
to DVDD.................................................................... ±3.3V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin QSOP (derate 9.50mW/°C above +70°C) ........762mW
24-Pin TQFN
(derate 20.8mW/°C above +70°C) ............................1667mW
Operating Temperature Range
MAX518_BEEG................................................-40°C to +85°C
MAX5184ETG ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution N 10 Bits
Integral Nonlinearity INL -2 ±0.5 +2 LSB
Differential Nonlinearity DNL Guaranteed monotonic -1 ±0.5 1 LSB
Zero-Scale Error
Full-Scale Error (Note 1) -40 ±15 +40 LSB
DYNAMIC PERFORMANCE
Output Settling Time To ±0.5LSB error band 25 ns
Glitch Impulse 10 pVs
Spurious-Free
Dynamic Range to
Nyquist
Total Harmonic Distortion to
Nyquist
Signal-to-Noise Ratio to
Nyquist
Clock and Data Feedthrough All 0s to all 1s 50 nVs
Output Noise 10 pA/√Hz
ANALOG OUTPUT
Full-Scale Output Voltage V
Voltage Compliance of Output -0.3 0.8 V
Output Leakage Current DACEN = 0, MAX5181 only -1 1 µA
SFDR
THD
SNR
FS
MAX5181 -2 +2
MAX5184 -8 +8
f
MAX518_BEEG
MAX5184ETG
MAX518_BEEG
MAX5184ETG f
= 40MHz, f
CLK
= 40MHz,
f
CLK
f
= 2.2MHz, TA = +25°C
OUT
f
= 40MHz, f
CLK
f
= 40MHz,
CLK
= 2.2MHz, TA = +25°C
f
OUT
f
= 40MHz,
CLK
f
= 2.2MHz, TA = +25°C
OUT
f
= 40MHz, f
CLK
= 40MHz,
f
CLK
= 2.2MHz, TA = +25°C
f
OUT
= 40MHz, f
CLK
= 500kHz 72
OUT
= 500kHz -70
OUT
= 500kHz 61
OUT
= 2.2MHz 59
OUT
57 70
-68 -63
-68 -57
56 59
400 mV
LSB
dBc
dBc
dB
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= 3V, V
AGND
= V
DGND
= 0V, f
CLK
= 40MHz, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= T
MIN
to T
MAX
, unless
otherwise noted. Typical values are at T
A
= +25°C.)
Note 1: Excludes reference and reference resistor (MAX5184) tolerance.
TIMING CHARACTERISTICS
Output Voltage Temperature
Drift
TCV
REF
50 ppm/°C
Reference Supply Rejection 0.5 mV/V
Current Gain (I
FS
/ I
REF
) 8 mA/mA
PARAMETER SYMBOL MIN TYP MAX UNITS
Digital Supply Current I
DVDD
4.2 5.0 mA
Digital Power-Supply Voltage DV
DD
2.7 3.3 V
Analog Supply Current I
AVDD
1.7 4.0 mA
Analog Power-Supply Voltage AV
DD
2.7 3.3 V
Standby Current I
STANDBY
1.0 1.5 mA
Shutdown Current I
SHDN
0.5 1 µA
Digital Input Voltage High V
IH
2 V
Output Voltage Range V
REF
1.12 1.2 1.28 V
Reference Output Drive
Capability
I
REFOUT
10 µA
Digital Input Voltage Low V
IL
0.8 V
Digital Input Current I
IN
±1 µA
Digital Input Capacitance C
IN
10 pF
DAC DATA to CLK Rise Setup
Time
t
DS
10 ns
DAC CLK Rise to DATA Hold
Time
t
DH
0 ns
CS Fall to CLK Rise Time
5 ns
CS Fall to CLK Fall Time
5 ns
DACEN Rise Time to V
OUT
0.5 µs
PD Fall Time to V
OUT
50 µs
Clock Period t
CLK
25 ns
Clock High Time t
CH
10 ns
Clock Low Time t
CL
10 ns
CONDITIONS
PD = 0, DACEN = 1, digital inputs at 0V or DV
DD
VIN= 0V or DV
DD
PD = 0, DACEN = 1, digital inputs at 0V or DV
DD
PD = 0, DACEN = 0, digital inputs at 0V or DV
DD
PD = 1, DACEN = X,digital inputs at 0V
or DVDD(X = don’t care)
Full-Scale Output Current I
FS
0.5 1 1.5
mAMAX5181 only
DAC External Output Resistor
load
R
L
400
ΩMAX5181 only
REFERENCE
POWER REQUIREMENTS
LOGIC INPUTS AND OUTPUTS
TIMING CHARACTERISTICS
3.0
2.5
1.5
2.0
1.0
-40 35-15 10 60 85
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
MAX5181/4toc04
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT (mA)
MAX5181
MAX5184
8
7
6
5
4
3
2.5 4.03.0 3.5 4.5 5.0 5.5
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5181/4toc05
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT (mA)
MAX5184
MAX5181
4.00
3.75
3.25
3.50
3.00
-40 35-15 10 60 85
DIGITAL SUPPLY CURRENT vs.
TEMPERATURE
MAX5181/4toc06
TEMPERATURE (°C)
DIGITAL SUPPLY CURRENT (mA)
MAX5184
MAX5181
610
600
590
580
570
2.5 4.03.0 3.5 4.5 5.0 5.5
STANDBY CURRENT vs.
SUPPLY VOLTAGE
MAX5181/4toc07
SUPPLY VOLTAGE (V)
STANDBY CURRENT (μA)
MAX5184
MAX5181
600
590
570
560
580
550
-40 35-15 10 60 85
STANDBY CURRENT vs.
TEMPERATURE
MAX5181/4toc08
TEMPERATURE (°C)
STANDBY CURRENT (μA)
MAX5184
MAX5181
0.14
0.12
0.10
0.06
0.08
0.04
2.5 4.03.0 3.5 4.5 5.0 5.5
SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
MAX5181/4toc09
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT (μA)
MAX5184
MAX5181
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
4 _______________________________________________________________________________________
Typical Operating Characteristics
(AVDD= DVDD= 3V, V
AGND
= V
DGND
= 0V, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs.
INPUT CODE
0.6
0.5
0.4
0.3
0.2
INL (LSB)
0.1
0
-0.1
-0.2
0 128 256 384 512 640 768 896 1024
INPUT CODE
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX5184
2.5 4.03.0 3.5 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
MAX5181/4toc01
DIFFERENTIAL NONLINEARITY vs.
INPUT CODE
0.4
0.3
0.2
0.1
0
DNL (LSB)
-0.1
-0.2
-0.3
0 128 256 384 512 640 768 896 1024
INPUT CODE
3.0
MAX5181/4toc02
2.5
2.0
1.5
ANALOG SUPPLY CURRENT (mA)
1.0
MAX5181/4toc03
MAX5181
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, V
AGND
= V
DGND
= 0V, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= +25°C, unless otherwise noted.)
4
3
1
2
0
0 400300100 200 500
OUTPUT CURRENT vs.
REFERENCE CURRENT
MAX5181/4toc13
REFERENCE CURRENT (μA)
OUTPUT CURRENT (mA)
DYNAMIC RESPONSE RISE TIME
MAX5181/4toc14
500ns/div
OUTP
150mV/
div
OUTN
150mV/
div
DYNAMIC RESPONSE FALL TIME
MAX5181/4toc15
500ns/div
OUTP
150mV/
div
OUTN
150mV/
div
SETTLING TIME
MAX5181/4toc16
12.5ns/div
OUTN
100mV/
div
OUTP
100mV/
div
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0246
81012141618
20
FFT PLOT
MAX5181/4toc17
OUTPUT FREQUENCY (MHz)
(dBc)
f
OUT
= 2.2MHz
f
CLK
= 40MHz
100
90
70
60
50
80
40
10 20 25 30 35 40 45 50 55 6015
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
MAX5181/4toc18
CLOCK FREQUENCY (MHz)
SFDR (dBc)
SHUTDOWN CURRENT vs.
0.13
0.11
0.09
0.07
SHUTDOWN CURRENT (μA)
0.05
0.03
-40 35-15 10 60 85
TEMPERATURE
MAX5181
MAX5184
TEMPERATURE (°C)
MAX5184
MAX5181
SUPPLY VOLTAGE (V)
1.28
1.27
MAX5181/4toc11
1.26
1.25
REFERENCE VOLTAGE (V)
1.24
1.23
-40 35-15 10 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
MAX5181/4toc10
REFERENCE VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.28
1.27
1.26
1.25
1.24
1.23
2.5 4.03.0 3.5 4.5 5.0 5.5
MAX5181/4toc12
MAX5181
MAX5184
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD= DVDD= 3V, V
AGND
= V
DGND
= 0V, IFS= 1mA, 400Ω differential output, CL= 5pF, TA= +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs.
OUTPUT FREQUENCY AND CLOCK FREQUENCY
78
f
= 40MHz
CLK
76
74
72
f
= 10MHz
CLK
SFDR (dBc)
70
68
66
500 1300900 1700 2100
OUTPUT FREQUENCY (kHz)
f
CLK
= 20MHz
f
f
f
CLK
CLK
CLK
= 50MHz
= 60MHz
= 30MHz
MULTITONE SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
20
0
-20
-40
-60
SFDR (dBc)
-80
-100
-120
-140
06421081412 1816 20
OUTPUT FREQUENCY (MHz)
MAX5181/4toc19
MAX5181/4toc21
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
62.4
62.2
62.0
61.8
61.6
SIINAD (dB)
61.4
61.2
61.0
60.8
0 1500500 1000 2000 2500
OUPUT FREQUENCY (kHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
74
72
70
68
SFDR (dBc)
66
64
62
60
0.5 0.75 1.0 1.25 1.5
FULL-SCALE OUTPUT CURRENT (mA)
MAX5181/4toc20
MAX5181/84-22
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 7
Pin Description
PIN
QSOP TQFN
1 22 CREF REFO
2 23 OUTP Positive Analog Output. Current output for MAX5181; voltage output for MAX5184.
3 24 OUTN Negative Analog Output. Current output for MAX5181; voltage output for MAX5184.
4 1 AGND Analog Ground
52AVDDAnalog Positive Supply, 2.7V to 3.3V
6 3 DACEN
74PD
85CS Active-Low Chip Select
9 6 CLK Clock Input
10 7 REN Active-Low Reference Enable. Connect to DGND to activate on-chip 1.2V reference.
11 8 D0 Data Bit D0 (LSB)
12–19 9–16 D1–D8 Data Bits D1–D8
20 17 D9 Data Bit D9 (MSB)
21 18 DV
22 19 DGND Digital Ground
23 20 REFR Reference Input
24 21 REFO Reference Output
— — EP
NAME FUNCTION
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGND
1: Power-up DAC with PD = DGND
X: Enter shutdown mode with PD = DVDD (X = don’t care)
Power-Down Select
0: Enter DAC standby mode (DACEN = DGND) or power-up DAC (DACEN = DVDD)
1: Enter shutdown mode
Digital Supply, 2.7V to 3.3V
DD
Exposed Pad (TQFN Only). Internally connected to AGND. Connected to the analog
ground plane (AGND).
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
8 _______________________________________________________________________________________
Detailed Description
The MAX5181/MAX5184 are 10-bit digital-to-analog converters (DACs) capable of operating with clock speeds
up to 40MHz. Each converter consists of separate input
and DAC registers, followed by a current source array
capable of generating up to 1.5mA full-scale output current (Figure 1). An integrated 1.2V voltage reference and
control amplifier determine the data converters’ full-scale
output currents/voltages. Careful reference design
ensures close gain matching and excellent drift characteristics. The MAX5184’s voltage output operation features matched 400Ω on-chip resistors that convert the
current-array current into a voltage.
Internal Reference and
Control Amplifier
The MAX5181/MAX5184 provide an integrated 50ppm/°C,
1.2V, low-noise bandgap reference that can be disabled and overridden by an external reference voltage.
REFO serves either as an external reference input or an
integrated reference output. If REN is connected to
DGND, the internal reference is selected and REFO
provides a 1.2V output. Due to its limited 10µA output
drive capability, REFO must be buffered with an external amplifier, if heavier loading is required.
The MAX5181/MAX5184 also employ a control amplifier
designed to regulate simultaneously the full-scale output current (I
FS
) for both outputs of the devices. The
output current is calculated as follows:
IFS= 8 I
REF
where I
REF
is the reference output current (I
REF
=
V
REFO/RSET
) and IFSis the full-scale output current.
R
SET
is the reference resistor that determines the
amplifier’s output current on the MAX5181 (Figure 2).
This current is mirrored into the current source array,
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
The MAX5184 converts this output current into a differential output voltage (V
OUT
) with two internal, groundreferenced 400Ω load resistors. Using the internal 1.2V
reference voltage, the MAX5184’s integrated
Figure 1. Functional Diagram
REN
AV
AGND CS DACEN PD
DD
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5184 ONLY.
REFO
REFR
CLK
1.2V REF
9.6kΩ*
OUTPUT
LATCHES
MSB
DECODE
INPUT
LATCHES
CURRENT-
SOURCE ARRAY
DAC SWITCHES
OUTPUT
LATCHES
LATCHES
D9–D0
MSB
DECODE
INPUT
400Ω*
MAX5181
MAX5184
DV
DD
CREF
OUTP
OUTN
400Ω*
DGND
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
_______________________________________________________________________________________ 9
reference output-current resistor (R
SET
= 9.6kΩ) sets
I
REF
to 125µA and IFSto 1mA.
External Reference
To disable the MAX5181/MAX5184’s internal reference,
connect REN to DVDD. A temperature-stable, external
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the current array. For improved accuracy and drift performance, choose a fixed output voltage reference such
as the 1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower-power standby mode, connect digital
inputs PD and DACEN to DGND. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEN
must be pulled high with PD held at DGND. The
MAX5181/MAX5184 typically require 50µs to wake up
and let both outputs and the reference settle.
Shutdown Mode
For lowest power consumption, the MAX5181/MAX5184
provide a power-down mode in which the reference, control amplifier, and current array are inactive and the DAC
supply current is reduced to 1µA. To enter this mode,
connect PD to DVDD. To return to active mode, connect
PD to DGND and DACEN to DVDD. About 50µs are
required for the parts to leave shutdown mode and settle
to their outputs’ values prior to shutdown. Table 1 lists the
power-down mode selection.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5181/MAX5184. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D9 through D0. The content of the input latch is
then shifted to the DAC register, and the output updates at the rising edge of the next clock.
Outputs
The MAX5181 output is designed to supply full-scale
output currents of 1mA into 400Ω loads in parallel with
a capacitive load of 5pF. The MAX5184 features integrated 400Ω resistors that restore the array current to
proportional, differential voltages of 400mV. These differential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed operational amplifier to convert the differential voltage into a
single-ended voltage.
Figure 2. Setting IFSwith the Internal 1.2V Reference and the Control Amplifier
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
MAX4040
R
SET
C
AGND
*COMPENSATION CAPACITOR (C
COMP
COMP
AGND
= 100nF) **9.6kΩ REFERENCE CURRENT-SET RESISTOR
REFO
*
R
SET
REFR
I
REF
R
SET
9.6kΩ
REN
BANDGAP
REFERENCE
**
DGND
1.2V
CURRENT-
SOURCE ARRAY
MAX5181
MAX5184
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
FOR MAX5181.
R
SET
I
FS
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
10 ______________________________________________________________________________________
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (INL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the difference between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Table 1. Power-Down Mode Selection
X = Don’t care.
Figure 3. MAX5181/MAX5184 with External Reference
Wake-Up
High-Z
High-Z
MAX5181
MAX5181
AGNDMAX5184
ShutdownX1
Last state prior to standby mode10
AGND
MAX5184
Standby00
OUTPUT STATEPOWER-DOWN MODEDACEN (DAC ENABLE)
PD
(POWER-DOWN SELECT)
AV
DD
MAX6520
EXTERNAL
1.2V
REFERENCE
AGND
REFO
REFR
R
SET
9.6kΩ*
REN
1.2V
BANDGAP
REFERENCE
DV
DD
0.1μF10μF
DGND
I
CURRENT-
SOURCE ARRAY
FS
AGND
*9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
R
SET
MAX5181
MAX5184
FOR MAX5181.
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 11
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corresponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5181. The differential
voltage across OUTP and OUTN is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
I/Q Reconstruction
in a QAM Application
The low-distortion performance of two MAX5181/
MAX5184s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) architectures where two separate buses carry the I and Q
data. A QAM signal is both amplitude (AM) and phase
modulated, created by summing two independently
modulated carriers of identical frequency but different
phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5181/MAX5184 may be used to reconstruct the
analog I and Q components.
Figure 4. Timing Diagram
t
CLK
CLK
D0–D9
t
DS
OUT N - 1
N - 1
THD 20 log
=×
⎛
(V V V V )
+++
2232425
⎜
⎜
⎝
V
1
⎞
2
⎟
⎟
⎠
t
CH
N + 1
N + 1
N
t
DH
t
CL
N
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
12 ______________________________________________________________________________________
The I/Q reconstruction system is completed by a quadrature modulator that combines the reconstructed components with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
Using the MAX5181/MAX5184 for
Arbitrary Waveform Generation
Designing a traditional arbitrary waveform generator
(AWG) requires five major functional blocks (Figure 8a):
clock generator, counter, waveform memory, DAC for
waveform reconstruction, and output filter. The waveform memory contains the sequentially stored digital
replica of the desired analog waveforms. This memory
shares a common clock with the DAC.
For each clock cycle, a counter adds one count to the
address for the waveform memory. The memory then
loads the next value to the DAC, which generates an
analog output voltage corresponding to that data value.
A DAC output filter can either be a simple or complex
lowpass filter, depending on the AWG requirements for
waveform function and frequencies. The main limitations of the AWG’s flexibility are DAC resolution and
dynamic performance, memory length, clock frequency, and the filter characteristics.
Although the MAX5181/MAX5184 offer high-frequency
operation and excellent dynamics, they are suitable for
relaxed requirements in resolution (10-bit AWGs). To
increase an AWG’s high-frequency accuracy, tempera-
Figure 5a. Integral Nonlinearity Figure 5b. Differential Nonlinearity
Figure 5c. Offset Error Figure 5d. Gain Error
7
6
5
4
3
ANALOG OUTPUT VALUE
2
1
0
000 010001 011 100 101 110
AT STEP
001 (1/4 LSB )
DIGITAL INPUT CODE
AT STEP
011 (1/2 LSB )
111
6
5
4
3
2
ANALOG OUTPUT VALUE
1
0
000 010001 011 100 101
7
GAIN ERROR
(-1 1/4 LSB)
6
IDEAL DIAGRAM
5
ANALOG OUTPUT VALUE
4
0
000 101100 110 111
ACTUAL
OFFSET
POINT
IDEAL OFFSET
POINT
ACTUAL
DIAGRAM
OFFSET ERROR
(+1 1/4 LSB)
DIGITAL INPUT CODE
3
2
1
ANALOG OUTPUT VALUE
0
000 010001 011
IDEAL DIAGRAM
1 LSB
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
DIGITAL INPUT CODE
IDEAL FULL-SCALE OUTPUT
ACTUAL
FULL-SCALE
OUTPUT
DIGITAL INPUT CODE
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 13
Figure 7. Using the MAX5181/MAX5184 for I/Q Signal Reconstruction
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
+
10μF
R
SET
+3V
+3V
D0–D9
**
0.1μF
0.1μF
AV
CLK
REFO
REFR
AV
CREF
DD
0.1μF
402Ω
402Ω
-5V
+5V
OUTPUT
MAX4108
402Ω
400Ω*
402Ω
400Ω*
*400Ω RESISTORS INTERNAL TO MAX5184 ONLY.**MAX5181 ONLY
+
10μF
DD
0.1μF
DV
DD
OUTP
MAX5181
MAX5184
OUTN
REN AGNDDGND
AV
DV
DD
+3V
10
DIGITAL
SIGNAL
PROCESSOR
10
DD
AV
DD
MAX5181
MAX5184
DV
MAX5181
MAX5184
I COMPONENT
DD
Q COMPONENT
BP
FILTER
CARRIER
FREQUENCY
BP
FILTER
0°
QUADRATURE
MODULATOR
+3V
90°
MAX2452
IF
Σ
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
14 ______________________________________________________________________________________
ture stability, wide-band tuning, and past phase-continuos frequency switching, the user may approach a
direct digital synthesis (DDS) AWG (Figure 8b). This
DDS loop supports standard waveforms that are repetitive, such as sine, square, TTL, and triangular waveforms. DDS allows for precise control of the
data-stream input to the DAC. Data for one complete
output waveform cycle is sequentially stored in a RAM.
As the RAM addresses are changing, the DAC converts the incoming data bits into a corresponding voltage waveform. The resulting output signal frequency is
proportional to the frequency rate at which the RAM
addresses are changed.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influence the MAX5181/MAX5184’s performance. Unwanted
digital crosstalk may couple through the input, reference, power-supply, and ground connections, which
may affect dynamic specifications like SNR or SFDR. In
addition, electromagnetic interference (EMI) can either
couple into or be generated by the MAX5181/
MAX5184. Therefore, grounding and power-supply
decoupling guidelines for high-speed, high-frequency
applications should be closely followed.
First, a multilayer PC board with separate ground and
power-supply planes is recommended. High-speed
signals should be run on controlled impedance lines
Figure 8b. Direct Digital Synthesis AWG
Figure 8a. Traditional Arbitrary Waveform Generation
DV
AV
DD
COUNTER
CLOCK
GENERATOR
*MAX5181 ONLY
WAVEFORM
MEMORY
(RAM)
DATA
10ADR
9.6kΩ*
DD
MAX5181
MAX5184
400Ω*
LOWPASS
RECONSTRUCTION
FILTER
VARIABLE
fc
FILTERED
WAVEFORM
(ANALOG OUTPUT)
PIR
PHASE
INCREMENT
REGISTER
*MAX5181 ONLY
A
D
D
E
R
CLOCK
GENERATOR
ACCUMULATOR
ACCUMULATOR
FEEDBACK LOOP
FOR DATA BITS
PHASE
ADR
WAVEFORM
MEMORY
(RAM)
AV
DV
DD
DD
DATA
10
MAX5181
MAX5184
400Ω*
9.6kΩ*
LOWPASS
RECONSTRUCTION
FILTER
VARIABLE
fc
FILTERED
WAVEFORM
(ANALOG OUTPUT)
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 15
directly above the ground plane. Since the MAX5181/
MAX5184 have separate analog and digital ground
buses (AGND and DGND, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
Both devices have two power-supply inputs: analog
VDD(AVDD) and digital VDD(DVDD). Each AVDDinput
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close as possible to the ground plane.
The DVDDpins should also have separate 10µF and
0.1µF capacitors adjacent to their respective pins. Try
to minimize analog load capacitance for proper operation. For best performance, bypass with low-ESR 0.1µF
capacitors to AVDD.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with additional decoupling capacitors forming a pi network can
also improve performance.
24
23
22
21
20
19
OUTN
OUTP
CREF
REFO
REFR
DGND
7
8
9
10
11
12
REN
D0
D1
D2
D3
D4
13
14
15
16
17
18
D5
D6
D7
D8
D9
DV
DD
6
EP
5
4
3
2
1
+
CLK
CS
PD
DACEN
AV
DD
AGND
MAX5184
TQFN-EP
TOP VIEW
Pin Configurations (continued)
Chip Information
SUBSTRATE CONNECTED TO AGND
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO
24 QSOP E24+1
21-0055
90-0172
24 TQFN T2444+4
21-0139
90-0222
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
4 4/03 — —
5 8/10 Added lead-free and automotive qualified parts to Ordering Information 1
REVISION
DATE
DESCRIPTION PAGES CHANGED
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