Maxim MAX5123BEEE, MAX5123AEEE, MAX5122BEEE, MAX5122AEEE Datasheet

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

General Description

The MAX5122/MAX5123 low-power, 12-bit, voltage-out­put, digital-to-analog converters (DACs) feature an inter­nal precision bandgap reference and output amplifier.

The MAX5122 operates on a single +5V supply with an
internal +2.5V reference, and offers a configurable output
amplifier. If necessary, the user can override the on-chip,
<10ppm/°C voltage reference with an external reference.
The MAX5123 has the same features as the MAX5122 but
operates from a single +3V supply and has an internal
+1.25V precision reference. The user-accessible inverting
input and output of the amplifier allows specific gain con­figurations, remote sensing, and high output drive capa­bility for a wide range of force/sense applications. Both
devices draw only 500µA of supply current, which
reduces to 3µA in power-down mode. In addition, their
power-up reset feature allows for a user-selectable initial
output state of either 0V or midscale and reduces output
glitches during power-up.

The serial interface is compatible with SPI™, QSPI™, and
MICROWIRE™, which makes the MAX5122/MAX5123
suitable for cascading multiple devices. Each DAC has
a double-buffered input organized as an input register
followed by a DAC register. A 16-bit shift register loads
data into the input register. The DAC register may be
updated independently or simultaneously with the input
register.

Both devices are available in a 16-pin QSOP package
and are specified for the extended-industrial (-40°C to
+85°C) operating temperature range. For pin-compatible
14-bit upgrades, see the MAX5171/MAX5173 data sheet;
for the pin-compatible 13-bit version, see the MAX5132/
MAX5133 data sheet.

Applications

Industrial Process Control
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
Microprocessor-Controlled Systems

Features

♦ Single-Supply Operation

+5V (MAX5122)
+3V (MAX5123)

♦ Built-In 10ppm/°C max Precision Bandgap Reference

+2.5V (MAX5122)
+1.25V (MAX5123)

♦ SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial

Interface

♦ Pin-Programmable Shutdown Mode and Power-

Up Reset (0 or Midscale Output Voltage)

♦ Buffered Output Capable of Driving 5kΩ 100pF

or 4–20mA Loads

♦ Space-Saving 16-Pin QSOP Package
♦ Pin-Compatible 13-Bit Upgrades Available

(MAX5132/MAX5133)

♦ Pin-Compatible 14-Bit Upgrades Available

(MAX5171/MAX5173)

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

________________________________________________________________

Maxim Integrated Products

1

16
15
14
13
12
11
10

9

1
2
3
4
5
6
7
8

FB V

DD

REFADJ
REF
AGND
PD
UPO
DOUT
DGND

TOP VIEW

MAX5122
MAX5123

QSOP

OUT

RSTVAL

CS

PDL
CLR

DIN

SCLK

19-1446; Rev 0; 3/99

PART

MAX5122AEEE

MAX5122BEEE -40°C to +85°C

-40°C to +85°C

TEMP. RANGE

PIN-

PACKAGE

16 QSOP
16 QSOP

Pin Configuration

Ordering Information

INL

(LSB)

±0.5

±1
MAX5123AEEE
MAX5123BEEE±1-40°C to +85°C

-40°C to +85°C 16 QSOP
16 QSOP ±2

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX5122 (+5V)

(VDD= +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, output amplifier configured
in unity-gain, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

VDDto AGND, DGND...............................................-0.3V to +6V

AGND to DGND.....................................................-0.3V to +0.3V

Digital Inputs to DGND.............................................-0.3V to +6V

Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V

DD

+ 0.3V)

FB, OUT to AGND ......................................-0.3V to (V

DD

+ 0.3V)

REF, REFADJ to AGND..............................-0.3V to (V

DD

+ 0.3V)

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (T

A

= +70°C)

QSOP (derate 8.00mW/°C above +70°C).....................667mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

VIN= 0 or V

DD

MAX5122A

REFADJ = V

DD

4.5V ≤ VDD≤ 5.5V

MAX5123B

MAX5122B

MAX5122A

MAX5122A

TA= +25°C

CONDITIONS

pF8C

IN

Input Capacitance

µA-1 0.001 1I

IN

Input Leakage Current

mV200V

HYS

Input Hysteresis

V0.8V

IL

Input Low Voltage

V3V

IH

Input High Voltage

µA3.3 7REFADJ Current

ppm/°C

10

TCV

REF

3

Output Voltage Temperature
Coefficient

V2.475 2.5 2.525V

REF

Output Voltage

-0.5 0.5

Bits12NResolution

µV/V20 250PSRRPower-Supply Rejection Ratio

ppm/°C

10 30

TCV

FS

310

Full-Scale Temperature
Coefficient (Note 3)

LSB-1 1DNLDifferential Nonlinearity

mV-10 10V

OS

Offset Error (Note 2)

mV-3 -0.2 3GEGain Error

UNITSMIN TYP MAXSYMBOLPARAMETER

I

SINK

= 2mA

I

SOURCE

= 2mA

V0.13 0.4V

OL

Output Low Voltage

VVDD- 0.5V

OH

Output High Voltage

MAX5123B

LSB

-1 1

INLIntegral Nonlinearity (Note 1)

0 ≤ I

OUT

≤ 100µA (sourcing) µV/µA0.1 1V

OUT/IOUT

Reference External Load Regulation

mA4Reference Short-Circuit Current

STATIC PERFORMANCE

REFERENCE

DIGITAL INPUT

DIGITAL OUTPUTS

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX5122 (+5V) (continued)

(VDD= +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, output amplifier configured
in unity-gain, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

To ±0.5LSB, V

STEP

= 2.5V

CS = VDD, f

SCLK

= 100kHz,

V

SCLK

= 5Vp-p

CONDITIONS

µA320I

SHDN

Power-Supply Current in Shutdown

µA500 600I

DD

Power-Supply Current (Note 5)

V4.5 5.5V

DD

Power-Supply Voltage (Note 5)

nV-sec5Digital Feedthrough

ms2Time Required to Exit Shutdown

µs20Output Settling Time

V0 to V

DD

Output Voltage Swing (Note 4)

UNITSMIN TYP MAXSYMBOLPARAMETER

ELECTRICAL CHARACTERISTICS—MAX5123 (+3V)

(VDD= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, output amplifier connected
in unity-gain, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

MAX5123A

REFADJ = V

DD

2.7V ≤ VDD≤ 3.3V

MAX5123B

MAX5123B

MAX5123A

MAX5123A

TA= +25°C

CONDITIONS

mV200V

HYS

Input Hysteresis

V0.8V

IL

Input Low Voltage

V2.2V

IH

Input High Voltage

µA3.3 7REFADJ Current

mA4Reference Short-Circuit Current

ppm/°C

10

TCV

REF

MAX5123B

3

0 ≤ I

OUT

≤ 100µA (sourcing)

Output Voltage Temperature
Coefficient

V1.237 1.25 1.263V

REF

Output Voltage

-1 1

µV/µA0.1 1

Bits12NResolution

µV/V20 250PSRRPower-Supply Rejection Ratio

ppm/°C

10 30

TCV

FS

LSB

310

V

OUT/IOUT

Full-Scale Temperature
Coefficient (Note 3)

LSB-1 1DNLDifferential Nonlinearity

mV-10 10V

OS

Offset Error (Note 2)

Reference External Load Regulation

mV-5 -0.2 5GEGain Error

UNITSMIN TYP MAXSYMBOLPARAMETER

-2 2

INLIntegral Nonlinearity (Note 1)

V/µs0.6SRVoltage Output Slew Rate

STATIC PERFORMANCE

REFERENCE

DIGITAL INPUT

µA-0.1 0 0.1Current into FB

DYNAMIC PERFORMANCE

POWER REQUIREMENTS

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS—MAX5123 (+3V) (continued)

(VDD= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, output amplifier connected
in unity-gain, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

To ±0.5LSB, V

STEP

= 1.25V

CS = VDD, f

SCLK

= 100kHz,

V

SCLK

= 3Vp-p

CONDITIONS

µA320I

SHDN

Power-Supply Current in Shutdown

µA500 600I

DD

Power-Supply Current (Note 5)

V2.7 3.6V

DD

Power-Supply Voltage (Note 5)

nV-sec5Digital Feedthrough

ms2Time Required to Exit Shutdown

µA-0.1 0 0.1Current into FB

µs20Output Settling Time

V0 to V

DD

Output Voltage Swing (Note 4)

UNITSMIN TYP MAXSYMBOLPARAMETER

I

SINK

= 2mA V0.13 0.4V

OL

Output Low Voltage

I

SOURCE

= 2mA VVDD- 0.5V

OH

Output High Voltage

VIN= 0 or V

DD

µA-1 0.001 1I

IN

Input Leakage Current

pF8C

IN

Input Capacitance

V/µs0.6SRVoltage Output Slew Rate

TIMING CHARACTERISTICS—MAX5122 (+5V)

(VDD= +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, output amplifier connected
in unity-gain, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

ns40t

CSS

CS Fall to SCLK Rise Setup Time

ns40t

CL

SCLK Pulse Width Low

CONDITIONS

ns100t

CP

SCLK Clock Period

ns40t

CH

SCLK Pulse Width High

ns0t

CSH

SCLK Rise to CS Rise Hold Time

ns10t

CS0

SCLK Rise to CS Fall Delay Time

ns40t

DS

SDI Setup Time

ns0t

DH

SDI Hold Time

UNITSMIN TYP MAXSYMBOLPARAMETER

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold Time

C

LOAD

= 200pF ns80t

DO1

SCLK Rise to DOUT Valid
Propagation Delay Time

C

LOAD

= 200pF ns80t

DO2

SCLK Fall to DOUT Valid
Propagation Delay Time

DIGITAL OUTPUTS

POWER REQUIREMENTS

DYNAMIC PERFORMANCE

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

_______________________________________________________________________________________ 5

Note 1: Accuracy is guaranteed by the following table:

Note 2: Offset is measured at the code closest to 10mV.
Note 2: The temperature coefficient is determined by the “box” method, in which the maximum

∆V

OUT

over the temperature range

is divided by ∆T and the typical reference voltage.

Note 4: Accuracy is better than 1.0LSB for V

OUT

= 10mV to (VDD- 180mV). Guaranteed by PSR test on end points.

Note 5: R

LOAD

= ∞and digital inputs are at either VDDor DGND.

TIMING CHARACTERISTICS—MAX5123 (+3V)

(VDD= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, RL= 5kΩ, CL= 100pF, output amplifier connected
in unity-gain, T

A

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

ns60t

CSS

CS Fall to SCLK Rise Setup Time

ns150

ns

C

LOAD

= 200pF

75

t

CSW

t

CL

SCLK Pulse Width Low

CONDITIONS

ns150t

CP

SCLK Clock Period

ns75t

CH

SCLK Pulse Width High

ns0t

CSH

SCLK Rise to CS Rise Hold Time

CS Pulse Width High

ns75t

CS1

CS Rise to SCLK Rise Hold Time

C

LOAD

= 200pF ns200t

DO1

SCLK Rise to DOUT Valid
Propagation Delay Time

ns200t

DO2

SCLK Fall to DOUT Valid
Propagation Delay Time

ns10t

CS0

SCLK Rise to CS Fall Delay Time

ns60t

DS

SDI Setup Time

ns0t

DH

SDI Hold Time

UNITSMIN TYP MAXSYMBOLPARAMETER

165
333

4095
4095

Accuracy Guaranteed

To Code:From Code:

V

DD

(V)

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

6 _______________________________________________________________________________________

Typical Operating Characteristics

(VDD= +5V, RL= 5kΩ, CL= 100pF, output amplifier in unity-gain configuration, TA= +25°C, unless otherwise noted.)

200

250

300

350

400

450

500

-60 -20-40 0 20406080100

MAX5122

SUPPLY CURRENT vs. TEMPERATURE

MAX5122/23 toc04

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

(CODE = AAA HEX)

(CODE = 000 HEX)

250

300

400

350

450

500

4.0 4.5 5.0 5.5 6.0

MAX5122

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX5122/23 toc05

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

(CODE = AAA HEX)

(CODE = 000 HEX)

0

0.25

0.50

1.00

0.75

1.25

1.75

1.50

2.00

-60 -20-40 0 20406080100

MAX5122

SHUTDOWN CURRENT vs. TEMPERATURE

MAX5122/23 toc06

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

2.490

2.495

2.500

2.505

2.510

-60 -20-40 0 20406080100

MAX5122

FULL-SCALE OUTPUT VOLTAGE

vs. TEMPERATURE

MAX5122/23 toc07

TEMPERATURE (°C)

FULL-SCALE OUTPUT (V)

RL = 5kΩ
C

L

= 100pF

0.1 1 10 100

MAX5122

FULL-SCALE OUTPUT ERROR vs. RESISTIVE LOAD

MAX5122/23 toc08

RL (kΩ)

FULL-SCALE OUTPUT ERROR (LSB)

0.25

-2.00

-1.25

-0.50

CS
5V/div

OUT
1V/div

2µs/div

MAX5122

DYNAMIC RESPONSE RISE TIME

MAX5122/23-09

-0.20

-0.15

-0.10

-0.05

0

0.05

0.10

0.15

0.20

0 1,000 2,000 3,000 4,000 5,000

MAX5122

INTEGRAL NONLINEARITY vs.

DIGITAL INPUT CODE

MAX5122/23 toc01

DIGITAL INPUT CODE

INL (LSB)

-0.20

-0.15

-0.10

-0.05

0

0.05

0.10

0.15

0.20

0 1,000 2,000 3,000 4,000 5,000

MAX5122

DIFFERENTIAL NONLINEARITY vs.

DIGITAL INPUT CODE

MAX5122/23 toc02

DIGITAL INPUT CODE

DNL (LSB)

2.490

2.495

2.500

2.505

2.510

-60 -20 20 60-40 0 40 80 100

MAX5122

REFERENCE VOLTAGE vs. TEMPERATURE

MAX5122/23 toc03

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

_______________________________________________________________________________________

7

-0.20

-0.15

-0.10

0

-0.05

0.05

0.10

0.15

0.20

0.25

0 1,000 2,000 3,000 4,000 5,000

MAX5123

INTEGRAL NONLINEARITY vs.

DIGITAL INPUT CODE

MAX5122/23 toc13

DIGITAL INPUT CODE

INL (LSB)

200

250

300

350

400

-60 -20-40 0 20406080100

MAX5123

SUPPLY CURRENT vs. TEMPERATURE

MAX5122/23 toc16

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

(CODE = AAA HEX)

(CODE = 000 HEX)

-0.25

-0.20

-0.15

-0.10

-0.05

0

0.05

0.10

0.15

0 1,000 2,000 3,000 4,000 5,000

MAX5123

DIFFERENTIAL NONLINEARITY vs.

DIGITAL INPUT CODE

MAX5122/23 toc14

DIGITAL INPUT CODE

DNL (LSB)

1.240

1.245

1.250

1.255

1.260

-60 -20 20 60-40 0 40 80 100

MAX5123

REFERENCE VOLTAGE vs. TEMPERATURE

MAX5122/23 toc15

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

200

300

250

350

400

2.50 2.75 3.00 3.25 3.50

MAX5123

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX5122/23 toc17

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

(CODE = AAA HEX)

(CODE = 000 HEX)

0.1

0.2

0.3

0.4

0.5

-60 -20-40 0 20406080100

MAX5123

SHUTDOWN CURRENT vs. TEMPERATURE

MAX5122/23 toc18

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

CS
5V/div

OUT
1V/div

2µV/div

MAX5122

DYNAMIC RESPONSE FALL TIME

MAX5122/23-10

SCLK
2V/div

OUT
1mV/div
AC COUPLED

2µs/div

MAX5122

DIGITAL FEEDTHROUGH (SCLK, OUT)

MAX5122/23-11

CS
2V/div

OUT
100mV/div
AC COUPLED

5µs/div

MAX5122

MAJOR CARRY TRANSITION

MAX5122/23-12

Typical Operating Characteristics (continued)

(VDD= +5V, RL= 5kΩ, CL= 100pF, output amplifier in unity-gain configuration, TA= +25°C, unless otherwise noted.)

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

8 _______________________________________________________________________________________

1.240

1.245

1.250

1.255

1.260

-60 -20-40 0 20406080100

MAX5123

FULL-SCALE OUTPUT VOLTAGE

vs. TEMPERATURE

MAX5122/23 toc19

TEMPERATURE (°C)

FULL-SCALE OUTPUT (V)

0.01 10.1 10 100

MAX5123

FULL-SCALE OUTPUT ERROR

vs. RESISTIVE LOAD

MAX5122/23 toc20

RL (kΩ)

FULL-SCALE OUTPUT ERROR (LSB)

-4

-3

-2

-1

0

CS
2V/div

OUT
400mV/div

1µs/div

MAX5123

DYNAMIC-RESPONSE RISE TIME

MAX5122/23-21

CS
2V/div

OUT
400mV/div

1µs/div

MAX5123

DYNAMIC-RESPONSE FALL TIME

MAX5122/23-22

SCLK
2V/div

OUT
500µV/div
AC COUPLED

2µs/div

MAX5123

DIGITAL FEEDTHROUGH (SCLK, OUT)

MAX5122/23-23

CS
2V/div

OUT
100mV/div
AC COUPLED

5µV/div

MAX5123

MAJOR CARRY TRANSITION

MAX5122/23-24

Typical Operating Characteristics (continued)

(VDD= +5V, RL= 5kΩ, CL= 100pF, output amplifier in unity-gain configuration, TA= +25°C, unless otherwise noted.)

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

_______________________________________________________________________________________ 9

Analog Output Voltage. High impedance if part is in shutdown.OUT2

Power-Down Lockout (Digital Input).
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).

PDL

4

Reset Value Input (Digital Input).
1: Connect to VDDto select midscale as the output reset value.
0: Connect to DGND to select 0V as the output reset value.

RSTVAL3

Active-Low Chip-Select Input (Digital Input)

CS

6

Serial Clock InputSCLK8

Serial Data Input. Data is clocked in on the rising edge of SCLK.DIN7

Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.

CLR

5

Serial Data OutputDOUT10

Power-Down Input (Digital Input). Pulling PD high when PDL = VDDplaces the IC into shutdown with a maxi­mum shutdown current of 20µA.

PD12

User-Programmable Output (Digital Output)UPO11

Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5122) or +1.25V (MAX5123) nominal output, externally adjustable at REFADJ. In external reference
mode, disable the internal reference by pulling REFADJ to VDDand applying the external reference to REF.

REF14

PIN

Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.V

DD

16

Amplifier Inverting Sense Input (Analog Input)FB1

FUNCTIONNAME

Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDDwhen using an
external reference.

REFADJ15

Analog GroundAGND13

Digital GroundDGND9

Pin Description

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

10 ______________________________________________________________________________________

_______________Detailed Description

The MAX5122/MAX5123 12-bit, force/sense DACs are
easily configured with a 3-wire serial interface. They
include a 16-bit data-in/data-out shift register and have
a double-buffered digital input consisting of an input
register and a DAC register. In addition, these devices
employ precision bandgap references, as well as an
output amplifier with accessible feedback and output
pins that can be used to set the gain externally (Figure

1) or for forcing and sensing applications. These DACs
are designed with an inverted R-2R ladder network
(Figure 2) that produces a weighted voltage proportion­al to the digital input code.

Internal Reference

Both devices use an on-board precision bandgap ref­erence with a low temperature coefficient of only
10ppm/°C (max) to generate an output voltage of +2.5V
(MAX5122) or +1.25V (MAX5123). The REF pin can
source up to 100µA and may become unstable with
capacitive loads exceeding 100pF. REFADJ can be
used for minor adjustments to the reference voltage.

MAX5122
MAX5123

SR

CONTROL

16-BIT

SHIFT REGISTER

DECODE

CONTROL

INPUT

REGISTER

BANDGAP

REFERENCE

REFERENCE

BUFFER

DAC

REGISTER

DAC

2X

(X1)

DOUT
UPO

FB

OUT

4k

1.25V

12

AGND DGNDV

DD

DIN

SCLKCS

2.5V (1.25V)

LOGIC

OUTPUT

CLR

RSTVAL

PDL

PD

REFADJ REF

( ) ARE FOR MAX5123 ONLY.

Figure 1. Simplified Functional Diagram

OUT

FB

NOTE: SHOWN FOR ALL 1s ON DAC.

D0 D9 D10

D11

*INTERNAL REFERENCE: +2.5V (MAX5122),
+1.25V (MAX5123); OR EXTERNAL REFERENCE

2R

2R 2R 2R 2R

RRR

REF*

AGND

Figure 2. Simplified Inverted R-2R DAC Structure

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

______________________________________________________________________________________ 11

The circuit in Figure 3 achieves a nominal reference
adjustment range of ±1%. Connect a 33nF capacitor
from REFADJ to AGND to establish low-noise DAC
operation. Larger capacitor values may be used, but
will result in increased start-up delay. The time constant
(τ) for the start-up delay is determined by the REFADJ
input impedance of 4kΩ and C

REFADJ

:

τ= 4kΩ · C

REFADJ

External Reference

An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
VDD. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper oper­ation, do not exceed the input voltage range limits of 0
to (VDD- 1.4V) for V

REF

.

Determine the output voltage using the following equa­tion (REFADJ = VDD):

V

OUT

= V

REF

[(NB / 4096) G]

where NB is the numeric value of the MAX5122/
MAX5123 input code (0 to 4095), V

REF

is the external
reference voltage, and G is the gain of the output
amplifier, set by an external resistor-divider. The REF
pin has a minimum input resistance of 40kΩ and is
code-dependent.

Output Amplifier

The MAX5122/MAX5123’s DAC output is internally
buffered by a precision amplifier with a typical slew rate
of 0.6V/µs. Access to the output amplifier’s inverting
input (FB) provides the user greater flexibility with
amplifier gain setting and signal conditioning (see

Applications Information

).

The output amplifier typically settles to ±0.5LSB from a
full-scale transition within 20µs when it is connected in
unity gain and loaded with 5kΩ100pF. Loads less
than 1kΩ may result in degraded performance.

Power-Down Mode

These devices feature software- and hardware-pro­grammable (PD pin) shutdown modes that reduce the
typical supply current to 3µA. To enter software shut­down mode, program the control sequence for the DAC
as shown in Table 1.

In shutdown mode, the amplifier output becomes high­impedance and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5122/MAX5123 to recall the output state prior to
entering shutdown when returning to normal operation.
To exit shutdown mode, load both input and DAC regis­ters simultaneously or update the DAC register from the
input register. When returning from shutdown to normal
operation, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.

REFADJ

+3V

15k

100k

400k

33nF

MAX5123

Figure 3a. MAX5122 Reference Adjust Circuit Figure 3b. MAX5123 Reference Adjust Circuit

+5V

90k

100k

400k

33nF

MAX5122

REFADJ

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

12 ______________________________________________________________________________________

Power-Down Lockout Input (PDL)

The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low tran­sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.

Power-Down Input (PD)

Pulling PD high places the MAX5122/MAX5123 in shut­down. Pulling PD low will not return the MAX5122/
MAX5123 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the ser-
ial interface are required to exit power-down mode.

Serial-Interface Configuration

(SPI/QSPI/MICROWIRE/PIC16/PIC17)

The MAX5122/MAX5123 3-wire serial interface is com­patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2­byte-long serial input word contains three control bits,
12 data bits in MSB-first format, and one sub-bit, which
is always zero (Table 2).

The MAX5122/MAX5123’s digital inputs are double
buffered, which allows the user to:

• Load the input register without updating the DAC
register,

• Update the DAC register with data from the input
register,

• Update the input and DAC registers concurrently.

Load input register; DAC register unchanged.12-Bit DAC Data0 0

0

1

0

Update DAC register from input register; exit shutdown.XXXXXXXXXXXX0 1

1

1

0 Simultaneously load input and DAC registers; exit shutdown.12-Bit DAC Data0

UPO goes low (default).XXXXXXXXXXXX1 0

0

0

1

Mode 1; DOUT clocked out on SCLK’s rising edge.1XXXXXXXXXXX1 1

1

1

0 UPO goes high.XXXXXXXXXXXX1

No operation.XXXXXXXXXXXX0

Shutdown DAC (provided PDL = 1).

XXXXXXXXXXXX1

Mode 0; DOUT clocked out on SCLK’s falling edge (default).00XXXXXXXXXX1 1 1

C1 C0C2

FUNCTION

D11 ............... D0

Table 1. Serial-Interface Programming Commands

X = Don’t care* S0 is a sub-bit and always zero.

DIN

SCLK

CS

MOSI

SCK

I/O

SPI/QSPI

PORT

(PIC16/PIC17)

SS

V

DD

CPOL = 0, CPHA = 0
(CKE = 1, CKP = 0, SMP= 0
SSPM3 - SSPM0 = 0001)

( ) ARE FOR PIC16/PIC17 ONLY.

MAX5122
MAX5123

Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)

DIN

SCLK

CS

SK

SO

I/O

MICROWIRE

PORT

MAX5122
MAX5123

Figure 5. MICROWIRE Interface Connections

16-BIT SERIAL WORD

0

S0*

0

0

0

0

0

0

0

0

S0*

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

______________________________________________________________________________________ 13

The 16-bit input word may be sent in two 1-byte pack­ets (SPI-, MICROWIRE-, and PIC16/PIC17-compatible),
with CS low during this period. The control bits C2, C1,
and C0 (table 1) determine:

• The clock edge on which DOUT transitions,

• The state of the user-programmable logic output,

• The configuration of the device after shutdown.

The general timing diagram in Figure 6 illustrates how
data is acquired. CS must be low for the part to receive
data. With CS low, data at DIN is clocked into the regis­ter on the rising edge of SCLK. When CS transitions
high, data is latched into the input and/or DAC regis­ters, depending on the setting of the three control bits
C2, C1, and C0. The maximum serial clock frequency
guaranteed for proper operation is 10MHz for the

MAX5122 and 6.6MHz for the MAX5123. Figure 7
depicts a more detailed timing diagram of the serial
interface.

PIC16 with SSP Module

and PIC17 Interface

The MAX5122/MAX5123 are compatible with a
PIC16/PIC17 microcontroller (µC), using the synchro­nous serial port (SSP) module. To establish SPI commu­nication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by ini­tializing its synchronous serial port control register (SSP­CON) and synchronous serial port status register
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.

In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit writings (Figure

6) are necessary to feed the DAC with three control bits,
12 data bits, and one sub-bit. DIN data transitions on
the serial clock’s falling edge and is clocked into the
DAC on SCLK’s rising edge. The first eight bits of DIN
contain the three control bits (C2, C1, C0) and the first
five data bits (D11–D7). The second 8-bit data stream
contains the remaining bits (D6–D0), and the sub-bit S0.

Control Bits

MSB ............................................................................... LSB

D11................................D0C2, C1, C0

Figure 6. Serial-Interface Timing

SCLK

DIN

DOUT

t

CS0

t

CSS

t

CL

t

CH

t

CP

t

CSW

t

CS1

t

CSH

t

DS t

DO1

t

DO2

t

DH

CS

Figure 7. Detailed Serial-Interface Timing

Table 2. Serial Data Format

⇐ 16 BITS OF SERIAL DATA ⇒

Sub-Bit

S0

MSB ..... Data Bits ..... LSB

CS

SCLK

DIN

1

C2 S0

COMMAND

EXECUTED

8

C1

C0

D11

D10

D9

D8 D5 D4 D3 D2 D1 D0D7 D6

9

16

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

14 ______________________________________________________________________________________

Serial Data Output

The contents of the internal shift-register are output
serially on DOUT which allows for daisy-chaining of
multiple devices (see

Applications Information

) as well
as data readback. The MAX5122/MAX5123 may be
programmed to shift data out of DOUT on the serial
clock’s rising edge (Mode 1) or on the falling edge
(Mode 0). The latter is the default during power-up and
provides a lag of 16 clock cycles, maintaining SPI,
QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In
Mode 1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.

User-Programmable Output (UPO)

The UPO feature allows an external device to be con­trolled through the serial-interface setup (Table 1) there­by reducing the number of microcontroller I/O ports
required. During power-down, this output will retain the
last digital state before shutdown. With CLR pulled low,
UPO will reset to the default state after wake-up.

Table 3. Detailed SSPCON Register Contents

Receive Overflow Detect BitXSSPOV BIT6

BIT7

Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.0CKP BIT4

BIT5

Synchronous Serial Port Enable Bit.
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as serial­port pins.

1SSPEN

0SSPM2 BIT2

BIT3

1SSPM0 BIT0

BIT1

CONTROL BIT

0SSPM1

Write Collision Detection BitXWCOL

SYNCHRONOUS SERIAL-PORT CONTROL REGISTER

(SSPCON)

MAX5122/MAX5123

SETTINGS

Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects f

CLK

= f

OSC

/ 16

0SSPM3

X = Don’t care

Table 4. Detailed SSPSTAT Register Contents

X = Don’t care

SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.

1CKE BIT6

Buffer Full Status Bit

BIT7

Update Address

Read/Write Bit Information

Stop BitXP BIT4

BIT5 Data Address BitXD/A

XR/W BIT2

BIT3

XBF BIT0

BIT1

CONTROL BIT

XUA

SPI Data Input Sample Phase. Input data is sampled at the mid­dle of the data output time.

0SMP

SYNCHRONOUS SERIAL-PORT CONTROL REGISTER

(SSPSTAT)

MAX5130/MAX5131

SETTINGS

Start BitXS

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

______________________________________________________________________________________ 15

__________Applications Information

Definitions

Integral Nonlinearity (INL)

Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli­fied. For a DAC, the deviations are measured at every
single step.

Differential Nonlinearity (DNL)

Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of

1LSB. If the magnitude of the DNL is less than or equal
to 1LSB, the DAC guarantees no missing codes and is
monotonic.

Offset Error

The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off­set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.

Gain Error

Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre­sponds to the same percentage error in each step.

0

2

1

4

3

7
6

5

000 010001 011 100 101 110

AT STEP
O11 (1/2 LSB )

AT STEP
001 (1/4 LSB )

111

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

Figure 8a. Integral Nonlinearity

Figure 8b. Differential Nonlinearity

0

2

1

4

3

6

5

000 010001 011 100 101

DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)

DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)

1 LSB

1 LSB

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

Figure 8c. Offset Error

Figure 8d. Gain Error

0

5

4

6

7

000 101100 110 111

IDEAL DIAGRAM

GAIN ERROR

(-1 1/4 LSB)

IDEAL FULL-SCALE OUTPUT

ACTUAL

FULL-SCALE

OUTPUT

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

3

2

1

ANALOG OUTPUT VALUE (LSB)

ACTUAL

OFFSET POINT

0

000 010001 011

ACTUAL

DIAGRAM

IDEAL DIAGRAM

OFFSET ERROR
(+1 1/4 LSB)

IDEAL OFFSET
POINT

DIGITAL INPUT CODE

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

16 ______________________________________________________________________________________

Settling Time

The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value within the converter’s specified accu­racy.

Digital Feedthrough

Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.

Unipolar Output

Figure 9 shows the MAX5122/MAX5123 setup for unipo­lar, Rail-to-Rail®operation with a closed- loop gain of
2V/V. With its internal reference of +2.5V, the MAX5122
provides a convenient unipolar output range of 0 to
+4.99878V, while the MAX5123 offers an output range of
0 to +2.49939V with its on-board +1.25V reference.
Table 5 lists example codes for unipolar output voltages.

Bipolar Output

The MAX5122/MAX5123 can be configured for unity­gain bipolar operation (FB = OUT) using the circuit
shown in Figure 10. The output voltage V

OUT

is then

given by the following equation:

V

OUT

= V

REF

[{G (NB / 4096)} - 1]

where NB is the numeric value of the DAC’s binary
input code, V

REF

is the voltage of the internal (or exter­nal) precision reference, and G is the overall gain. The
application circuit in Figure 10 uses a low-cost op amp
(MAX4162) external to the MAX5122/MAX5123.
Together with the MAX5122/MAX5123 this circuit offers
an overall gain of +2V/V. Table 6 lists example codes
for bipolar output voltages.

Reset (RSTVAL) and

Clear (

CCLLRR

) Functions

The MAX5122/MAX5123 DACs feature a clear pin (CLR),
which resets the output to a certain value, depending
upon how RSTVAL is set. RSTVAL = DGND selects an
output of 0, and RSTVAL = VDDselects a midscale out­put when CLR is pulled low.

The CLR pin has a minimum input resistance of 40kΩ in
series with a diode to the supply voltage (VDD). If the
digital voltage is higher than the supply voltage for the
part, a small input current may flow, but this current will
be limited to (V

CLR

- VDD- 0.5V) / 40kΩ.

Note: Clearing the DAC will also cause the part to exit
a software shutdown (PD = 0).

Daisy-Chaining Devices

Any number of MAX5122/MAX5123s may be daisy­chained by simply connecting the serial data output pin
(DOUT) of one device to the serial data input pin (DIN)
of the following device in the chain (Figure 11).

Another configuration (Figure 12) allows several
MAX5122/MAX5123 DACs to share one common DIN
signal line. In this configuration, the data bus is common
to all devices; data is not shifted through a daisy-chain.
However, more I/O lines are required in this configura­tion, because each IC needs a dedicated CS line.

MAX5122
MAX5123

DAC

NOTE: GAIN = +2V/V

REF

OUT

DGNDAGND

+5V/+3V

V

DD

FB

50k

50k

Figure 9. Unipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to V

DD

.

MAX5122
MAX5123

MAX4162

DAC

AGND

DGND

REF

V

OUT

FB

+5V/+3V 50k 50k

V+

V-

V

DD

OUT

Figure 10. Unity-Gain Bipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to V

DD

.

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

______________________________________________________________________________________ 17

V

REF

(2049 / 4096) 21000 0000 0001 0

0

V

REF

(2047 / 4096) 20111 1111 1111 0

0 V

REF

(2048 / 4096) 21000 0000 0000

00000 0000 0000 0

0

V

REF

(4095 / 4096) 21111 1111 1111

V

REF

(1 / 4096) 20000 0000 0001

DAC CONTENTS

SUB-BIT

S0

EXTERNAL REFERENCE

MAX5122/MAX5123

V

REF

[ {2 (2049 / 4096)} - 1]1000 0000 0001 0

0

+610.35µV

+1.24939V

DAC CONTENTS

V

REF

[ {2 (2047 / 4096)} - 1]0111 1111 1111 0

0

-610.35µV

0V V

REF

[ {2 (2048 / 4096)} - 1]1000 0000 0000

-V

REF

0000 0000 0000 0

0

-1.25V

-1.24939V

V

REF

[ {2 (4095 / 4096)} - 1]1111 1111 1111

V

REF

[ {2 (1 / 4096)} - 1]0000 0000 0001

Table 5. Unipolar Code Table (Gain = +1.6384V/V)

Table 6. Bipolar Code Table (Figure 10)

+2.50122V

+4.99878V

+1.25061V

+2.49939V

+2.49878V

+2.5V

+1.24939V

+1.25V

MAX5122 MAX5123

0V

+1.2207mV

0V

+610.35µV

INTERNAL REFERENCE

MSB LSB

ANALOG OUTPUT

ANALOG OUTPUT

+1.2207mV

+2.49878V

-1.2207mV

0V

-2.5V

-2.49878V

Figure 11. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT

INTERNAL REFERENCE

SUB-BIT

S0

MAX5123

EXTERNAL REFERENCE

MAX5122/MAX5123

MAX5122

MSB LSB

SCLK

I II III

MAX5122
MAX5123

DIN

CS

SCLK

MAX5122
MAX5123

DINDOUT DOUT DOUT

CS

SCLK

DIN

CS

MAX5122
MAX5123

TO OTHER
SERIAL DEVICES

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

18 ______________________________________________________________________________________

Using an External Reference

with AC Components

The MAX5122/MAX5123 have multiplying capabilities
within the reference input voltage range specifications.
Figure 13 shows a technique for applying a sinusoidal
input to REF, where the AC signal is offset before being
applied to the reference input.

Power-Supply and Bypassing

Considerations

On power-up, the input and DAC registers are cleared to
either zero (RSTVAL = DGND) or midscale (RSTVAL =

V

DD

). Bypass the power supply (VDD) with a 4.7µF
capacitor in parallel with a 0.1µF capacitor to AGND.
Minimize lead lengths to reduce lead inductance.

Layout Considerations

Digital and AC signals coupling to AGND can create
noise at the output. Connect AGND to the highest quali­ty ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are
not recommended. If noise becomes an issue, shield­ing may be required.

TO OTHER
SERIAL DEVICES

MAX5122
MAX5123

DIN

SCLK

CS

MAX5122
MAX5123

DIN

SCLK

CS

MAX5122

MAX5123

DIN

I II III

SCLK

CS

DIN

SCLK

CS1
CS2

CS3

Figure 12. Multiple Devices Share One Common Digital Input (DIN)

DAC

OUT

MAX5122
MAX5123

10k

26k

REF

FB

V

DD

DGNDAGND

+5V/

+3V

AC

REFERENCE

INPUT

500mVp-p

MAX495

+5V/+3V

___________________Chip Information

TRANSISTOR COUNT: 3308
SUBSTRATE CONNECTED TO AGND

Figure 13. External Reference with AC Components

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs

with 10ppm/°C Internal Reference

______________________________________________________________________________________ 19

Package Information

QSOP.EPS

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

MAX5122/MAX5123

+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference

NOTES