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General Description
The MAX5062/MAX5063/MAX5064 high-frequency,
125V half-bridge, n-channel MOSFET drivers drive highand low-side MOSFETs in high-voltage applications.
These drivers are independently controlled and their
35ns typical propagation delay, from input to output, are
matched to within 3ns (typ). The high-voltage operation
with very low and matched propagation delay between
drivers, and high source/sink current capabilities in a
thermally enhanced package make these devices suitable for the high-power, high-frequency telecom power
converters. The 125V maximum input voltage range provides plenty of margin over the 100V input transient
requirement of telecom standards. A reliable on-chip
bootstrap diode connected between V
DD
and BST elimi-
nates the need for an external discrete diode.
The MAX5062A/C and the MAX5063A/C offer both noninverting drivers (see the Selector Guide). The
MAX5062B/D and the MAX5063B/D offer a noninverting
high-side driver and an inverting low-side driver. The
MAX5064A/B offer two inputs per driver that can be
either inverting or noninverting. The MAX5062A/B/C/D
and the MAX5064A feature CMOS (V
DD
/ 2) logic inputs.
The MAX5063A/B/C/D and the MAX5064B feature TTL
logic inputs. The MAX5064A/B include a break-beforemake adjustment input that sets the dead time between
drivers from 16ns to 95ns. The drivers are available in the
industry-standard 8-pin SO footprint and pin configuration, and a thermally enhanced 8-pin SO and 12-pin
(4mm x 4mm) thin QFN packages. All devices operate
over the -40°C to +125°C automotive temperature range.
Applications
Telecom Half-Bridge Power Supplies
Two-Switch Forward Converters
Full-Bridge Converters
Active-Clamp Forward Converters
Power-Supply Modules
Motor Control
Features
♦ HIP2100/HIP2101 Pin Compatible (MAX5062A/
MAX5063A)
♦ Up to 125V Input Operation
♦ 8V to 12.6V V
DD
Input Voltage Range
♦ 2A Peak Source and Sink Current Drive Capability
♦ 35ns Typical Propagation Delay
♦ Guaranteed 8ns Propagation Delay Matching
Between Drivers
♦ Programmable Break-Before-Make Timing
(MAX5064)
♦ Up to 1MHz Combined Switching Frequency while
Driving 100nC Gate Charge (MAX5064)
♦ Available in CMOS (V
DD
/ 2) or TTL Logic-Level
Inputs with Hysteresis
♦ Up to 15V Logic Inputs Independent of Input
Voltage
♦ Low 2.5pF Input Capacitance
♦ Instant Turn-Off of Drivers During Fault or PWM
Start-Stop Synchronization (MAX5064)
♦ Low 200µA Supply Current
♦ Versions Available With Combination of
Noninverting and Inverting Drivers (MAX5062B/D
and MAX5063B/D)
♦ Available in 8-Pin SO, Thermally Enhanced SO,
and 12-Pin Thin QFN Packages
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
PART HIGH-SIDE DRIVER LOW-SIDE DRIVER LOGIC LEVELS PIN COMPATIBLE
MAX5062AASA Noninverting Noninverting CMOS (V
DD
/ 2) HIP 2100IB
MAX5062BASA Noninverting Inverting CMOS (V
DD
/ 2) —
MAX5062CASA Noninverting Noninverting CMOS (V
DD
/ 2) —
MAX5062DASA Noninverting Inverting CMOS (V
DD
/ 2) —
Selector Guide
19-3502; Rev 5; 5/07
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Selector Guide continued at end of data sheet.
*EP = Exposed paddle.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
Ordering Information continued at end of data sheet.
PART TEMP RANGE
MAX5062AASA -40°C to +125°C 8 SO — S8-5
MAX5062BASA -40°C to +125°C 8 SO — S8-5
MAX5062CASA -40°C to +125°C 8 SO-EP* — S8E-14
MAX5062DASA -40°C to +125°C 8 SO-EP* — S8E-14
PINPACKAGE
TOP
MARK
PKG
CODE
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= V
BST
= +8V to +12.6V, VHS= GND = 0V, BBM = open, TA= -40°C to +125°C, unless otherwise noted. Typical values are at
V
DD
= V
BST
= +12V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
V
DD
, IN_H, IN_L, IN_L+, IN_L-, IN_H+, IN_H-........-0.3V to +15V
DL, BBM .....................................................-0.3V to (V
DD
+ 0.3V)
HS............................................................................-5V to +130V
DH to HS.....................................................-0.3V to (V
DD
+ 0.3V)
BST to HS ...............................................................-0.3V to +15V
AGND to PGND (MAX5064) ..................................-0.3V to +0.3V
dV/dt at HS ........................................................................50V/ns
Continuous Power Dissipation (T
A
= +70°C)
8-Pin SO (derate 5.9mW/°C above +70°C)...............470.6mW
8-Pin SO with Exposed Pad (derate 19.2mW/°C
above +70°C)* ....................................................1538.5mW
12-Pin Thin QFN (derate 24.4mW/°C
above +70°C)* ....................................................1951.2mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*Per JEDEC 51 standard multilayer board.
PARAMETER
CONDITIONS
UNITS
POWER SUPPLIES
Operating Supply Voltage V
DD
(Note 2) 8.0
V
MAX5062_/
MAX5063_
70
VDD Quiescent Supply Current I
DD
IN_H = IN_L = GND
(no switching)
MAX5064_
µA
VDD Operating Supply Current I
DDO
fSW = 500kHz, VDD = +12V 3 mA
BST Quiescent Supply Current I
BST
IN_H = IN_L = GND (no switching) 15 40 µA
BST Operating Supply Current I
BSTOfSW
= 500kHz, VDD = V
BST
= +12V 3 mA
UVLO (VDD to GND)
VDD rising 6.5 7.3 8.0 V
UVLO (BST to HS)
BST rising 6.0 6.9 7.8 V
UVLO Hysteresis 0.5 V
LOGIC INPUT
MAX5062_/MAX5064A,
CMOS (V
DD
/ 2) version
0.67 x
0.55 x
Input-Logic High V
IH_
MAX5063_/MAX5064B, TTL version 2
V
MAX5062_/MAX5064A,
CMOS (V
DD
/ 2) version
0.4 x
0.33 x
Input-Logic Low V
IL_
MAX5063_/MAX5064B, TTL version 1.4 0.8
V
MAX5062_/MAX5064A,
CMOS (V
DD
/ 2) version
1.6
Logic-Input Hysteresis V
HYS
MAX5063_/MAX5064B, TTL version
V
SYMBOL
MIN TYP MAX
12.6
120 260
UVLO
VDD
UVLO
BST
V
DD
V
DD
1.65
V
DD
0.25
140
V
DD
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= V
BST
= +8V to +12.6V, VHS= GND = 0V, BBM = open, TA= -40°C to +125°C, unless otherwise noted. Typical values are at
V
DD
= V
BST
= +12V and TA= +25°C.) (Note 1)
PARAMETER
CONDITIONS
UNITS
V
IN_H+
, V
IN_L+
= 0V
V
IN_H-
, V
IN_L-
, V
IN_H
= V
DD
Logic-Input Current I_IN
-1
+1 µA
IN_H+, IN_L+ IN_H, to GND
IN_L to V
DD
for MAX5062B/D,
MAX5063B/D
IN_H-, IN_L-, IN_H, to V
DD
Input Resistance R
IN
1MΩ
Input Capacitance C
IN
2.5 pF
HIGH-SIDE GATE DRIVER
HS Maximum Voltage
V
BST Maximum Voltage
V
TA = +25°C 2.5 3.3
Driver Output Resistance
(Sourcing)
VDD = 12V, IDH = 100mA
(sourcing)
T
A
= +125°C 3.5 4.6
Ω
TA = +25°C 2.1 2.8
Driver Output Resistance
(Sinking)
VDD = 12V, IDH = 100mA
(sinking)
T
A
= +125°C 3.2 4.2
Ω
DH Reverse Current (Latchup
Protection)
(Note 3)
mA
Power-Off Pulldown Clamp
Voltage
V
Peak Output Current (Sourcing) CL = 10nF, VDH = 0V 2 A
Peak Output Current (Sinking)
CL = 10nF, VDH = 12V 2 A
LOW-SIDE GATE DRIVER
TA = +25°C 2.5 3.3
Driver Output Resistance
(Sourcing)
VDD = 12V, IDL = 100mA
(sourcing)
T
A
= +125°C 3.5 4.6
Ω
TA = +25°C 2.1 2.8
Driver Output Resistance
(Sinking)
VDD = 12V, IDL = 100mA
(sinking)
T
A
= +125°C 3.2 4.2
Ω
Reverse Current at DL (Latchup
Protection)
(Note 3)
mA
Power-Off Pulldown Clamp
Voltage
V
DD
= 0V or floating, IDL = 1mA (sinking)
V
Peak Output Current (Sourcing) I
PK_LP
CL = 10nF, VDL = 0V 2 A
Peak Output Current (Sinking) I
PK_LN
CL = 10nF, VDL = 12V 2 A
INTERNAL BOOTSTRAP DIODE
Forward Voltage Drop V
f
I
BST
= 100mA
V
Turn-On and Turn-Off Time t
R
I
BST
= 100mA 40 ns
SYMBOL
V
= VDD for MAX5062B/D, MAX5063B/D
IN_L
V
= 0V for MAX5062A/C, MAX5063A/C
IN_L
MIN TYP MAX
0.001
V
HS_MAX
V
BST_MAX
R
ON_HP
R
ON_HN
I
DH_PEAK
R
ON_LP
R
ON_LN
IN_L for MAX5062A/C, MAX5063A/C to GND
V
= 0V or floating, IDH = 1mA (sinking) 0.94 1.16
BST
125
140
400
400
0.95 1.16
0.91 1.11
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
4 _______________________________________________________________________________________
Note 1: All devices are 100% tested at TA= +125°C. Limits over temperature are guaranteed by design.
Note 2: Ensure that the V
DD
-to-GND or BST-to-HS voltage does not exceed 13.2V.
Note 3: Guaranteed by design, not production tested.
Note 4: Break-before-make time is calculated by t
BBM
= 8ns x (1 + R
BBM
/ 10kΩ).
Note 5: See the Minimum Pulse Width section.
ELECTRICAL CHARACTERISTICS (continued)
(VDD= V
BST
= +8V to +12.6V, VHS= GND = 0V, BBM = open, TA= -40°C to +125°C, unless otherwise noted. Typical values are at
V
DD
= V
BST
= +12V and TA= +25°C.) (Note 1)
PARAMETER
CONDITIONS
UNITS
SWITCHING CHARACTERISTICS FOR HIGH- AND LOW-SIDE DRIVERS (VDD = V
BST
= +12V)
CL = 1000pF 7
CL = 5000pF 33Rise Time t
R
CL = 10,000pF 65
ns
CL = 1000pF 7
CL = 5000pF 33
Fall Time t
F
CL = 10,000pF 65
ns
CMOS 30 55
Turn-On Propagation Delay Time
t
D_ON
Figure 1, CL = 1000pF
(Note 3)
TTL 35 63
ns
CMOS 30 55
Turn-Off Propagation Delay Time
t
D_OFF
Figure 1, CL = 1000pF
(Note 3)
TTL 35 63
ns
Delay Matching Between
Inverting Input to Output and
Noninverting Input to Output
CL = 1000pF, BBM open for MAX5064,
Figure 1 (Note 3)
28ns
Delay Matching Between DriverLow and Driver-High
CL = 1000pF, BBM open for MAX5064,
Figure 1 (Note 3)
28ns
R
BBM
= 10kΩ 16
R
BBM
= 47kΩ (Notes 3, 4) 40 56 72
Break-Before-Make Accuracy
(MAX5064 Only)
R
BBM
= 100kΩ 95
ns
Internal Nonoverlap 1ns
VDD = V
BST
= 12V
Minimum Pulse-Width Input Logic
(High or Low) (Note 5)
VDD = V
BST
= 8V
ns
SYMBOL
t
MATCH1
MIN TYP MAX
t
MATCH2
t
PW-MIN
135
170
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(Typical values are at VDD= V
BST
= +12V and TA= +25°C, unless otherwise specified.)
UNDERVOLTAGE LOCKOUT
AND V
(V
DD
7.5
7.4
7.3
7.2
7.1
7.0
UVLO (V)
6.9
6.8
6.7
6.6
6.5
-40 125
RISING) vs. TEMPERATURE
BST
UVLO
VDD
UVLO
BST
TEMPERATURE (°C)
I
DDO
3.0
2.8
2.6
2.4
2.2
2.0
1.8
(mA)
1.6
BSTO
I
1.4
+
1.2
DDO
I
1.0
0.8
0.6
0.4
0.2
0
013
VDD QUIESCENT CURRENT
vs. V
160
MAX5064
140
120
100
(μA)
DD
I
TA = +25°C, TA = 0°C
80
60
40
20
0
0426810153 7 9 1112131415
MAX5062/3/4 toc01
1109565 80-10 5 20 35 50-25
+ I
vs. V
BSTO
(fSW = 250kHz)
VDD (V)
(NO SWITCHING)
DD
TA = -40°C
VDD (V)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
UVLO HYSTERESIS (V)
0.3
0.2
0.1
DD
TA = +125°C
VDD AND BST UNDERVOLTAGE LOCKOUT
HYSTERESIS vs. TEMPERATURE
UVLO
VDD
HYSTERESIS
UVLO
BST
HYSTERESIS
0
-40 125
TEMPERATURE (°C)
MAX5062/3/4 toc04
1210 11345678912
MAX5062/3/4 toc06
1109565 80-10 5 20 35 50-25
200
180
160
140
120
(mA)
100
DIODE
I
80
60
40
20
0
0.5 0.70.6 0.8 0.9 1.0 1.1
21
V
NO SWITCHING
18
15
12
(μA)
BST
I
9
6
3
0
0426810153 7 9 1112131415
MAX5062/3/4 toc02
2V/div
0V
500μA/div
0A
INTERNAL BST DIODE
(I-V) CHARACTERISTICS
TA = +125°C
TA = +25°C
TA = 0°C
TA = -40°C
VDD - V
BST
BST QUIESCENT CURRENT
vs. BST VOLTAGE
= VDD + 1V,
BST
TA = +125°C
TA = -40°C, TA = 0°C, TA = +25°C
V
(V)
BST
IDD vs. V
MAX5064
IN_L-, IN_H- = V
IN_L+, IN_H+ = GND
(V)
DD
40μs/div
MAX5062/3/4 toc05
MAX5062/3/4 toc07
DD
MAX5062/3/4 toc03
V
DD
I
DD
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Typical values are at VDD= V
BST
= +12V and TA= +25°C, unless otherwise specified.)
10
9
8
7
(mA)
6
BSTO
5
+ I
4
DDO
I
3
2
1
0
VDD AND BST OPERATING SUPPLY
CURRENT vs. FREQUENCY
CL = 0
MAX5062/3/4 toc08
0 1000
FREQUENCY (kHz)
900700 800200 300 400 500 600100
DH OR DL OUTPUT LOW VOLTAGE
vs. TEMPERATURE
0.34
SINKING 100mA
0.32
0.30
0.28
0.26
0.24
0.22
0.20
0.18
OUTPUT LOW VOLTAGE (V)
0.16
0.14
0.12
0.10
-40 125
TEMPERATURE (°C)
MAX5062/3/4 toc09
1109565 80-10 5 20 35 50-25
PEAK DH AND DL
SOURCE/SINK CURRENT
CL = 100nF
2A/div
1μs/div
MAX5062/3/4 toc10
DH OR DL5V/div
SINK AND SOURCE
CURRENT
DH OR DL FALL TIME
= 8V
= 12V
LOAD
= 10nF)
MAX5062/3/4 toc12
1109565 80-10 5 20 35 50-25
vs. TEMPERATURE (C
120
110
100
90
80
70
(ns)
60
F
t
50
40
30
20
10
0
-40 125
VDD = V
BST
VDD = V
BST
TEMPERATURE (°C)
DH OR DL RISE TIME
BST
BST
= 8V
= 12V
= 10nF)
L
vs. TEMPERATURE (C
120
108
96
84
72
(ns)
60
R
t
48
36
24
12
0
-40 125
VDD = V
VDD = V
TEMPERATURE (°C)
DH OR DL RISE PROPAGATION DELAY
vs. TEMPERATURE
60
55
50
45
40
35
30
25
20
PROPAGATION DELAY (ns)
15
10
5
0
-40 125
DH
DL
TEMPERATURE (°C)
MAX5062/3/4 toc11
1109565 80-10 5 20 35 50-25
MAX5062/3/4 toc13
1109565 80-10 5 20 35 50-25
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(Typical values are at VDD= V
BST
= +12V and TA= +25°C, unless otherwise specified.)
DH OR DL FALL PROPAGATION DELAY
60
55
50
45
40
35
30
25
20
PROPAGATION DELAY (ns)
15
10
5
0
-40 125
BREAK-BEFORE-MAKE DEAD TIME
120
MAX5064
110
100
90
80
70
(ns)
60
BBM
t
50
40
30
20
10
0
-40 125
vs. TEMPERATURE
DH
DL
TEMPERATURE (°C)
vs. TEMPERATURE
R
= 100kΩ
BBM
R
= 10kΩ
BBM
TEMPERATURE (°C)
MAX5062/3/4 toc14
1109565 80-10 5 20 35 50-25
MAX5062/3/4 toc16
1109565 80-10 5 20 35 50-25
(ns)
BBM
t
5V/div
5V/div
BREAK-BEFORE-MAKE
DEAD TIME vs. R
250
MAX5064
225
200
175
150
125
100
75
50
25
0
10
50
R
BBM
DELAY MATCHING (DH/DL RISING)
CL = 0
10ns/div
170
(kΩ)
210 25090 130
BBM
MAX5062/3/4 toc15
290
MAX5062/3/4 toc17
INPUT
DH/DL
DELAY MATCHING (DH/DL FALLING)
CL = 0
5V/div
5V/div
10ns/div
MAX5062/3/4 toc18
INPUT
DH/DL
10V/div
10V/div
10V/div
5V/div
DH/DL RESPONSE TO VDD GLITCH
40μs/div
MAX5062/3/4 toc19
DH
DL
V
DD
INPUT
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
8 _______________________________________________________________________________________
MAX5064 Pin Description
PIN NAME FUNCTION
1VDDPower Input. Bypass to GND with a parallel combination of 0.1µF and 1µF ceramic capacitor.
2 BST
Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
3 DH High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.
4 HS Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
5 IN_H High-Side Noninverting Logic Input
6 IN_L
Low-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input
(MAX5062B/D, MAX5063B/D).
7 GND Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.
8 DL Low-Side-Gate Driver Output. Drives low-side MOSFET gate.
—EP
Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground
plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only).
MAX5062/MAX5063 Pin Description
PIN NAME FUNCTION
1 BST
2 DH High-Side-Gate Driver Output. Drives high-side MOSFET gate.
3 HS Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
4 AGND
5 BBM
Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
Analog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced to
Break-Before-Make Programming Resistor Connection. Connect a 10kΩ to 100kΩ resistor from BBM
to AGND to program the break-before-make time (t
greater than 200kΩ disables the BBM function and makes t
1nF capacitor to AGND.
) from 16ns to 95ns. Resistance values
BBM
= 1ns. Bypass this pin with at least a
BBM
6 IN_H-
7 IN_H+
8 IN_L-
9 IN_L+
10 PGND
11 DL Low-Side-Gate Driver Output. Drives the low-side MOSFET gate.
12 V
—EP
DD
High-Side Inverting CMOS (V
AGND when not used.
High-Side Noninverting CMOS (V
V
when not used.
DD
Low-Side Inverting CMOS (V
when not used.
Low-Side Noninverting CMOS (V
V
when not used.
DD
Power Ground. Return path for high-switching current signals. Use PGND as a return path for the
low-side driver.
Power Input. Bypass to PGND with a 0.1µF ceramic in parallel with a 1µF ceramic capacitor.
Exposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in
heat dissipation.
/ 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
DD
/ 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
DD
/ 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND
DD
/ 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
DD
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
_______________________________________________________________________________________ 9
Detailed Description
The MAX5062/MAX5063/MAX5064 are 125V/2A highspeed, half-bridge MOSFET drivers that operate from a
supply voltage of +8V to +12.6V. The drivers are
intended to drive a high-side switch without any isolation device like an optocoupler or drive transformer.
The high-side driver is controlled by a TTL/CMOS logic
signal referenced to ground. The 2A source and sink
drive capability is achieved by using low R
DS_ON
pand n-channel driver output stages. The BiCMOS
process allows extremely fast rise/fall times and low
propagation delays. The typical propagation delay from
the logic-input signal to the drive output is 35ns with a
matched propagation delay of 3ns typical. Matching
these propagation delays is as important as the
absolute value of the delay itself. The high 125V input
voltage range allows plenty of margin above the 100V
transient specification per telecom standards.
The MAX5064 is available in a thermally enhanced
TQFN package, which can dissipate up to 1.95W (at
+70°C) and allow up to 1MHz switching frequency
while driving 100nC combined gate-charge MOSFETs.
Figure 1. Timing Characteristics for Noninverting and Inverting Logic Inputs
IN_L+
IN_L-
IN_H+
V
IH
V
IL
90%
DL
t
D_OFF1
t
F
V
IH
V
t
D_OFF2
V
IL
IL
V
t
D_ON1
t
D_ON2
IH
10%
t
R
90%
DH
t
D_OFF3
t
F
V
t
MATCH1
t
MATCH2
= (t
= (t
IH
D_ON2
D_ON3
- t
- t
D_ON1
D_ON1
t
) or (t
) or (t
D_OFF4
D_OFF2
D_ON4
- t
- t
D_OFF1
D_ON2
)
) or (t
D_OFF3
- t
D_OFF1
V
IL
) or (t
D_OFF4
IN_H-
- t
D_OFF2
)
t
D_ON3
t
D_ON4
10%
t
R
MAX5062/MAX5063/MAX5064
Undervoltage Lockout
Both the high- and low-side drivers feature undervoltage lockout (UVLO). The low-side driver’s UVLO
LOW
threshold is referenced to GND and pulls both driver
outputs low when V
DD
falls below 6.8V. The high-side
driver has its own undervoltage lockout threshold
(UVLO
HIGH
), referenced to HS, and pulls DH low when
BST falls below 6.4V with respect to HS.
During turn-on, once V
DD
rises above its UVLO threshold, DL starts switching and follows the IN_L logic input.
At this time, the bootstrap capacitor is not charged and
the BST-to-HS voltage is below UVLO
BST
. For synchronous buck and half-bridge converter topologies, the
bootstrap capacitor can charge up in one cycle and
normal operation begins in a few microseconds after the
BST-to-HS voltage exceeds UVLO
BST
. In the two-switch
forward topology, the BST capacitor takes some time (a
few hundred microseconds) to charge and increase its
voltage above UVLO
BST
.
The typical hysteresis for both UVLO thresholds is 0.5V.
The bootstrap capacitor value should be selected carefully to avoid unintentional oscillations during turn-on
and turn-off at the DH output. Choose the capacitor
value about 20 times higher than the total gate capacitance of the MOSFET. Use a low-ESR-type X7R dielectric ceramic capacitor at BST (typically a 0.1µF ceramic
is adequate) and a parallel combination of 1µF and
0.1µF ceramic capacitors from V
DD
to GND
(MAX5062_, MAX5063_) or to PGND (MAX5064_). The
high-side MOSFET’s continuous on-time is limited due
to the charge loss from the high-side driver’s quiescent
current. The maximum on-time is dependent on the size
of C
BST
, I
BST
(50µA max), and UVLO
BST
.
Output Driver
The MAX5062/MAX5063/MAX5064 have low 2.5Ω
R
DS_ON
p-channel and n-channel devices (totem pole)
in the output stage. This allows for a fast turn-on and
turn-off of the high gate-charge switching MOSFETs.
The peak source and sink current is typically 2A.
Propagation delays from the logic inputs to the driver
outputs are matched to within 8ns. The internal p- and
n-channel MOSFETs have a 1ns break-before-make
logic to avoid any cross conduction between them. This
internal break-before-make logic eliminates shootthrough currents reducing the operating supply current
as well as the spikes at VDD. The DL voltage is approximately equal to VDDand the DH-to-HS voltage, a diode
drop below VDD, when they are in a high state and to
zero when in a low state. The driver R
DS_ON
is lower at
higher VDD. Lower R
DS_ON
means higher source and
sink currents and faster switching speeds.
Internal Bootstrap Diode
An internal diode connects from VDDto BST and is
used in conjunction with a bootstrap capacitor externally connected between BST and HS. The diode charges
the capacitor from V
DD
when the DL low-side switch is
on and isolates VDDwhen HS is pulled high as the highside driver turns on (see the Typical Operating Circuit).
The internal bootstrap diode has a typical forward voltage drop of 0.9V and has a 10ns typical turn-off/turn-on
time. For lower voltage drops from V
DD
to BST, connect
an external Schottky diode between VDDand BST.
Programmable Break-Before-Make
(MAX5064)
Half-bridge and synchronous buck topologies require
that the high- or low-side switch be turned off before
the other switch is turned on to avoid shoot-through
currents. Shoot-through occurs when both high- and
low-side switches are on at the same time. This condition is caused by the mismatch in the propagation
delay from IN_H/IN_L to DH/DL, driver output impedance, and the MOSFET gate capacitance. Shootthrough currents increase power dissipation, radiate
EMI, and can be catastrophic, especially with high
input voltages.
The MAX5064 offers a break-before-make (BBM) feature that allows the adjustment of the delay from the
input to the output of each driver. The propagation
delay from the rising edges of IN_H and IN_L to the rising edges of DH and DL, respectively, can be programmed from 16ns to 95ns. Note that the BBM time
(t
BBM
) has a higher percentage error at lower value
because of the fixed comparator delay in the BBM
block. The propagation delay mismatch (t
MATCH_
)
needs to be included when calculating the total t
BBM
error. The low 8ns (maximum) delay mismatch reduces
the total t
BBM
variation. Use the following equations to
calculate R
BBM
for the required BBM time and
t
BBM_ERROR
:
where t
BBM
is in nanoseconds.
The voltage at BBM is regulated to 1.3V. The BBM circuit
adjusts t
BBM
depending on the current drawn by R
BBM
.
Bypass BBM to AGND with a 1nF or smaller ceramic
capacitor (C
BBM
) to avoid any effect of ground bounce
caused during switching. The charging time of C
BBM
does not affect t
BBM
at turn-on because the BBM voltage
is stabilized before the UVLO clears the device turn-on.
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
10 ______________________________________________________________________________________
Rk
BBM
ttt
BBM ERROR BBM MATCH
t
⎛
=×
ΩΩ
__
BBM
⎜
⎝
8
.
015
=× +
⎞
−10
1 200
for R k
ns
⎟
⎠
BBM
<
Topologies like the two-switch forward converter, where
both high- and low-side switches are turned on and off
simultaneously, can have the BBM function disabled by
leaving BBM unconnected. When disabled, t
BBM
is typi-
cally 1ns.
Driver Logic Inputs (IN_H, IN_L, IN_H+,
IN_H-, IN_L+, IN_L-)
The MAX5062_/MAX5064A are CMOS (V
DD
/ 2) logicinput drivers while the MAX5063_/MAX5064B have TTLcompatible logic inputs. The logic-input signals are
independent of VDD. For example, the IC can be powered by a 10V supply while the logic inputs are provided from a 12V CMOS logic. Also, the logic inputs are
protected against voltage spikes up to 15V, regardless
of the VDDvoltage. The TTL and CMOS logic inputs
have 400mV and 1.6V hysteresis, respectively, to avoid
double pulsing during transition. The logic inputs are
high-impedance pins and should not be left floating.
The low 2.5pF input capacitance reduces loading and
increases switching speed. The noninverting inputs are
pulled down to GND and the inverting inputs are pulled
up to VDDinternally using a 1MΩ resistor. The PWM
output from the controller must assume a proper state
while powering up the device. With the logic inputs
floating, the DH and DL outputs pull low as VDDrises
up above the UVLO threshold.
The MAX5064_ has two logic inputs per driver, which
provide greater flexibility in controlling the MOSFET.
Use IN_H+/IN_L+ for noninverting logic and IN_H-/
IN_L- for inverting logic operation. Connect
IN_H+/IN_L+ to VDDand IN_H-/IN_L- to GND if not
used. Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low and IN_- for
active-high shutdown logic.
Minimum Pulse Width
The MAX5062/MAX5063/MAX5064 uses a single-shot
level shifter architecture to achieve low propagation
delay. Typical level shifter architecture causes a minimum (high or low) pulse width (t
Dmin
) at the output that
may be higher than the logic-input pulse width. For
MAX5062/MAX5063/MAX5064 devices, the DH minimum high pulse width (t
Dmin-DH-H
) is lower than the DL
minimum low pulse width (t
Dmin-DL-L
) to avoid any
shoot-through in the absence of external BBM delay
during the narrow pulse at low duty cycle (see Figure 2).
At high duty cycle (close to 100%) the DH minimum low
pulse width (t
Dmin-DH-L
) must be higher than the DL
minimum low pulse width (t
Dmin-DL-L
) to avoid overlap
and shoot-through (see Figure 3). In the case of
MAX5062/MAX5063/MAX5064, there is a possibility of
about 40ns overlap if an external BBM delay is not provided. We recommend adding external delay in the INH
path so that the minimum low pulse width seen at INH
is always longer than t
PW-min
. See the Electrical
Characteristics table for the typical values of t
PW-MIN
.
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 11
Figure 2. Minimum Pulse-Width Behavior for Narrow DutyCycle Input (On-Time < t
PW_MIN
)
Table 1. MAX5064_ Truth Table
IN_H+/IN_L+ IN_H-/IN_L- DH/DL
Low Low Low
Low High Low
High Low High
High High Low
V
DD
A)
PWM
IN
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
B)
PWM
IN
DH
INH
INL
t
DMIN-DH-H
V
IN
DH
HS
DL
N
N
V
OUT
BUILT-IN
DEAD TIME
DL
t
DMIN-DL-L
MAX5062/MAX5063/MAX5064
Applications Information
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5062/MAX5063/MAX5064. Peak supply and output
currents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device grounding may also disturb other circuits sharing the same AC
ground return path. Any series inductance in the VDD,
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX5062/
MAX5063/MAX5064 with any capacitive load. Place
one or more 0.1µF ceramic capacitors in parallel as
close to the device as possible to bypass VDDto GND
(MAX5062/MAX5063) or PGND (MAX5064). Use a
ground plane to minimize ground return resistance and
series inductance. Place the external MOSFET as close
as possible to the MAX5062/MAX5063/MAX5064 to further minimize board inductance and AC path resistance. For the MAX5064_ the low-power logic ground
(AGND) is separated from the high-power driver return
(PGND). Apply the logic-input signal between IN_ to
AGND and connect the load (MOSFET gate) between
DL and PGND.
Power Dissipation
Power dissipation in the MAX5062/MAX5063/MAX5064
is primarily due to power loss in the internal boost
diode and the nMOS and pMOS FETS.
For capacitive loads, the total power dissipation for the
device is:
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
12 ______________________________________________________________________________________
Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < t
PW_MIN
)
V
DD
V
IN
A)
EXTERNAL
BBM DELAY
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
V
DD
EXTERNAL
BBM DELAY
INH
INL
INH
DH
DH
HS
DL
V
IN
V
N
N
N
OUT
V
OUT
B)
PWM
PWM
IN
IN
C)
PWM
IN
EXTERNAL
BBM DELAY
t
DMIN-DH-L
DH
POTENTIAL
OVERLAP TIME
HS
INL
DL
N
MAX5062A/MAX5062C/MAX5063A/MAX5063C/MAX5064
PCV f I I V
D L DD SW DDO BSTO DD
DL
⎛
=× ×
⎝
2
t
DMIN-DL-H
⎞
++
()
⎠
×
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 13
where CLis the combined capacitive load at DH and
DL. V
DD
is the supply voltage and fSWis the switching
frequency of the converter. P
D
includes the power dissipated in the internal bootstrap diode. The internal
power dissipation reduces by P
DIODE
, if an external
bootstrap Schottky diode is used. The power dissipation in the internal boost diode (when driving a capacitive load) will be the charge through the diode per
switching period multiplied by the maximum diode forward voltage drop (Vf= 1V).
The total power dissipation when using the internal
boost diode will be PDand, when using an external
Schottky diode, will be PD- P
DIODE
. The total power
dissipated in the device must be kept below the maximum of 1.951W for the 12-pin TQFN package, 1.5W for
the 8-pin SO with exposed pad, and 0.471W for the
regular 8-pin SO package at TA= +70°C ambient.
Layout Information
The MAX5062/MAX5063/MAX5064 drivers source and
sink large currents to create very fast rise and fall
edges at the gates of the switching MOSFETs. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use
the following PC board layout guidelines when designing with the MAX5062/MAX5063/MAX5064:
• It is important that the VDDvoltage (with respect to
ground) or BST voltage (with respect to HS) does
not exceed 13.2V. Voltage spikes higher than 13.2V
from VDDto GND or BST to HS can damage the
device. Place one or more low ESL 0.1µF decoupling ceramic capacitors from VDDto GND
(MAX5062/MAX5063) or to PGND (MAX5064), and
from BST to HS as close as possible to the part. The
ceramic decoupling capacitors should be at least
20 times the gate capacitance being driven.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from gate
to source when the gate is being pulled low. The
active current loop is from the MOSFET driver output
(DL or DH) to the MOSFET gate, to the MOSFET
source, and to the return terminal of the MOSFET driver (either GND or HS). When the gate of the MOSFET is being pulled high, the active current loop is
from the MOSFET driver output, (DL or DH), to the
MOSFET gate, to the MOSFET source, to the return
terminal of the drivers decoupling capacitor, to the
positive terminal of the decoupling capacitor, and to
the supply connection of the MOSFET driver. The
decoupling capacitor will be either the flying capacitor connected between BST and HS or the decoupling capacitor for VDD. Care must be taken to
minimize the physical distance and the impedance of
these AC current paths.
• Solder the exposed pad of the TQFN (MAX5064) or
SO (MAX5062C/D and MAX5063C/D) package to a
large copper plane to achieve the rated power dissipation. Connect AGND and PGND at one point near
VDD’s decoupling capacitor return.
PCV fV
=×
DIODE DH DD SW f
()
××− 1
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
14 ______________________________________________________________________________________
Typical Application Circuits
Figure 4. MAX5062 Half-Bridge Conversion
Figure 5. Synchronous Buck Converter
= 8V TO 12.6V
V
DD
= 0 TO 125V
V
IN
V
DD
BST
DH
MAX5062A/
IN_H
IN_L
MAX5063A
HS
DL
GND
PWM
CONTROLLER
PIN FOR PIN REPLACEMENT FOR THE HIP2100/HIP2101
= 8V TO 12.6V
V
DD
V
BST
DD
DH
MAX5064
PWM
C
BBM
R
BBM
IN_H+
IN_L-
BBM
AGND PGND
HS
DL
N
N
= 0 TO 125V
V
IN
C
BST
N
V
OUT
N
V
OUT
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 15
Typical Application Circuits (continued)
Figure 6. Two-Switch Forward Conversion
Figure 7. MAX5064 Half-Bridge Converter
V
= 8V TO 12.6V
DD
PWM
= 8V TO 12.6V
V
DD
IN_H+
IN_L+
BBM
AGND PGND
= 0 TO 125V
V
IN
C
V
DD
MAX5064
BST
DH
HS
DL
BST
N
V
OUT
N
= 0 TO 125V
V
IN
PWM
C
BBM
R
BBM
IN_H+
IN_L-
BBM
V
DD
MAX5064_
PGNDAGND
BST
DH
C
BST
N
HS
DL
N
V
OUT
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
16 ______________________________________________________________________________________
Pin Configurations
MAX5062A
MAX5062C
GND
V
DD
IN_H
DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
V
DD
/2 CMOS
MAX5064A
PGND
V
DD
IN_H+
IN_L-
DH
DL
HS
BST
BBM
IN_H-
IN_L+
AGND
1
2
4
3
7
8
5
6
11
10
9
12
V
DD
/2 CMOS
MAX5064B
PGND
V
DD
IN_H+
IN_L-
DH
DL
HS
BST
BBM
IN_H-
IN_L+
AGND
1
2
4
3
7
8
5
6
11
10
9
12
TTL
SO/SO-EP
MAX5062B/
MAX5062D
GND
V
DD
IN_H
DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
V
DD
/2 CMOS
SO/SO-EP
MAX5063B/
MAX5063D
GND
V
DD
IN_H
DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
TTL
SO/SO-EP
MAX5063A/
MAX5063C
GND
V
DD
IN_H
DH
DL
HS
BST
IN_L
2
3
4
5
8
7
6
1
TTL
SO/SO-EP
THIN QFN THIN QFN
Functional Diagrams
TOP VIEW
1
V
DD
2
MAX5062A/B
DH
3
MAX5063A/B
4
SO
87DL
GNDBST
1
V
DD
2
MAX5062C/D
DH
IN_L
6
IN_HHS
5
3
4
MAX5063C/D
SO-EP
87DL
GNDBST
IN_L
6
IN_HHS
5
PGND
DD
10
11DL
12
IN_L+8IN_L-7IN_H+
9
MAX5064A/
MAX5064B
12DH3
BST
THIN QFN
IN_H-
6
BBM
5
AGND
4V
HS
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 17
Typical Operating Circuit
PART
TEMP
PIN-
TOP
PKG
CODE
MAX5063AASA
-40°C to
8 SO — S8-5
MAX5063BASA
-40°C to
8 SO — S8-5
MAX5063CASA
-40°C to
—
S8E-14
MAX5063DASA
-40°C to
—
S8E-14
MAX5064AATC
-40°C to
12 TQFN
T1244-4
MAX5064BATC
-40°C to
12 TQFN
T1244-4
Ordering Information (continued)
PART HIGH-SIDE DRIVER LOW-SIDE DRIVER LOGIC LEVELS PIN COMPATIBLE
MAX5063AASA Noninverting Noninverting TTL HIP2101IB
MAX5063BASA Noninverting Inverting TTL —
MAX5063CASA Noninverting Noninverting TTL —
MAX5063DASA Noninverting Inverting TTL —
MAX5064AATC
Both Inverting and
Noninverting
Both Inverting and
Noninverting
CMOS (V
DD
/ 2) —
MAX5064BATC
Both Inverting and
Noninverting
Both Inverting and
Noninverting
TTL —
Selector Guide (continued)
Chip Information
TRANSISTOR COUNT: 790
PROCESS: HV BiCMOS
*EP = Exposed paddle.
Devices are available in both leaded and lead-free packaging.
Specify lead-free by replacing “-T” with “+T” when ordering.
VIN = 125V
V
DD
MAX5064A/
MAX5064B
PWM IN
V
DD
C
BBM
BBM
R
IN_H+
IN_H-
IN_L+
IN_L-
BBM
AGND
BST
V
PGND
DH
HS
DD
DL
8V TO 12.6V
C
BST
C
DD
V
OUT
RANGE
PACKAGE
MARK
+125°C
+125°C
+125°C
+125°C
+125°C
+125°C
8 SO-EP*
8 SO-EP*
AAEF
AAEG
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
18 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
8L, SOIC EXP. PAD.EPS
PACKAGE OUTLINE
8L SOIC, .150" EXPOSED PAD
21-0111
1
C
1
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
______________________________________________________________________________________ 19
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
24L QFN THIN.EPS
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
1
E
2
MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
Revision History
Pages changed at Rev 5: 1, 2, 4, 5, 11–15, 19, 20
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2
2
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