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General Description
The MAX5038/MAX5041 dual-phase, PWM controllers
provide high-output-current capability in a compact
package with a minimum number of external components. The MAX5038/MAX5041 utilize a dual-phase,
average current-mode control that enables optimal use
of low R
DS(ON)
MOSFETs, eliminating the need for exter-
nal heatsinks even when delivering high output currents.
Differential sensing enables accurate control of the out-
put voltage, while adaptive voltage positioning provides
optimum transient response. An internal regulator
enables operation with input voltage ranges of +4.75V to
+5.5V or +8V to +28V. The high switching frequency, up
to 500kHz per phase, and dual-phase operation allow
the use of low-output inductor values and input capacitor
values. This accommodates the use of PC boardembedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size,
and low system cost.
The MAX5038/MAX5041 also feature a clock input
(CLKIN) for synchronization to an external clock, and a
clock output (CLKOUT) with programmable phase delay
(relative to CLKIN) for paralleling multiple phases. The
MAX5038 offers a variety of factory-trimmed preset output
voltages (see Selector Guide) and the MAX5041 offers an
adjustable output voltage from +1.0V to +3.3V.
The MAX5038/MAX5041 operate over the extended
industrial temperature range (-40°C to +85°C) and are
available in a 28-pin SSOP package. Refer to the
MAX5037 data sheet for a VRM 9.0-compatible, VIDcontrolled output voltage controller in a 44-pin MQFP or
QFN package.
Applications
Servers and Workstations
Point-Of-Load High-Current/High-Density
Telecom DC-DC Regulators
Networking Systems
Large-Memory Arrays
RAID Systems
High-End Desktop Computers
Features
♦ +4.75V to +5.5V or +8V to +28V Input Voltage
Range
♦ Up to 60A Output Current
♦ Internal Voltage Regulator for a +12V or +24V
Power Bus
♦ True Differential Remote Output Sensing
♦ Two Out-Of-Phase Controllers Reduce Input
Capacitance Requirement and Distribute Power
Dissipation
♦ Average Current-Mode Control
Superior Current Sharing Between Individual
Phases and Paralleled Modules
Accurate Current Limit Eliminates MOSFET and
Inductor Derating
♦ Integrated 4A Gate Drivers
♦ Selectable Fixed Frequency 250kHz or 500kHz Per
Phase (Up to 1MHz for 2 Phases)
♦ Fixed (MAX5038) or Adjustable (MAX5041) Output
Voltages
♦ 0.5% Accurate Reference (MAX5041B)
♦ External Frequency Synchronization from 125kHz
to 600kHz
♦ Internal PLL with Clock Output for Paralleling
Multiple DC-DC Converters
♦ Thermal Protection
♦ 28-Pin SSOP Package
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
________________________________________________________________Maxim Integrated Products 1
19-2514; Rev 3; 8/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART
TEMP RANGE
PIN-
OUTPUT
VOLTAGE
MAX5038EAI12
Fixed +1.2V
MAX5038EAI15
Fixed +1.5V
MAX5038EAI18
Fixed +1.8V
MAX5038EAI25
Fixed +2.5V
MAX5038EAI33
Fixed +3.3V
MAX5041EAI
Adj +1.0V to
+3.3V
MAX5041BEAI
Adj +1.0V to
+3.3V
Pin Configuration appears at end of data sheet.
PACKAGE
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
-40°C to +85°C 28 SSOP
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND…………………………………….…-0.3V to +35V
DH_ to LX_ ................................-0.3V to [(V
BST
_ - VLX_) + 0.3V]
DL_ to PGND..............................................-0.3V to (V
CC
+ 0.3V)
BST_ to LX_..............................................................-0.3V to +6V
V
CC
to SGND............................................................-0.3V to +6V
V
CC
to PGND............................................................-0.3V to +6V
SGND to PGND.....................................................-0.3V to +0.3V
All Other Pins to SGND...............................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ............762mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETER
CONDITIONS
UNITS
SYSTEM SPECIFICATIONS
828
Input Voltage Range V
IN
Short IN and VCC together for +5V input
operation
5.5
V
Quiescent Supply Current I
Q
EN = VCC or SGND 4 10 mA
Efficiency η I
LOAD
= 52A (26A per phase) 90 %
OUTPUT VOLTAGE
MAX5038 only, no load
Nominal Output Voltage
Accuracy
MAX5038 only, no load, V
IN
= VCC =
+4.75V to +5.5V or V
IN
= +8V to +28V
(Note 2)
-1 +1
%
MAX5041 only, no load
MAX5041 only, no load, VIN = VCC =
+4.75V to +5.5V or V
IN
= +8V to +28V
MAX5041B only, no load
SENSE+ to SENSE- Voltage
Accuracy
MAX5041B only, no load,
V
IN
= +8V to +28V
V
STARTUP/INTERNAL REGULATOR
VCC Undervoltage Lockout UVLO VCC falling 4.0
4.5 V
VCC Undervoltage Lockout
Hysteresis
mV
VCC Output Accuracy VIN = +8V to +28V, I
SOURCE
= 0 to 80mA
5.1
V
MOSFET DRIVERS
Output Driver Impedance R
ON
Low or high output 1 3 Ω
Output Driver Source/Sink
Current
4A
Non-Overlap Time t
NO
CDH_
/DL
_ = 5nF 60 ns
SYMBOL
MIN TYP MAX
4.75
IDH_, IDL_
-0.8 +0.8
0.992 1.008
0.990 1.010
0.995 1.005
0.995 1.005
4.85
4.15
200
5.30
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR AND PLL
CLKIN = SGND
262
Switching Frequency f
SW
CLKIN = V
CC
525
kHz
PLL Lock Range f
PLL
600 kHz
PLL Locking Time t
PLL
µs
PHASE = V
CC
125
PHASE = unconnected 85 90 95
CLKOUT Phase Shift
(at f
SW
= 125kHz)
φ
PHASE = SGND 55 60 65
degrees
CLKIN Input Pulldown Current I
CLKIN
357µA
CLKIN High Threshold
2.4 V
CLKIN Low Threshold
0.8 V
CLKIN High Pulse Width t
CLKIN
ns
PHASE High Threshold
4V
PHASE Low Threshold
1V
PHASE Input Bias Current
I
PHASEBIA
-50
µA
CLKOUT Output Low Level
I
SINK
= 2mA (Note 2) 100 mV
CLKOUT Output High Level
I
SOURCE
= 2mA (Note 2) 4.5 V
CURRENT LIMIT
Average Current-Limit Threshold
V
CL
CSP_ to CSN_ 45 48 51 mV
Cycle-by-Cycle Current Limit V
CLPK
CSP_ to CSN_ (Note 3) 90
130 mV
Cycle-by-Cycle Overload
Response Time
t
R
V
CSP
_ to V
CSN
_ = +150mV
ns
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance RCS_4kΩ
Common-Mode Range
)
V
Input Offset Voltage
)
-1 +1 mV
Amplifier Gain A
V(CS)
18 V/V
3dB Bandwidth f
3dB
4 MHz
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
Transconductance gm
ca
µS
Open-Loop Gain
)
No load 50 dB
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Common-Mode Voltage Range
)
V
DIFF Output Voltage V
CM
V
SENSE+
= V
SENSE-
= 0 0.6 V
Input Offset Voltage
)
-1 +1 mV
MAX5038/MAX5041 (+1.2V, +1.5V, +1.8V
output versions)
1
Amplifier Gain
)
MAX5038 (+2.5V and +3.3V output versions)
0.5
V/V
238 250
475 500
125
200
115 120
CLKOUT
V
CLKINH
V
CLKINL
V
PHASEH
V
PHASEL
V
CLKOUTL
V
CLKOUTH
V
CMR(CS
V
OS(CS
A
VOL(CE
V
CMR(DIFF
V
OS(DIFF
A
V(DIFF
200
112
260
-0.3 +3.6
550
-0.3 +1.0
0.997
0.495
+50
1.003
0.505
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +5V, circuit of Figure 1, TA= -40°C to +85°C, unless otherwise noted. Typical specifications are at TA= +25°C.) (Note 1)
PARAMETER
CONDITIONS
UNITS
3dB Bandwidth f
3dB
C
DIFF
= 20pF 3 MHz
Minimum Output Current Drive
)
1.0 mA
SENSE+ to SENSE- Input
Resistance
R
VS
_50
kΩ
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain
)
70 dB
Unity-Gain Bandwidth f
UGEA
3MHz
EAN Input Bias Current I
B(EA)
V
EAN
= +2.0V
nA
Error-Amplifier Output Clamping
Voltage
)
With respect to V
CM
918 mV
THERMAL SHUTDOWN
Thermal Shutdown T
SHDN
°C
Thermal-Shutdown Hysteresis 8°C
EN INPUT
EN Input Low Voltage V
ENL
1V
EN Input High Voltage V
ENH
3V
EN Pullup Current I
EN
4.5 5 5.5 µA
Note 1: Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Note 2: Guaranteed by design. Not production tested.
Note 3: See Peak-Current Comparator section.
SYMBOL
I
OUT(DIFF
A
VOL(EA
MIN TYP MAX
100
-100 +100
V
CLAMP(EA
810
150
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
_______________________________________________________________________________________ 5
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCY
MAX5038/41 toc01
I
OUT
(A)
η (%)
4844403632282420161284
50
60
70
80
90
100
40
052
f = 500kHz
f = 250kHz
VIN = +5V
V
OUT
= +1.8V
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
MAX5038/41 toc02
I
OUT
(A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
VIN = +12V
VIN = +5V
V
OUT
= +1.8V
f
SW
= 250kHz
EFFICIENCY vs. OUTPUT CURRENT
MAX5038/41 toc03
I
OUT
(A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
VIN = +24V
V
OUT
= +1.8V
f
SW
= 125kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
MAX5038/41 toc04
I
OUT
(A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
V
OUT
= +1.1V
V
OUT
= +1.5V
V
OUT
= +1.8V
VIN = +12V
f
SW
= 250kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
MAX5038/41 toc05
I
OUT
(A)
η (%)
4844403632282420161284
50
40
30
20
10
60
70
80
90
100
0
052
V
OUT
= +1.1V
V
OUT
= +1.5V
V
OUT
= +1.8V
VIN = +5V
f
SW
= 500kHz
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGE
MAX5038/41 toc06
FREQUENCY (kHz)
I
CC
(mA)
550500400 450200 250 300 350150
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
6.0
100 600
VIN = +24V
VIN = +12V
VIN = +5V
EXTERNALCLOCK
NO DRIVER LOAD
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
MAX5038/41 toc07
TEMPERATURE (°C)
I
CC
(mA)
603510-15
10
20
30
40
50
60
70
80
90
100
0
-40 85
250kHz
125kHz
VIN = +12V
C
DL_
= 22nF
C
DH_
= 8.2nF
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
MAX5038/41 toc08
TEMPERATURE (°C)
I
CC
(mA)
603510-15
50
75
100
125
150
175
25
-40 85
600kHz
500kHz
VIN = +5V
C
DL_
= 22nF
C
DH_
= 8.2nF
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVER
MAX5038/41 toc09
C
DRIVER
(nF)
I
CC
(mA)
13117 953
10
20
30
40
50
60
70
80
90
100
0
115
VIN = +12V
f
SW
= 250kHz
Typical Operating Characteristics
(Circuit of Figure 1. TA= +25°C, unless otherwise noted.)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
MAX5038/41 toc10
V
OUT
(V)
(V
CSP_
- V
CSN_
) (mV)
1.71.61.4 1.51.2 1.31.1
46
47
48
49
50
51
52
53
54
55
45
1.0 1.8
PHASE 2
PHASE 1
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMP GAIN (R
F
/ RIN)
MAX5038/41 toc11
I
LOAD
(A)
V
OUT
(V)
5045403530252015105
1.65
1.70
1.75
1.80
1.85
1.60
055
VIN = +12V
V
OUT
= +1.8V
RF / RIN = 15
RF / RIN = 12.5
RF / RIN = 10
RF / RIN = 7.5
DIFFERENTIAL AMPLIFIER BANDWIDTH
MAX5038/41 toc12
FREQUENCY (MHz)
GAIN (V/V)
PHASE (deg)
10.1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.01 10
-225
-270
-180
-135
-90
-45
0
45
90
PHASE
GAIN
DIFF OUTPUT ERROR
vs. SENSE+ TO SENSE- VOLTAGE
MAX5038/41 toc13
∆V
SENSE
(V)
ERROR (%)
1.91.81.1 1.2 1.3 1.5 1.61.4 1.7
0.025
0.050
0.075
0.100
0.125
0.150
0.175
0.200
0
1.0 2.0
VIN = +12V
NO DRIVER
VCC LOAD REGULATION
vs. INPUT VOLTAGE
MAX5038/41 toc14
ICC (mA)
V
CC
(V)
13512015 30 45 75 9060 105
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
4.80
0 150
VIN = +24V
VIN = +12V
VIN = +8V
DC LOAD
VCC LINE REGULATION
MAX5038/41 toc15
VIN (V)
V
CC
(V)
262420 2212 14 16 1810
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
4.75
828
ICC = 0
ICC = 40mA
VCC LINE REGULATION
MAX5038/41 toc16
VIN (V)
V
CC
(V)
13.012.09.0 10.0 11.0
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
4.75
8.0
ICC = 80mA
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
MAX5038/41 toc17
C
DRIVER
(nF)
t
R
(ns)
312616 21116
10
20
30
40
50
60
70
80
90
100
110
120
0
136
DL_
DH_
VIN = +12V
f
SW
= 250kHz
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
MAX5038/41 toc18
C
DRIVER
(nF)
t
F
(ns)
312616 21116
10
20
30
40
50
60
70
80
90
100
110
120
0
136
DL_
DH_
VIN = +12V
f
SW
= 250kHz
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
_______________________________________________________________________________________ 7
100ns/div
HIGH-SIDE DRIVER (DH_)
SINK AND SOURCE CURRENT
DH_
1.6A/div
MAX5038/41 toc19
VIN = +12V
C
DH_
= 22nF
100ns/div
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
DL_
1.6A/div
MAX5038/41 toc20
VIN = +12V
C
DL_
= 22nF
100µs/div
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHz
CLKOUT
5V/div
MAX5038/41 toc21
PLLCMP
200mV/div
VIN = +12V
NO LOAD
350kHz
250kHz
0
100µs/div
PLL LOCKING TIME
250kHz TO 500kHz AND
500kHz TO 250kHz
CLKOUT
5V/div
MAX5038/41 toc22
PLLCMP
200mV/div
0
VIN = +12V
NO LOAD
500kHz
250kHz
100µs/div
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz
CLKOUT
5V/div
MAX5038/41 toc23
PLLCMP
200mV/div
0
VIN = +12V
NO LOAD
250kHz
150kHz
40ns/div
HIGH-SIDE DRIVER (DH_)
RISE TIME
MAX5038/41 toc24
VIN = +12V
C
DH_
= 22nF
DH_
2V/div
40ns/div
HIGH-SIDE DRIVER (DH_)
FALL TIME
MAX5038/41 toc25
DH_
2V/div
VIN = +12V
C
DH_
= 22nF
40ns/div
LOW-SIDE DRIVER (DL_)
RISE TIME
MAX5038/41 toc26
DL_
2V/div
VIN = +12V
C
DL_
= 22nF
40ns/div
LOW-SIDE DRIVER (DL_)
FALL TIME
MAX5038/41 toc27
DL_
2V/div
VIN = +12V
C
DL_
= 22nF
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
500ns/div
OUTPUT RIPPLE
MAX5038/41 toc28
V
OUT
(AC-COUPLED)
10mV/div
VIN = +12V
V
OUT
= +1.75V
I
OUT
= 52A
2ms/div
INPUT STARTUP RESPONSE
MAX5038/41 toc29
VIN
5V/div
VIN = +12V
V
OUT
= +1.75V
I
OUT
= 52A
V
PGOOD
1V/div
V
OUT
1V/div
1ms/div
ENABLE STARTUP RESPONSE
MAX5038/41 toc30
VEN
2V/div
V
PGOOD
1V/div
V
OUT
1V/div
VIN = +12V
V
OUT
= +1.75V
I
OUT
= 52A
40µs/div
LOAD-TRANSIENT RESPONSE
MAX5038/41 toc31
VIN = +12V
V
OUT
= +1.75V
I
STEP
= 8A TO 52A
t
RISE
= 1µs
V
OUT
50mV/div
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1, 13
CSP2,
CSP1
Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
2, 14
CSN2,
CSN1
Current-Sense Differential Amplifier Negative Input. Senses the inductor current.
3 PHASE
Phase-Shift Setting Input. Connect PHASE to V
CC
for 120°, leave PHASE unconnected for 90°, or connect
PHASE to SGND for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
4
External Loop-Compensation Input. Connect compensation network for the phase lock loop (see Phase-
Locked Loop section).
5, 7
CLP2,
CLP1
Current-Error Amplifier Output. Compensate the current loop by connecting an RC network to ground.
6 SGND Signal Ground. Ground connection for the internal control circuitry.
8
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
V
OUT+
at the load. The MAX5038 regulates the difference between SENSE+ and SENSE- according to the
factory preset output voltage. The MAX5041 regulates the SENSE+ to SENSE- difference to +1.0V.
9
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
V
OUT-
or PGND at the load.
10 DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.
11 EAN
Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.
12
Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error
amplifier gain-setting resistors determine the amount of adaptive voltage positioning
15 EN Output Enable. A logic low shuts down the power drivers. EN has an internal 5µA pullup current.
16, 26
BST1,
BST2
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply.
Connect 0.47µF ceramic capacitors between BST_ and LX_.
17, 25
DH1,
DH2
High-Side Gate Driver Output. Drives the gate of the high-side MOSFET.
18, 24
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for
the high-side driver.
19, 23
Low-Side Gate Driver Output. Synchronous MOSFET gate drivers for the two phases.
20 V
CC
Internal +5V Regulator Output. VCC is derived internally from the IN voltage. Bypass to SGND with 4.7µF
and 0.1µF ceramic capacitors.
21 IN
Supply Voltage Connection. Connect IN to V
CC
for a +5V system. Connect the VRM input to IN through an
RC lowpass filter, a 2.2Ω resistor and a 0.1µF ceramic capacitor.
22 PGND
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and V
CC
bypass capacitor
returns together.
27
Oscillator Output. CLKOUT is phase-shifted from CLKIN by the amount specified by PHASE. Use CLKOUT
to parallel additional MAX5038/MAX5041s.
28 CLKIN
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz.
The PWM frequency defaults to the internal oscillator if CLKIN is connected to V
CC
or SGND. Connect
CLKIN to SGND to set the internal oscillator to 250kHz or connect to V
CC
to set the internal oscillator to
500kHz. CLKIN has an internal 5µA pulldown current.
PLLCMP
SENSE+
SENSE-
EAOUT
LX1, LX2
DL1, DL2
CLKOUT
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
10 ______________________________________________________________________________________
MAX5038
MAX5041
IN
EN
PHASE 1
CSP1
DRV_V
CC
RAMP1
GM
IN
CLK
CLP1
CSN1
SHDN
BST1
DL1
LX1
DH1
V
CC
TO INTERNAL CIRCUITS
CSP1
CSN1
CLP1
PHASE 2
CSP2
DRV_V
CC
GM
IN
CLK
CLP2
CSN2
SHDN
BST2
DL2
LX2
DH2
CSP2
CSN2
CLP2
PHASE-
LOCKED
LOOP
RAMP
GENERATOR
RAMP2
CLKIN
CLKOUT
PLLCMP
DIFF
AMP
ERROR
AMP
SENSE-
SENSE+
DIFF
EAN
EAOUT
PGND
PGND
PGND
SGND
V
REF
= V
OUT
for V
OUT ≤
1.8V (MAX5038)
V
REF
= V
OUT
/2 for V
OUT
> 1.8V (MAX5038)
V
REF
= +1.0V (MAX5041)
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
0.6V
Functional Diagram
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 11
Detailed Description
The MAX5038/MAX5041 (Figures 1 and 2) average current-mode PWM controllers drive two out-of-phase
buck converter channels. Average current-mode control improves current sharing between the channels
while minimizing component derating and size. Parallel
multiple MAX5038/MAX5041 regulators to increase the
output current capacity. For maximum ripple rejection
at the input, set the phase shift between phases to 90°
for two paralleled converters, or 60° for three paralleled
converters. Paralleling the MAX5038/MAX5041s
improves design flexibility in applications requiring
upgrades (higher load).
CLKIN
PLLCMP
PGND
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
V
CC
EAOUT
EAN
DIFF
EN
CSP2
CSN2
CSP1
CSN1
MAX5038
3
R1
C39
V
IN
= +12V
C1, C2
21
15
IN
C25
C26
R4
R7
R8
R6
C29
C30
R5
C27
C28
SGND
CLP2
CLP1
Q2
Q1
D2
Q2
D1
V
IN
Q1
V
IN
D4
D3
C32
C12
C31
C3–C7
L2
R3
L1
R2
C13
C8–C11
C14,
C15
C16–C24,
C33
LOAD
+1.8V AT 60A
V
OUT
SENSE -
SENSE +
17
18
19
16
20
25
24
23
26
9
8
14
13
1
2
BST1
V
CC
28
4
10
11
12
7
5
6
22
BST2
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
V
CC
R
X
Figure 1. MAX5038 Typical Application Circuit, VIN= +12V
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
12 ______________________________________________________________________________________
Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor
ripple current, effectively multiplying the switching frequency by the number of phases. Each phase of the
MAX5038/MAX5041 consists of an inner average current loop controlled by a common outer-loop voltage-
error amplifier (VEA) that corrects the output voltage
errors. The MAX5038/MAX5041 utilize a single controlling VEA and an average current mode to force the
phase currents to be equal.
CLKIN
PLLCMP
PGND
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
V
CC
EAOUT
EAN
DIFF
EN
CSP2
CSN2
CSP1
CSN1
MAX5041
3
R1
C39
V
IN
= +12V
C1,
C2
21
15
IN
C25
C26
R4
R7
R8
R6
C29
C30
R5
C27
C28
SGND
CLP2
CLP1
Q2
Q1
D2
Q2
D1
V
IN
Q1
V
IN
D4
D3
C32
C12
C31
C3–C7
L2
R3
L1
R2
C13
C8–C11
C14,
C15
C16–C24,
C33
LOAD
+1.8V AT 60A
V
OUT
SENSE SENSE +
17
18
19
16
20
25
24
23
26
9
8
14
13
1
2
BST1
V
CC
28
4
10
11
12
7
5
6
22
BST2
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
R
H
R
L
V
CC
R
X
Figure 2. MAX5041 Typical Application Circuit, VIN= +12V
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 13
VINand V
CC
The MAX5038/MAX5041 accept a wide input voltage
range of +4.75V to +5.5V or +8V to +28V. All internal
control circuitry operates from an internally regulated
nominal voltage of +5V (VCC). For input voltages of +8V
or greater, the internal VCCregulator steps the voltage
down to +5V. The VCCoutput voltage regulates to +5V
while sourcing up to 80mA. Bypass VCCto SGND with
4.7µF and 0.1µF low-ESR ceramic capacitors for highfrequency noise rejection and stable operation (Figures 1
and 2).
Calculate power dissipation in the MAX5038/MAX5041
as a product of the input voltage and the total VCCregulator output current (ICC). ICCincludes quiescent current (IQ) and gate drive current (IDD):
PD = V
IN
x I
CC
ICC= IQ+ fSWx (QG1+ Q
G2
+ QG3+ QG4)
where, QG1, QG2, Q
G3,
and QG4are the total gate
charge of the low-side and high-side external
MOSFETs, IQis 4mA (typ), and fSWis the switching frequency of each individual phase.
For applications utilizing a +5V input voltage, disable
the VCCregulator by connecting IN and VCCtogether.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX5038/MAX5041 include an undervoltage lockout with hysteresis and a power-on reset circuit for converter turn-on and monotonic rise of the output voltage.
The UVLO threshold is internally set between +4.0V
and +4.5V with a 200mV hysteresis. Hysteresis at
UVLO eliminates “chattering” during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5038/MAX5041 draw up to 4mA of current before
the input voltage reaches the UVLO threshold.
The compensation network at the current error amplifiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes a parallel combination of
capacitors (C28, C30) and resistors (R5, R6) in series
with other capacitors (C27, C29) (see Figures 1 and 2).
The voltage at CLP_ limits the maximum current available to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2V
P-P
voltage ramp signals necessary for the PWM comparators. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to VCCto set the
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock input for the phaselocked loop (PLL). When driven externally, the internal
oscillator locks to the signal at CLKIN. A rising edge at
CLKIN starts the ON cycle of the PWM. Ensure that the
external clock pulse width is at least 200ns. CLKOUT
provides a phase-shifted output with respect to the rising edge of the signal at CLKIN. PHASE sets the
amount of phase shift at CLKOUT. Connect PHASE to
VCCfor 120° of phase shift, leave PHASE unconnected
for 90° of phase shift, or connect PHASE to SGND for
60° of phase shift with respect to CLKIN.
The MAX5038/MAX5041 require compensation on
PLLCMP even when operating from the internal oscillator.
The device requires an active PLL in order to generate
the proper clock signal required for PWM operation.
Control Loop
The MAX5038/MAX5041 use an average current-mode
control scheme to regulate the output voltage (Figures
3a and 3b). The main control loop consists of an inner
current loop and an outer voltage loop. The inner loop
controls the output currents (I
PHASE1
and I
PHASE2
)
while the outer loop controls the output voltage. The
inner current loop absorbs the inductor pole reducing
the order of the outer voltage loop to that of a singlepole system.
The current loop consists of a current-sense resistor
(RS), a current-sense amplifier (CA_), a current-error
amplifier (CEA_), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM_). The precision
CA_ amplifies the sense voltage across R
S
by a factor
of 18. The inverting input to the CEA_ senses the CA_
output. The CEA_ output is the difference between the
voltage-error amplifier output (EAOUT) and the gainedup voltage from the CA_. The RC compensation network connected to CLP1 and CLP2 provides external
frequency compensation for the respective CEA_. The
start of every clock cycle enables the high-side drivers
and initiates a PWM ON cycle. Comparator CPWM_
compares the output voltage from the CEA_ with a 0 to
+2V ramp from the oscillator. The PWM ON cycle terminates when the ramp voltage exceeds the error voltage.
(1)
(2)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
14 ______________________________________________________________________________________
DRIVE 2
DRIVE 1
CPWM1
CPWM2
CEA1
CEA2
VEA
DIFF
AMP
CA1
CA2
CLP2
CSP2
CSN2
CLP1
CSN1
CSP1
SENSE+
SENSE-
V
IN
V
IN
LOAD
C
OUT
V
OUT
RIN*
R
F
*
R
S
R
S
I
PHASE1
I
PHASE2
R
CF
C
CFF
C
CF
R
CF
C
CCF
C
CF
MAX5041
V
REF
=
+1.0V
*RF AND RIN ARE
EXTERNAL TO MAX5041
(R
F
= R8, RIN = R7, FIGURE 2)
Figure 3b. MAX5041 Control Loop
DRIVE 2
DRIVE 1
CPWM1
CPWM2
CEA1
CEA2
VEA
DIFF
AMP
CA1
CA2
V
REF
C
LP2
C
SP2
C
SN
2
C
LP1
C
SN
1
C
SP1
SENSE+
SENSE-
V
IN
V
IN
LOAD
C
OUT
V
OUT
RIN*
R
F
*
R
S
R
S
I
PHASE1
I
PHASE2
R
CF
C
CFF
C
CF
R
CF
C
CCF
C
CF
*RF AND RIN ARE EXTERNAL TO MAX5038
(R
F
= R8, RIN = R7, FIGURE 1)
MAX5038
Figure 3a. MAX5038 Control Loop
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 15
The outer voltage control loop consists of the differential amplifier (DIFF AMP), reference voltage, and VEA.
The unity-gain differential amplifier provides true differential remote sensing of the output voltage. The differential amplifier output connects to the inverting input
(EAN) of the VEA. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5041 reference voltage is set to +1.0V
and the MAX5038 reference is set to the preset output
voltage. The VEA controls the two inner current loops
(Figures 3a and 3b). Use a resistive feedback network
to set the VEA gain as required by the adaptive voltage-positioning circuit (see the Adaptive Voltage
Positioning section).
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense amplifier senses the voltage across a current-sense resistor.
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault conditions such as an output inductor malfunction (Figure 4).
Note that the average current-limit threshold of 48mV
still limits the output current during short-circuit conditions. To prevent inductor saturation, select an output
inductor with a saturation current specification greater
than the average current limit (48mV). Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a cracked output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current comparator has a delay of only 260ns.
Current-Error Amplifier
Each phase of the MAX5038/MAX5041 has a dedicated
transconductance current-error amplifier (CEA_) with a
typical gmof 550µS and 320µA output sink and source
current capability. The current-error amplifier outputs,
CLP1 and CLP2, serve as the inverting input to the
PWM comparator. CLP1 and CLP2 are externally
accessible to provide frequency compensation for the
inner current loops (Figures 3a and 3b). Compensate
CEA_ such that the inductor current down slope, which
becomes the up slope to the inverting input of the PWM
comparator, is less than the slope of the internally generated voltage ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V
P-P
ramp. At the start of each clock
cycle, an R-S flip-flop resets and the high-side driver
(DH_) turns on. The comparator sets the flip-flop as
soon as the ramp voltage exceeds the CLP_ voltage,
thus terminating the ON cycle (Figure 4).
2 x fs (V/s)
RAMP
CLK
CSP_
CSN_
GM
IN
SHDN
CLP_
DRV_V
CC
BST_
DH_
LX_
DL_
PGND
A
V
= 18
PWM
COMPARATOR
PEAK-CURRENT
COMPARATOR
112mV
S
R
Q
Q
Gm =
500µS
Figure 4. Phase Circuit (Phase 1/Phase 2)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
16 ______________________________________________________________________________________
Differential Amplifier
The differential amplifier (DIFF AMP) facilitates output
voltage remote sensing at the load (Figures 3a and 3b).
It provides true differential output voltage sensing while
rejecting the common-mode voltage errors due to highcurrent ground paths. Sensing the output voltage
directly at the load provides accurate load voltage
sensing in high-current environments. The VEA provides the difference between the differential amplifier
output (DIFF) and the desired output voltage. The differential amplifier has a bandwidth of 3MHz. The difference between SENSE+ and SENSE- regulates to the
preset output voltage for the MAX5038 and regulates to
+1V for the MAX5041.
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop and
determines the error between the differential amplifier
output and the internal reference voltage (V
REF
).
V
REF
equals V
OUT(NOM)
for the +1.8V or lower voltage
versions of the MAX5038 and V
REF
equals V
OUT(NOM)
/2
for the +2.5V and +3.3V versions. For MAX5041, V
REF
equals +1V.
An offset is added to the output voltage of the
MAX5038/MAX5041 with a finite gain (RF/RIN) of the
VEA such that the no-load output voltage is higher than
the nominal value. Choose RFand RINfrom the
Adaptive Voltage Positioning section and use the following equations to calculate the no-load output voltage.
MAX5038:
MAX5041:
where RHand RLare the feedback resistor network
(Figure 2).
Some applications require V
OUT
equal to V
OUT(NOM)
at
no load. To ensure that the output voltage does not
exceed the nominal output voltage (V
OUT(NOM)
), add a
resistor RXfrom VCCto EAN.
Use the following equations to calculate the value of RX.
For MAX5038 versions of V
OUT(NOM)
≤ +1.8V:
For MAX5038 versions of V
OUT(NOM)
> +1.8V:
For MAX5041:
The VEA output clamps to +0.9V (plus the commonmode voltage of +0.6V), thus limiting the average maximum current from individual phases. The maximum
average current-limit threshold for each phase is equal
to the maximum clamp voltage of the VEA divided by
the gain (18) of the current-sense amplifier. This allows
for accurate settings for the average maximum current
for each phase. Set the VEA gain using RFand RINfor
the amount of output voltage positioning required as
discussed in the Adaptive Voltage Positioning section
(Figures 3a and 3b).
Adaptive Voltage Positioning
Powering new-generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward-voltage excursion when the output current suddenly decreases. A larger allowed, voltage-step excursion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
Voltage positioning and the ability to operate with multiple
reference voltages may require the output to regulate
away from a center value. Define the center value as the
voltage where the output drops (∆V
OUT
/2) at one half the
maximum output current (Figure 5).
RV
R
V
XCC
F
REF
=−×[.]16
RVV
R
V
X CC NOM
F
NOM
=− +×[( .)]212
RV V
R
V
X CC NOM
F
NOM
=− +×[( .)]06
V
R
R
RR
R
V
OUT NL
IN
F
HL
L
REF()
=+
⎛
⎝
⎜
⎞
⎠
⎟
×
+
⎛
⎝
⎜
⎞
⎠
⎟
×1
V
R
R
V
OUT NL
IN
F
OUT NOM() ( )
=+
⎛
⎝
⎜
⎞
⎠
⎟
×1
(3)
(4)
(5)
(6)
(7)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 17
Set the voltage-positioning window (∆V
OUT
) using the
resistive feedback of the VEA. Use the following equations to calculate the voltage-positioning window for the
MAX5038:
Use the following equation to calculate the voltage-positioning window for the MAX5041:
where R
IN
and RFare the input and feedback resistors of
the VEA, GCis the current-loop gain and RSis the current-sense resistor or, if using lossless inductor current
sensing, the DC resistance of the inductor.
Phase-Locked Loop: Operation and
Compensation
The PLL synchronizes the internal oscillator to the
external frequency source when driving CLKIN.
Connecting CLKIN to VCCor SGND forces the PWM
frequency to default to the internal oscillator frequency
of 500kHz or 250kHz, respectively. The PLL uses a
conventional architecture consisting of a phase detector and a charge pump capable of providing 20µA of
output current. Connect an external series combination
capacitor (C25) and resistor (R4) and a parallel capacitor (C26) from PLLCMP to SGND to provide frequency
compensation for the PLL (Figure 1). The pole-zero pair
compensation provides a zero at fZ= 1 / [R4 x (C25 +
C26)] and a pole at fP= 1 / (R4 x C26). Use the following typical values for compensating the PLL:
R4 = 7.5kΩ, C25 = 4.7nF, C26 = 470pF. If changing the
PLL frequency, expect a finite locking time of approximately 200µs.
The MAX5038/MAX5041 require compensation on
PLLCMP even when operating from the internal oscillator. The device requires an active PLL in order to generate the proper internal PWM clocks.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figures 1
and 2). The drivers’ high-peak sink and source current
capability provides ample drive for the fast rise and fall
times of the switching MOSFETs. Faster rise and fall
times result in reduced cross-conduction losses. For
modern CPU voltage-regulating module applications
where the duty cycle is less than 50%, choose highside MOSFETs (Q1 and Q3) with a moderate R
DS(ON)
and a very low gate charge. Choose low-side
MOSFETs (Q2 and Q4) with very low R
DS(ON)
and
moderate gate charge.
The driver block also includes a logic circuit that pro-
vides an adaptive non-overlap time to prevent shootthrough currents during transition. The typical
non-overlap time is 60ns between the high-side and
low-side MOSFETs.
BST_
VDDpowers the low- and high-side MOSFET drivers.
Connect a 0.47µF low-ESR ceramic capacitor between
BST_ and LX_. Bypass VCCto PGND with 4.7µF and
0.1µF low-ESR ceramic capacitors. Reduce the PC
board area formed by these capacitors, the rectifier
diodes between VCCand the boost capacitor, the
MAX5038/MAX5041, and the switching MOSFETs.
G
R
C
S
=
005.
∆V
IR
GR
RR
R
OUT
OUT IN
CF
HL
L
=
×
××
()
×
+
2
G
R
C
S
=
005.
∆V
IR
GR
OUT
OUT IN
CF
=
×
××2
LOAD (A)
V
CNTR
NO LOAD
1/2 LOAD
FULL LOAD
VOLTAGE-POSITIONING W
INDOW
V
CNTR
+ ∆V
OUT
/2
V
CNTR
- ∆V
OUT
/2
Figure 5. Defining the Voltage-Positioning Window
(8)
(9)
(10)
(11)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
18 ______________________________________________________________________________________
Overload Conditions
Average current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA output clamps to +0.9V with respect to the common-mode
voltage (VCM= +0.6V) and is compared with the output
of the current-sense amplifiers (CA1 and CA2) (see
Figures 3a and 3b). The current-sense amplifier’s gain
of 18 limits the maximum current in the inductor or
sense resistor to I
LIMIT
= 50mV/RS.
Parallel Operation
For applications requiring large output current, parallel
up to three MAX5038/MAX5041s (six phases) to triple
the available output current. The paralleled converters
operate at the same switching frequency but different
phases keep the capacitor ripple RMS currents to a minimum. Three parallel MAX5038/MAX5041 converters
deliver up to 180A of output current. To set the phase
shift of the on-board PLL, leave PHASE unconnected for
90° of phase shift (2 paralleled converters), or connect
PHASE to SGND for 60° of phase shift (3 converters in
parallel). Designate one converter as master and the
remaining converters as slaves. Connect the master and
slave controllers in a daisy-chain configuration as shown
in Figure 6. Connect CLKOUT from the master controller
to CLKIN of the first slaved controller, and CLKOUT from
the first slaved controller to CLKIN of the second slaved
controller. Choose the appropriate phase shift for minimum ripple currents at the input and output capacitors.
The master controller senses the output differential voltage through SENSE+ and SENSE- and generates the
DIFF voltage. Disable the voltage sensing of the slaved
controllers by leaving DIFF unconnected (floating).
Figure 7 shows a detailed typical parallel application circuit using two MAX5038s. This circuit provides four
phases at an input voltage of +12V and an output voltage range of +1V to +3.3V at 104A.
Applications Information
Each MAX5038/MAX5041 circuit drives two 180° out-ofphase channels. Parallel two or three MAX5038/
MAX5041 circuits to achieve four- or six-phase operation, respectively. Figure 1 shows the typical application
circuit for a two-phase operation. The design criteria for
a two-phase converter includes frequency selection,
inductor value, input/output capacitance, switching
MOSFETs, sense resistors, and the compensation network. Follow the same procedure for the four- and sixphase converter design, except for the input and output
capacitance. The input and output capacitance requirements vary depending on the operating duty cycle.
The examples discussed in this data sheet pertain to a
typical application with the following specifications:
V
IN
= +12V
V
OUT
= +1.8V
I
OUT(MAX)
= 52A
fSW= 250kHz
Peak-to-Peak Inductor Current (∆IL) = 10A
Table 1 shows a list of recommended external compo-
nents (Figure 1) and Table 2 provides component supplier information.
Number of Phases
Selecting the number of phases for a voltage regulator
depends mainly on the ratio of input-to-output voltage
(operating duty cycle). Optimum output-ripple cancellation depends on the right combination of operating duty
cycle and the number of phases. Use the following
equation as a starting point to choose the number of
phases:
N
PH
≈ K/D
where K = 1, 2, or 3 and the duty cycle is D = V
OUT/VIN.
Choose K to make NPHan integer number. For example, converting VIN= +12V to V
OUT
= +1.8V yields
better ripple cancellation in the six-phase converter
than in the four-phase converter. Ensure that the output
load justifies the greater number of components for
multiphase conversion. Generally limiting the maximum
output current to 25A per phase yields the most costeffective solution. The maximum ripple cancellation
occurs when NPH= K/D.
Single-phase conversion requires greater size and power
dissipation for external components such as the switching MOSFETs and the inductor. Multiphase conversion
eliminates the heatsink by distributing the power dissipation in the external components. The multiple phases
operating at given phase shifts effectively increase the
switching frequency seen by the input/output capacitors,
thereby reducing the input/output capacitance requirement for the same ripple performance. The lower inductance value improves the large-signal response of the
converter during a transient load at the output. Consider
all these issues when determining the number of phases
necessary for the voltage regulator application.
Inductor Selection
The switching frequency per phase, peak-to-peak ripple current in each phase, and allowable ripple at the
output determine the inductance value.
(12)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 19
CLKIN
CLKOUTSGNDPGND
IN
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
V
CC
V
IN
EAOUT
EAN
DIFF
SENSE-
SENSE+
CSP2
CSN2
CSP1
CSN1
V
CC
V
IN
V
IN
CLKOUTSGNDPGND
IN
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
EAOUT
EAN
CLKIN
CSP2
CSN2
CSP1
CSN1
DIFF
V
CC
V
IN
V
IN
CLKOUTSGNDPGND
IN
PHASE
DL2
LX2
DH2
DL1
LX1
DH1
EAOUT
EAN
CLKIN
CSP2
CSN2
CSP1
CSN1
DIFF
V
CC
V
IN
V
IN
TO OTHER MAX5038/MAX5041s
MAX5038/
MAX5041
MAX5038/
MAX5041
MAX5038/
MAX5041
LOAD
*FOR MAX5041 ONLY.
*
*
Figure 6. Parallel Configuration of Multiple MAX5038/MAX5041s
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
20 ______________________________________________________________________________________
MAX5038
(MASTER)
Q4
Q3
D2
Q2
D1
V
IN
4 x 22µF
C8–C11
Q1
V
IN
VIN = +12V
V
CC
D4
D3
C40
0.1µF
C12
0.47µF
C38
4.7µF
C3–C7
5 x 22µF
L2
0.6µH
R2
1.35mΩ
L1
0.6µH
R1
1.35mΩ
DH1
LX1
DL1
BST1
V
CC
DH2
LX2
DL2
BST2
CSP2CSN2PGOODPHASECLKOUTSGNDPGNDCLP2CLP1
R9
PGOOD
V
CC
R6
C35
C36
R5
C33
C34
C39
0.1µF
C1, C2
2 x 47µF
R3
2.2Ω
C31
C32
R4
CSP1CSN1SENSE+SENSE-INCLKINPLLCMP
R8
R7
EAOUT
EAN
DIFF
OVPIN
EN
C13
0.47µF
C14, C15,
C41, C42
2 x 100µF
C16–C25,
C43–C46
14 x 270µF
C26–C30,
C37
6
x
10µF
LOAD
V
OUT
= +1.1V TO
+3.3V AT 104A
V
CC
MAX5038
(SLAVE)
Q8
Q7
D6
Q6
D5
V
IN
C52–C55
4 x 22µF
Q5
V
IN
D8
D7
C64
0.1µF
C57
0.47µF
C65
4.7µF
C48–C51
5 x 22µF
L4
0.6µH
R11
1.35mΩ
L3
0.6µH
R10
1.35mΩ
DH1
LX1
DL1
BST1
V
CC
DH2
LX2
DL2
BST2
CSP2CSN2PHASESGNDPGNDCLP2CLP1
V
CC
R15
C59
C58
R14
C60
C61
C47
0.1µF
R12
2.2Ω
C62
C63
R13
CSP1CSN1SENSE+SENSE-CLKININPLLCMPEN
R17
R16
EAOUT
EAN
DIFF
C56
0.47µF
R18
R19
V
CC
R
X
V
CC
R
X
Figure 7. Four-Phase Parallel Application Circuit (VIN= +12V, V
OUT
= +1.1V to +3.3V at 104A)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 21
Table 1. Component List
DESIGNATION QTY DESCRIPTION
C1, C2 2 47µF,16V X5R input-filter capacitors TDK C5750X5R1C476M
C3–C11 9 22µF, 16V input-filter capacitors TDK C4532X5R1C226M
C12, C13 2 0.47µF, 16V capacitors TDK C1608X5R1A474K
C14, C15 2 100µF, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3
C16–C24, C33 10 270µF, 2V output-filter capacitors Panasonic EEFUE0D271R
C25 1 4700pF, 16V X7R capacitor Vishay-Siliconix VJ0603Y471JXJ
C26, C28, C30 3 470pF 16V capacitors Murata GRM1885C1H471JAB01
C27, C29 2 0.01µF 50V X7R capacitors Murata GRM188R71H103KA01
C31 1 4.7µF 16V X5R capacitor Murata GRM40-034X5R475k6.3
C32 3 0.1µF 16V X7R capacitors Murata GRM188R71C104KA01
D1, D2 2 Schottky diodes ON-Semiconductor MBRS340T3
D3, D4 2 Schottky diodes ON-Semiconductor MBR0520LT1
L1, L2 2 0.6µH, 27A inductors Panasonic ETQP1H0R6BFX
Q1, Q3 2 Upper-power MOSFETs Vishay-Siliconix Si7860DP
Q2, Q4 2 Lower-power MOSFETs Vishay-Siliconix Si7886DP
R1 1 2.2Ω ±1% resistor
R2, R3 4 Current-sense resistors, use two 2.7mΩ resistors in parallel, Panasonic ERJM1WSF2M7U
R4 1 7.5kΩ ±1% resistor
R5, R6 2 1kΩ ±1% resistors
R7 1 4.99kΩ ±1% resistor
R8, R9 2 37.4kΩ ±1% resistors
Table 2. Component Suppliers
SUPPLIER PHONE FAX WEBSITE
Murata 770-436-1300 770-436-3030 www.murata.com
ON Semiconductor 602-244-6600 602-244-3345 www.on-semi.com
Panasonic 714-373-7939 714-373-7183 www.panasonic.com
TDK 847-803-6100 847-390-4405 www.tcs.tdk.com
Vishay-Siliconix 1-800-551-6933 619-474-8920 www.vishay.com
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
22 ______________________________________________________________________________________
Selecting higher switching frequencies reduces the
inductance requirement, but at the cost of lower efficiency. The charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs create switching
losses. The situation worsens at higher input voltages,
since switching losses are proportional to the square of
input voltage. Use 500kHz per phase for VIN= +5V and
250kHz or less per phase for VIN> +12V.
Although lower switching frequencies per phase increase
the peak-to-peak inductor ripple current (∆IL), the ripple
cancellation in the multiphase topology reduces the input
and output capacitor RMS ripple current.
Use the following equation to determine the minimum
inductance value:
Choose ∆ILequal to about 40% of the output current
per phase. Since ∆ILaffects the output-ripple voltage,
the inductance value may need minor adjustment after
choosing the output capacitors for full-rated efficiency.
Choose inductors from the standard high-current,
surface-mount inductor series available from various
manufacturers. Particular applications may require custom-made inductors. Use high-frequency core material
for custom inductors. High ∆ILcauses large peak-to-peak
flux excursion increasing the core losses at higher frequencies. The high-frequency operation coupled with
high ∆IL, reduces the required minimum inductance
and even makes the use of planar inductors possible.
The advantages of using planar magnetics include lowprofile design, excellent current-sharing between phases due to the tight control of parasitics, and low cost.
For example, calculate the minimum inductance at
V
IN(MAX)
= +13.2V, V
OUT
= +1.8V, ∆IL= 10A, and fSW=
250kHz:
The average current-mode control feature of the
MAX5038/MAX5041 limits the maximum peak inductor
current which prevents the inductor from saturating.
Choose an inductor with a saturating current greater
than the worst-case peak inductor current.
Use the following equation to determine the worst-case
inductor current for each phase:
where R
SENSE
is the sense resistor in each phase.
Switching MOSFETs
when choosing a MOSFET for voltage regulators,
consider the total gate charge, R
DS(ON)
, power dissipation, and package thermal impedance. The product of
the MOSFET gate charge and on-resistance is a figure of
merit, with a lower number signifying better performance.
Choose MOSFETs optimized for high-frequency switching applications.
The average gate-drive current from the MAX5038/
MAX5041 output is proportional to the total capacitance
it drives from DH1, DH2, DL1, and DL2. The power dissipated in the MAX5038/MAX5041 is proportional to the
input voltage and the average drive current. See the V
IN
and VCCsection to determine the maximum total gate
charge allowed from all the driver outputs together.
The gate charge and drain capacitance (CV2)loss, the
cross-conduction loss in the upper MOSFET due to finite
rise/fall time, and the I2R loss due to RMS current in the
MOSFET R
DS(ON)
account for the total losses in the MOS-
FET. Estimate the power loss (PD
MOS
_) in the high-side
and low-side MOSFETs using following equations:
where Q
G
, R
DS(ON)
, tR, and tFare the upper-switching
MOSFET’s total gate charge, on-resistance at +25°C,
rise time, and fall time, respectively.
where D = V
OUT/VIN
, I
DC
= (I
OUT
- ∆IL)/2 and I
PK
=
(I
OUT
+ ∆IL)/2
IIIII
D
RMS HI
DC PK
DC PK−
=++×
()
×
22
3
PD Q V f
VI tt f
RI
MOS HI G DD SW
IN OUT R F SW
DS ON
RMS HI−−
=××
()
+
××+
()
×
⎛
⎝
⎜
⎞
⎠
⎟
+×
4
14
2
.
()
I
R
I
L PEAK
SENSE
L
_
.
=+
0 051
2
∆
L
k
H
MIN
=
−
()
×
××
=µ
13 2 1 8 1 8
13 2 250 10
06
.. .
.
.
L
VVV
Vf I
MIN
INMAX OUT OUT
IN SW L
=
−
()
×
××∆
(13)
(14)
(15)
(16)
(17)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 23
For example, from the typical specifications in the
Applications Information section with V
OUT
= +1.8V, the
high-side and low-side MOSFET RMS currents are 9.9A
and 24.1A, respectively. Ensure that the thermal impedance of the MOSFET package keeps the junction temperature at least 25°C below the absolute maximum
rating. Use the following equation to calculate maximum junction temperature:
TJ= PD
MOS
x θ
J-A
+ T
A
Input Capacitors
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple
reflected back to the source dictate the capacitance
requirement. Increasing the number of phases increases the effective switching frequency and lowers the
peak-to-average current ratio, yielding lower input
capacitance requirement.
The input ripple is comprised of ∆VQ(caused by the
capacitor discharge) and ∆V
ESR
(caused by the ESR of
the capacitor). Use low-ESR ceramic capacitors with
high ripple-current capability at the input. Assume the
contributions from the ESR and capacitor discharge are
equal to 30% and 70%, respectively. Calculate the
input capacitance and ESR required for a specified ripple using the following equation:
where I
OUT
is the total output current of the multiphase
converter and N is the number of phases.
For example, at V
OUT
= +1.8V, the ESR and input
capacitance are calculated for the input peak-to-peak
ripple of 100mV or less yielding an ESR and capacitance value of 1mΩ and 200µF.
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
In multiphase converter design, the ripple currents from
the individual phases cancel each other and lower the
ripple current. The degree of ripple cancellation
depends on the operating duty cycle and the number of
phases. Choose the right equation from Table 3 to calculate the peak-to-peak output ripple for a given duty
cycle of two-, four-, and six-phase converters. The maximum ripple cancellation occurs when NPH= K / D.
C
I
N
DD
Vf
IN
OUT
QSW
=
×−
()
×
1
∆
ESR
V
I
N
I
IN
ESR
OUT L
=
()
+
⎛
⎝
⎜
⎞
⎠
⎟
∆
∆
2
IIIII
D
RMS LO
DC PK
DC PK−
=++×
()
×
−
()
22
1
3
PD Q V f
CVf
RI
MOS LO G DD SW
OSS IN SW
DS ON
RMS LO−−
=××
()
+
×××
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
+×
2
3
14
2
2
.
()
Table 3. Peak-to-Peak Output Ripple
Current Calculations
NUMBER OF
PHASES (N)
DUTY
EQUATION FOR ∆I
P-P
2 < 50%
2 > 50%
4 0 to 25%
4
4 > 50%
6 < 17%
(18)
(19)
(20)
(21)
(22)
CYCLE (D)
25% to 50%
VD
∆I
=
VVD
()
IN O
∆I
=
∆I
=
VDD
()()12 4 1
O
∆I
=
×××
2
VD D
()( )2134
O
∆I
=
∆I
=
−×()12
O
Lf
SW
21
−
Lf
VD
O
Lf
−
()
×
SW
−×()14
SW
−−
DLf
SW
−−
DLf
××
SW
VD
−×()16
O
Lf
SW
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
24 ______________________________________________________________________________________
The allowable deviation of the output voltage during the
fast transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (t
RESPONSE
) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆V
OUT
). Assume 50% contribution each from the output capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
where I
STEP
is the load step and t
RESPONSE
is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Current Limit
The average current-mode control technique of the
MAX5038/MAX5041 accurately limits the maximum output current per phase. The MAX5038/MAX5041 sense
the voltage across the sense resistor and limit the peak
inductor current (I
L-PK
) accordingly. The ON cycle terminates when the current-sense voltage reaches 45mV
(min). Use the following equation to calculate maximum
current-sense resistor value:
where PDRis the power dissipation in sense resistors.
Select 5% lower value of R
SENSE
to compensate for any
parasitics associated with the PC board. Also, select a
non-inductive resistor with the appropriate wattage rating.
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5038/MAX5041 use
an average current-mode control scheme to regulate
the output voltage (Figures 3a and 3b). I
PHASE1
and
I
PHASE2
are the inner average current loops. The VEA
output provides the controlling voltage for these current
sources. The inner current loop absorbs the inductor
pole reducing the order of the outer voltage loop to that
of a single-pole system.
A resistive feedback around the VEA provides the best
possible response, since there are no capacitors to
charge and discharge during large-signal excursions, R
F
and RINdetermine the VEA gain. Use the following equation to calculate the value for RF:
where GCis the current-loop gain and N is number of
phases.
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid sub-harmonic oscillations
similar to those in peak current-mode control with insufficient slope compensation. Use the following equation to
calculate the resistor RCF:
For example, the maximum RCFis 12kΩ for R
SENSE
=
1.35mΩ.
C
CF
provides a low-frequency pole while RCFprovides a
midband zero. Place a zero at fZto obtain a phase bump
at the crossover frequency. Place a high-frequency pole
(fP) at least a decade away from the crossover frequency
to achieve maximum phase margin.
R
fL
VR
CF
SW
OUT SENSE
≤
×××
×
210
2
G
R
C
S
=
005.
R
IR
NG V
F
OUT IN
C OUT
=
×
××∆
PD
R
R
SENSE
=
×
−
25 10
3
.
R
I
N
SENSE
OUT
=
0 045.
C
It
V
OUT
STEP RESPONSE
Q
=
×
∆
ESR
V
I
OUT
ESR
STEP
=
∆
(23)
(24)
(25)
(26)
(27)
(28)
(29)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
______________________________________________________________________________________ 25
Use the following equations to calculate CCFand C
CFF
:
PC Board Layout
Use the following guidelines to layout the switching
voltage regulator.
1) Place the VINand VCCbypass capacitors close to
the MAX5038/MAX5041.
2) Minimize the high-current loops from the input
capacitor, upper switching MOSFET, inductor, and
output capacitor back to the input capacitor negative terminal.
3) Keep short the current loop from the lower switching MOSFET, inductor, and output capacitor and
return to the source of the lower MOSFET.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative terminal of the input filter capacitor.
6) Run the current-sense lines CS+ and CS- very
close to each other to minimize the loop area.
Similarly, run the remote voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power circuitry. Sense the current right at the pads of current-sense resistors.
7) Avoid long traces between the VCCbypass capacitors, driver output of the MAX5038/MAX5041,
MOSFET gates and PGND pin. Minimize the loop
formed by the VCCbypass capacitors, bootstrap
diode, bootstrap capacitor, MAX5038/MAX5041,
and upper MOSFET gate.
8) Place the bank of output capacitors close to the load.
9) Distribute the power components evenly across the
board for proper heat dissipation.
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
11) Use at least 4oz copper to keep the trace induc tance and resistance to a minimum. Thin copper PC
boards can compromise efficiency since high currents are involved in the application. Also, thicker
copper conducts heat more effectively, thereby
reducing thermal impedance.
Chip Information
TRANSISTOR COUNT: 5431
PROCESS: BiCMOS
C
fR
CFF
PCF
=
×× ×
1
2 π
C
fR
CF
ZCF
=
×× ×
1
2 π
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLKIN
CLKOUT
BST2
DH2
LX2
DL2
EN
PGND
IN
V
CC
DL1
LX1
DH1
BST1
CSN1
CSP1
EAOUT
EAN
DIFF
SENSE-
SENSE+
CLP1
SGND
CLP2
PLLCMP
PHASE
CSN2
CSP2
SSOP
TOP VIEW
MAX5038A
MAX5041A
Pin Configuration
(30)
(31)
MAX5038/MAX5041
Dual-Phase, Parallelable, Average Current-Mode
Controllers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SSOP.EPS
PACKAGE OUTLINE, SSOP, 5.3 MM
1
1
21-0056
C
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
7.90
H
L
0∞
0.301
0.025
8∞
0.311
0.037
0∞
7.65
0.63
8∞
0.95
MAX
5.38
MILLIMETERS
B
C
D
E
e
A1
DIM
A
SEE VARIATIONS
0.0256 BSC
0.010
0.004
0.205
0.002
0.015
0.008
0.212
0.008
INCHES
MIN
MAX
0.078
0.65 BSC
0.25
0.09
5.20
0.05
0.38
0.20
0.21
MIN
1.73 1.99
MILLIMETERS
6.07
6.07
10.07
8.07
7.07
INCHES
D
D
D
D
D
0.239
0.239
0.397
0.317
0.278
MIN
0.249
0.249
0.407
0.328
0.289
MAX
MIN
6.33
6.33
10.33
8.33
7.33
14L
16L
28L
24L
20L
MAX
N
A
D
e
A1
L
C
HE
N
12
B
0.068
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.
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