MAXIM MAX503 User Manual

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

19-0279; Rev 0; 8/94

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

_______________General Description

The MAX503 is a low-power, 10-bit, voltage-output digital­to-analog converter (DAC) that uses single 5V or dual ±5V
supplies. This device has an internal voltage reference plus
an output buffer amplifier. Operating current is only 250µA
from a single 5V supply, making it ideal for portable and
battery-powered applications. In addition, the shrink small­outline package (SSOP) measures only 0.1 square inches,
using less board area than an 8-pin DIP. 10-bit resolution is
achieved through laser trimming of the DAC, op amp, and
reference. No further adjustments are necessary.

Internal gain-setting resistors can be used to define a DAC
output voltage range of 0V to +2.048V, 0V to +4.096V, or
±2.048V. Four-quadrant multiplication is possible without
the use of external resistors or op amps. The parallel logic
inputs are double buffered and are compatible with 4-bit, 8­bit, and 16-bit microprocessors. For a hardware and soft­ware compatible 12-bit upgrade, refer to the MAX530 data
sheet. For DACs with similar features but with a serial data
interface, refer to the MAX504/MAX515 data sheet.

________________________Applications

Battery-Powered Data-Conversion Products
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
Microprocessor-Controlled Calibration

____________________________Features

♦ Buffered Voltage Output
♦ Internal 2.048V Voltage Reference
♦ Operates from Single 5V or Dual ±5V Supplies
♦ Low Power Consumption:

250µA Operating Current
40µA Shutdown-Mode Current

♦ SSOP Package Saves Space

1

♦ Relative Accuracy: ±

Temperature

/

LSB Max Over

2

♦ Guaranteed Monotonic Over Temperature
♦ 4-Quadrant Multiplication with No External

Components

♦ Power-On Reset
♦ Double-Buffered Parallel Logic Inputs

______________Ordering Information

PART TEMP. RANGE PIN-PACKAGE

MAX503CNG 0°C to +70°C 24 Narrow Plastic DIP
MAX503CWG 0°C to +70°C 24 Wide SO
MAX503CAG 0°C to +70°C 24 SSOP
MAX503ENG -40°C to +85°C 24 Narrow Plastic DIP
MAX503EWG -40°C to +85°C 24 Wide SO
MAX503EAG -40°C to +85°C 24 SSOP

Refer to the MAX530 for military temperature or die equivalents.

MAX503

________________Functional Diagram

REFOUT REFIN ROFS

REFGND

AGND

CLR

LDAC

18 13 22

2.048V

REFERENCE
17
14

POWER-ON

RESET

15

8

A0

9

A1

CONTROL

11

CS

WR

LOGIC

10

16

________________________________________________________________

24 1
D6/S0

D7/S1

DAC

10-BIT DAC LATCH

DAC LATCH

NBM

NBL
INPUT
LATCH

INPUT
LATCH

234567

D2

D8/D0

D3

D9/D1

MAX503

D4

D5

NBH
INPUT
LATCH

21

RFB

20

VOUT

23

V

DD

12

DGND

19

V

SS

__________________Pin Configuration

TOP VIEW

D7/S1
D8/D0
D9/D1

D2
D3
D4

D5

A0

A1

WR

CS

DGND

1
2
3
4

MAX503

5
6
7
8

9
10
11
12

DIP/SO/SSOP

Maxim Integrated Products

Call toll free 1-800-998-8800 for free samples or literature.

24
23

22
21
20

19
18
17
16
15
14
13

D6/S0
V

DD

ROFS
RFB
VOUT
V

SS

REFOUT
REFGND
LDAC
CLR
AGND
REFIN

1

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

ABSOLUTE MAXIMUM RATINGS

VDDto DGND and VDDto AGND................................-0.3V, +6V

to DGND and VSSto AGND .................................-6V, +0.3V

V

SS

to VSS............................................................... -0.3V, +12V

V

DD

AGND to DGND........................................................-0.3V, +0.3V

REFGND to AGND.........................................-0.3V, (V

Digital Input Voltage to DGND .................... -0.3V, (V

REFIN..................................................(V

MAX503

REFOUT..............................................(V

REFOUT to REFGND.................................... -0.3V, (V

RFB ....................................................(V

ROFS ..................................................(V

Note 1: The output may be shorted to VDD, VSS, DGND, or AGND if the continuous package power dissipation and current ratings

are not exceeded. Typical short-circuit currents are 20mA.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

- 0.3V), (VDD+ 0.3V)

SS

- 0.3V), (VDD+ 0.3V)

SS

- 0.3V), (VDD+ 0.3V)

SS

- 0.3V), (VDD+ 0.3V)

SS

DD
DD

DD

+ 0.3V)
+ 0.3V)

+ 0.3V)

VOUT to AGND (Note 1) .............................................. V

Continuous Current, Any Input ........................................±20mA

Continuous Power Dissipation (T

Narrow Plastic DIP (derate 13.33mW/°C above +70°C)...1067mW

Wide SO (derate 11.76mW/°C above +70°C)............... 941mW

SSOP (derate 8.00mW/°C above +70°C) ......................640mW

Operating Temperature Ranges

MAX503C_G .........................................................0°C to +70°C

MAX503E_G ......................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +165°C

Lead Temperature (soldering, 10sec) ........................... +300°C

= +70°C)

A

SS,VDD

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(VDD= 5V, VSS= 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C
RL= 10kΩ, CL= 100pF, TA= T

PARAMETER SYMBOL MIN TYP MAX UNITS

STATIC PERFORMANCE

Resolution
Relative Accuracy INL ±0.5 LSB(Note 2)

Differential Nonlinearity DNL ±1 LSB
Unipolar Offset Error V
Unipolar Offset

Temperature Coefficient
Unipolar Offset-Error

Supply Rejection
Gain Error (Note 2) GE LSB±1
Gain-Error Temperature Coefficient 1 ppm/°C

Gain-Error Power-Supply Rejection PSRR 0.1 LSB/V

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range 0V
Resistive Load 2 kΩ
DC Output Impedance 0.2 Ω
Short-Circuit Current I

REFERENCE INPUT (REFIN)

Reference Input Range 0V
Reference Input Resistance 40 kΩ
Reference Input Capacitance 10 50 pF
AC Feedthrough -80 dB

to T

MIN

, unless otherwise noted.)

MAX

CONDITIONS

N 10 Bits

Guaranteed monotonic

OS

TCV

OS

PSRR 0.1 LSB/V

4.5V ≤ VDD≤ 5.5V
DAC latch = all 1s,

VOUT < VDD- 0.4V (Note 2)

4.5V ≤ VDD≤ 5.5V

VOUT = 2V, load regulation ≤ ±0.5LSB

SC

Code dependent, minimum at code 0101...
Code dependent (Note 3)
(Note 4)

0 0.25 3 LSB

= 33µF,

REFOUT

3 ppm/°C

- 0.4 V

DD

12 mA

- 2 V

DD

2 _______________________________________________________________________________________

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(VDD= 5V, VSS= 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 10kΩ, CL= 100pF, TA= T

R

L

PARAMETER

REFERENCE OUTPUT (REFOUT)

Reference Tolerance V

Reference Output Resistance R
Power-Supply Rejection Ratio PSRR 200 µV/V
Noise Voltage e
Temperature Coefficient
Required External Capacitor C

DYNAMIC PERFORMANCE

Voltage Output Slew Rate
Voltage Output Settling Time
Digital Feedthrough 5 nV-s

Signal-to-Noise Plus
Distortion Ratio

DIGITAL INPUTS (S0, S1, D0–D9, LDAC, CLR, CS, WR, A0, A1)

Logic High Input V
Logic Low Input V
Digital Leakage Current ±1 µA
Digital Input Capacitance 8 pF

POWER SUPPLIES

Positive Supply-Voltage Range V
Positive Supply Current I

SWITCHING CHARACTERISTICS

Address to WR Setup t
Address to WR Hold t
CS to WR Setup t
CS to WR Hold t
Data to WR Setup
Data to WR Hold
WR Pulse Width t
LDAC Pulse Width t
CLR Pulse Width t

Internal Power-On Reset
Pulse Width

to T

MIN

, unless otherwise noted.)

MAX

SYMBOL MIN TYP MAX UNITS

REFOUT

REFOUT

REFOUT

SINAD

MAX503C
MAX503E
(Note 5)

4.5V ≤ VDD≤ 5.5V

0.1Hz to 10kHz

n

TA= +25°C
To ±0.5LSB, VOUT = 2V
WR = VDD, digital inputs all 1s to all 0s
Unity gain (Note 4)
Gain = 2 (Note 4)

IH

IL

VIN= 0V or V

DD

Outputs unloaded, all digital inputs = 0V or V

DD

AWS
AWH
CWS
CWH

t

DS

t

DH

WR

LDAC

CLR

t

(Note 3) 1.3 10 µs

POR

CONDITIONS

2.024 2.048 2.072TA= +25°C

2.011 2.085

3.3 µF

0.15 0.25 V/µs

2.4 V

DD

4.5 5.5 V

DD

5 ns
5 ns
0 ns
0 ns

45 ns

0 ns
45 ns
45 ns
45 ns

= 33µF,

REFOUT

2 Ω

400

30

25

68
68

250 400 µA

µVp-p

ppm/°C

0.8 V

MAX503

V2.015 2.081

µs

dB

_______________________________________________________________________________________ 3

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies

(VDD= 5V, VSS= -5V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 10kΩ, CL= 100pF, TA= T

R

L

PARAMETER

STATIC PERFORMANCE

Resolution N

MAX503

Relative Accuracy INL +0.5 LSB
Differential Nonlinearity
Bipolar Offset Error V
Bipolar Offset

Temperature Coefficient
Bipolar Offset-Error

Power-Supply Rejection
Gain Error ±1 LSB

Gain-Error Temperature Coefficient TC 1
Gain-Error Power-Supply Rejection

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range
Resistive Load
DC Output Impedance
Short-Circuit Current I

REFERENCE INPUT (REFIN)

Reference Input Range
Reference Input Resistance 40 kΩ
Reference Input Capacitance
AC Feedthrough -80 dB

REFERENCE OUTPUT (REFOUT)—Specifications are identical to those under Single +5V Supply
DYNAMIC PERFORMANCE—Specifications are identical to those under Single +5V Supply
DIGITAL INPUTS (S0, S1, D0–D9, LDAC, CLR, CS, WR, A0, A1)—Specifications are identical to those under Single +5V Supply
POWER SUPPLIES

Positive Supply Voltage V
Negative Supply Voltage V
Positive Supply Current I
Negative Supply Current I

SWITCHING CHARACTERISTICS—Specifications are identical to those under Single +5V Supply

Note 2: In single supply, INL and GE are calculated from code 3 to code 1023 (code excludes S0 and S1).
Note 3: Guaranteed by design.
Note 4: REFIN = 1kHz, 2.0Vp-p.
Note 5: Tested at I

= 100µA. The reference can typically source up to 5mA (see

OUT

to T

MIN

, unless otherwise noted.)

MAX

SYMBOL MIN TYP MAX

DNL ±1 LSB

Guaranteed monotonic

OS

TCV

OS

PSRR

PSRR 0.1 LSB/V

4.5V ≤ VDD≤ 5.5V, -5.5V ≤ V

4.5V ≤ VDD≤ 5.5V, -5.5V ≤ VSS≤ -4.5V

VOUT = 2V, load regulation ≤ ±0.5LSB

SC

Code dependent, minimum at code 0101...
Code dependent (Note 3)
(Note 4)

DD

SS

Outputs unloaded, all digital inputs = 0V or V

DD

Outputs unloaded, all digital inputs = 0V or V

SS

CONDITIONS

SS

10

≤ -4.5V

VSS+ 0.4 VDD- 0.4

2 kΩ

VSS+ 2 V

10 50 pF

4.5 5.5 V

-5.5 0 V

DD
DD

Typical Operating Characteristics

= 33µF,

REFOUT

3 ppm/°C

0.1 LSB/V

0.2
20 mA

250 400 µA
150 200 µA

±3

DD

).

UNITS

Bits

LSB

ppm/°C

V

Ω

- 2 V

4 _______________________________________________________________________________________

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

__________________________________________Typical Operating Characteristics

(Single +5V supply, unity gain, code = all 1s, TA = +25°C, unless otherwise noted.)

OUTPUT SINK CAPABILITY vs.

OUTPUT PULL-DOWN VOLTAGE

16
14
12
10

8
6
4

OUTPUT SINK CAPABILITY (mA)

2

0

0 0.8

0.2 0.4

OUTPUT PULL-DOWN VOLTAGE (V)

REFERENCE VOLTAGE vs.

2.055

2.050

REFERENCE VOLTAGE (V)

2.045

-60 120

TEMPERATURE

-20 20 80
TEMPERATURE (°C)

80
70
60
50
40
30
20

SIGNAL-TO-NOISE RATIO (dB)

10

0

_______________________________________________________________________________________

MAX503-1

0.6

60

1.0

MAX503-4

100400-40

140

AMPLIFIER SIGNAL-TO-NOISE RATIO

REFIN = 4Vp-p

DUAL SUPPLIES (±5V)

10 1k 100k

FREQUENCY (Hz)



OUTPUT SOURCE CAPABILITY vs.

OUTPUT PULL-UP VOLTAGE

8
7
6
5
4
3
2

OUTPUT SOURCE CAPABILITY (mA)

1
0

12

04

OUTPUT PULL-UP VOLTAGE (V)

3

MAX503-2

5

SUPPLY CURRENT vs. TEMPERATURE

300
290

280

270

260

250

SUPPLY CURRENT (µA)

240

230

-60 -20 60 140

-40 0 40 80 120

10k100

20 100

TEMPERATURE (°C)

200

MAX503-7

100

GAIN (dB)

-100

-200

-300

0

1

MAX503-5

GAIN AND PHASE vs.

FREQUENCY

(G = 2)
(G = 1)

10 100

FREQUENCY (kHz)

ANALOG FEEDTHROUGH vs.

-110

-100

-90

-80

-70

-60

-50

-40

-30

ANALOG FEEDTHROUGH (dB)

-20

-10
0

1 10 1k 100k

FREQUENCY

REFIN = 2V

p-p

CODE = ALL 0s,
DUAL SUPPLIES (±5V)

100 10k 1M

FREQUENCY (Hz)

GAIN vs. FREQUENCY

4

REFIN = 4Vp-p

2
0

-2

-4

-6

GAIN (dB)

-8

-10

-12

-14
1 100 100k

GAIN

DUAL SUPPLIES (±5V)

PHASE

1k 10k

FREQUENCY (Hz)



180

MAX503-8

0

PHASE SHIFT (Degrees)

-180

800

MAX503

MAX503-3

MAX503-6

5

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

____________________________Typical Operating Characteristics (continued)

(Single +5V supply, unity gain, code = all 1s, TA = +25°C, unless otherwise noted.)

REFERENCE OUTPUT VOLTAGE

vs. REFERENCE LOAD CURRENT

2.0480

2.0475

2.0470

2.0465

2.0460

2.0455

2.0450
0 5.0

1.0 2.0 4.0

0.5 1.5 2.5 3.5 4.5
REFERENCE LOAD CURRENT (mA)

A

3.0

MAX503-10

MAX503

SUPPLY CURRENT vs. REFIN

250

200

150

100

SUPPLY CURRENT (µA)

50

0

REFGND = AGND

REFGND = V

DD

EXTERNAL REFERENCE

0 500

100 200 400

50 150 250 350 450

300

REFIN (mV)

MAX503-9

REFERENCE OUTPUT (V)

DIGITAL FEEDTHROUGH

B

2µs/div

SETTLING TIME (RISING)

A

B

5µs/div

A: DIGITAL INPUTS RISING EDGE,
B: VOUT

NO LOAD, 1V/div

,

DUAL SUPPLY (±5V)
LDAC = LOW
BIPOLAR CONFIGURATION
V

= 2V

REFIN



SETTLING TIME (FALLING)

A: DIGITAL INPUTS FALLING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
DUAL SUPPLY (±5V)
LDAC = LOW
BIPOLAR CONFIGURATION
V

= 2V

REFIN

5µs/div

A: S0, S1, D0–D9 = 100kHz, 4Vp-p
B: VOUT, 10mV/div
LDAC = CS = HIGH 

6 _______________________________________________________________________________________

A

B

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

______________________________________________________________Pin Description

PIN FUNCTION

1 D7 input when A0 = A1 = 1, or S1 input when A0 = 0 and A1 = 1. Always set S1 to 0.*
2 D8 input when A0 = A1 = 1, or D0 input when A0 = 0 and A1 = 1.*
3 D9 input when A0 = A1 = 1, or D1 input when A0 = 0 and A1 = 1.*
4 D2 Input Data, or tie to S0 and multiplex when A0 = 1 and A1 = 0.*
5 D3 D3 Input Data, or tie to S1 and multiplex when A0 = 1 and A1 = 0.*
6 D4 D4 Input Data, or tie to D0 and multiplex when A0 = 1 and A1 = 0.*
7 D5 D5 Input Data, or tie to D1 and multiplex when A0 = 1 and A1 = 0.*

8 A0

9 A1

10 WR Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1.
11 CS Chip Select (active low). Enables addressing and writing to this chip from common bus lines.
12 DGND Digital Ground

13 REFIN

14 AGND Analog Ground
15 CLR Clear (active low). A low on CLR resets the DAC latches to all 0s.

16 LDAC

17 REFGND

18 REFOUT Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC.
19 V
20 VOUT Voltage Output. Op-amp buffered DAC output.
21 RFB Feedback Pin. Op-amp feedback resistor. Always connect to VOUT.
22 ROFS Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output.
23 V
24 D6/S0 D6 input when A0 = A1 = 1, or S0 input when A0 = 0 and A1 = 1. Always set S0 to 0.*

* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode.

NAME

D7/S1
D8/D0
D9/D1

D2

SS

DD

Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM),
and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.)

Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and A1 =
0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing.

Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to
REFOUT (pin 18) to use the internal 2.048V reference.

Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input
latch to the DAC latch and updates VOUT.

Reference Ground must be connected to AGND when using the internal reference. Connect to V
to disable the internal reference and save power.

Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation.

Positive Power Supply (+5V)

DD

MAX503

_______________________________________________________________________________________ 7

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

________________Detailed Description

The MAX503 consists of a parallel-input logic interface, a
10-bit R-2R ladder, a reference, and an op amp. The

Functional Diagram

flow through the input data latch to the DAC latch, as well
as the 2.048V reference and output op amp. Total supply
current is typically 250µA with a single +5V supply. This

MAX503

circuit is ideal for battery-powered, microprocessor-con­trolled applications where high accuracy, no adjustments,
and minimum component count are key requirements.

The MAX503 uses an “inverted” R-2R ladder network with
a BiCMOS op amp to convert 10-bit digital data to analog
voltage levels. Figure 1 shows a simplified diagram of the
R-2R DAC and op amp. Unlike a standard DAC, the
MAX503 uses an “inverted” ladder network. Normally, the
REFIN pin is the current output of a standard DAC and
would be connected to the summing junction, or virtual
ground, of an op amp. In this standard DAC configura­tion, however, the output voltage would be the inverse of

*

REFIN
AGND

REFOUT

2.048V

REFGND

D6/S0

D7/S1

LSB

NBL
INPUT
LATCH

shows the control lines and signal

R-2R Ladder

MAX503



RRR

2R2R 2R 2R 2R

LSB

D8/D0

D9/D1

DAC LATCH

NBM
INPUT
LATCH

D2

D4

D3

D5

MSB

MSB

NBH

INPUT

LATCH

*SHOWN FOR ALL 1s

2R
2R

OUTPUT
BUFFER

R = 80kΩ

CLR

ROFS
RFB

VOUT

the reference voltage. The MAX503’s topology makes the
ladder output voltage the same polarity as the reference
input, making the device suitable for single-supply oper­ation. The BiCMOS op amp is then used to buffer, invert,
or amplify the ladder signal.

Ladder resistors are nominally 80kΩ to conserve power
and are laser trimmed for gain and linearity. The input
impedance at REFIN is code dependent. When the DAC
register is all 0s, all rungs of the ladder are grounded
and REFIN is open or no load. Maximum loading (mini-

mum REFIN impedance) occurs at code 010101....

Minimum reference input impedance at this code is guar­anteed to be not less than 40k Ω.

The REFIN and REFOUT pins allow the user to choose
between driving the R-2R ladder with the on-chip refer­ence or an external reference. REFIN may be below ana­log ground when using dual supplies. See the

Reference

and

Four-Quadrant Multiplication

External

sections for

more information.

Internal Reference

The on-chip reference is laser trimmed to generate

2.048V at REFOUT. The output stage can source and
sink current so REFOUT can settle to the correct volt­age quickly in response to code-dependent loading
changes. Typically, source current is 5mA and sink
current is 100µA.

REFOUT connects the internal reference to the R-2R
DAC ladder at REFIN. The R-2R ladder draws 50µA
maximum load current. If any other connection is made
to REFOUT, ensure that the total load current is less
than 100µA to avoid gain errors.

A separate REFGND pin is provided to isolate refer­ence currents from other analog and digital ground
currents. To achieve specified noise performance, con­nect a 33µF capacitor from REFOUT to REFGND (see
Figure 2). Using smaller capacitance values increases
noise, and values less than 3.3µF may compromise the
reference’s stability. For applications requiring the low­est noise, insert a buffered RC filter between REFOUT
and REFIN. When using the internal reference,
REFGND must be connected to AGND. In applications
not requiring the internal reference, connect REFGND
to V

, which shuts down the reference. This saves

DD

typically 100µA of V
the need for C

REFOUT

supply current and eliminates

DD

.

Figure 1. Simplified MAX503 DAC Circuit

8 _______________________________________________________________________________________

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

R

REFOUT

C

REFOUT

300

SINGLE POLE ROLLOFF

250

)

RMS

200

150

100

REFERENCE NOISE (µV

50

0

0.1

Figure 2. Reference Noise vs. Frequency

S

C

S

TEK 7A22

C

REFOUT

1 10 100

FREQUENCY (kHz)

= 3.3µF

C

REFOUT

TOTAL
REFERENCE
NOISE

= 47µF

1.8

1.6

MAX503-FIG02

1.4

1.2

1.0

0.8

0.6

0.4

REFERENCE NOISE (mVp-p)

0.2

0.0

1000

Output Buffer

The output amplifier uses a folded cascode input stage
and a type AB output stage. Large output devices with
low series resistance allow the output to swing to
ground in single-supply operation. The output buffer is
unity-gain stable. Input offset voltage and supply cur­rent are laser trimmed. Settling time is 25µs to 0.01% of
final value. The output is short-circuit protected and
can drive a 2kΩ load with more than 100pF of load
capacitance. The op amp may be placed in unity-gain
(G = 1), in a gain of two (G = 2), or in a bipolar-output
mode by using the ROFS and RFB pins. These pins are
used to define a DAC output voltage range of 0V to
+2.048V, 0V to +4.096V or ±2.048V, by connecting
ROFS to VOUT, GND, or REFIN. RFB is always con­nected to VOUT. Table 1 summarizes ROFS usage.

Table 1. ROFS Usage

An external reference in the range (VSS+ 2V) to

External Reference

(VDD- 2V) may be used with the MAX503 in dual-sup­ply, unity-gain operation. In single-supply, unity-gain
operation, the reference must be positive and may not
exceed (VDD- 2V). The reference voltage determines
the DAC’s full-scale output.

If an upgrade to the internal reference is required, the

2.5V MAX873A is ideal: ±15mV initial accuracy,
7ppm/°C (max) temperature coefficient.

Power-On Reset

An internal power-on reset (POR) circuit forces the
DAC register to reset to all 0s when VDDis first applied.
The POR pulse is typically 1.3µs; however, it may take
2ms for the internal reference to charge its large filter
capacitor and settle to its trimmed value.

In addition to POR, a clear (CLR) pin, when held low,
sets the DAC register to all 0s. CLR operates asynchro­nously and independently from chip select (CS). With
the DAC input at all 0s, the op-amp output is at zero for
unity-gain and G = 2 configurations, but it is at -V

REF

for the bipolar configuration.

Shutdown Mode

The MAX503 is designed for low power consumption.
Understanding the circuit allows power consumption
management for maximum efficiency. In single-supply
mode (VDD= +5V, VSS= GND) the initial supply cur­rent is typically only 160µA, including the reference, op
amp, and DAC. This low current occurs when the
power-on reset circuit clears the DAC to all 0s and
forces the op-amp output to zero (unipolar mode only).
See the Supply Current vs. REFIN graph in the

Operating Characteristics

. Under this condition, there

Typical

is no internal load on the reference (DAC = all 0s,
REFIN is open circuit) and the op amp operates at its
minimum quiescent current. The CLR signal resets the
MAX503 to these same conditions and can be used to
control a power-saving mode when the DAC is not
being used by the system.

MAX503

ROFS

CONNECTED TO:

VOUT 0V to 2.048V G = 1
AGND 0V to 4.096V G = 2
REFIN -2.048V to +2.048V Bipolar

Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V

DAC OUTPUT

RANGE

_______________________________________________________________________________________ 9

OP-AMP

GAIN

5V, Low-Power, Parallel-Input,

CLR CS WR LDAC

Voltage-Output, 10-Bit DAC

REFOUT REFIN ROFS

2N7002

CLR

33µF

REFGND

AGND
DGND

CLR

A0
A1
CS

WR

LDAC

POWER-ON

RESET

CONTROL

LOGIC

MAX503

MAX503

Figure 3. Low-Current Shutdown Mode

Table 2. Input Latch Addressing

A0 A1 DATA UPDATED

L X X X X X Reset DAC latches
H H X H X X No operation
H X H H X X No operation
H L L H H H NBH (D6–D9)
H L L H H L NBM (D2–D5)

H L L H L H
H H H L X X Update DAC only

H L L X L L

H L L L H H NBH and update DAC

NBL (S0 = 0, S1 = 0,
D0, D1)

NBL and NBM (S0, S1,
D0–D5), DAC not
updated

2.048V

REFERENCE

D6/S0

MAX503



NBL

INPUT

LATCH

D7/S1

RFB

V

OUT

DAC

V

DD

+5V

V

SS

D8/D0

10-BIT DAC LATCH

D2

D9/D1

NBM

INPUT

LATCH

D3

NBH

INPUT

LATCH

D4

D5

An additional 110µA of supply current can be saved
when the internal reference is not used by connecting
REFGND to VDD. A low on-resistance N-channel FET,
such as the 2N7002, can be used to turn off the internal
reference to create a shutdown mode with minimum
current drain (Figure 3). When CLR is high, the transis­tor pulls REFGND to AGND and the reference and DAC
operate normally. When CLR goes low, REFGND is
pulled up to VDDand the reference is shut down. At the
same time, CLR resets the DAC register to all 0s, and
the op-amp output goes to 0V for unity-gain and
G = 2 modes. This reduces the total single-supply
operating current from 250µA (400µA max) to typically
40µA in shutdown mode.

10 ______________________________________________________________________________________

A0–A1

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

MAX503

ADDRESS BUS VALID

V

IH

V

IL

t

CS

t

WR

CWS

t

t

AWS

WR

AWH

t

CWH

DATA BITS

(8-BIT BYTE

OR 4-BIT NIBBLE)

CLR

LDAC

NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS

t

CLR

V

IH + VIL

2

Figure 4. MAX503 Write-Cycle Timing Diagram

A small error voltage is added to the reference output
by the reference current flowing through the N-channel
pull-down transistor. The switch’s on resistance should
be less than 5Ω. A typical reference current of 100µA
would add 0.5mV to REFOUT. Since the reference cur­rent and on resistance increase with temperature, the
overall temperature coefficient will degrade slightly.

As data is loaded into the DAC and the output moves
above GND, the op-amp quiescent current increases to
its nominal value and the total operating current aver­ages 250µA. Using dual supplies (±5V), the op amp is
fully biased continuously, and the VDDsupply current is
more constant at 250µA. The V

current is typically

SS

150µA.
The MAX503 logic inputs are compatible with TTL and

CMOS logic levels. However, to achieve the lowest
power dissipation, drive the digital inputs with rail-to-rail
CMOS logic. With TTL logic levels, the power require­ment increases by a factor of approximately 2.

V
V

t

IH
IL

DS

DATA BUS

VALID

t

DH

t

LDAC

Parallel Logic Interface

In order to provide hardware and software compatibility
with the 12-bit MAX530, the MAX503 employs a 12-bit
digital interface. As shown in Figure 3, there is actually
a 12-bit input latch, and therefore 12 bits of data should
be written. The two least significant bits (S1 and S0) are
sub-LSB, and must always be 0s. Designed to interface
with 4-bit, 8-bit, and 16-bit microprocessors (µPs), the
MAX503 uses 8 data pins and double-buffered logic
inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit
DAC latch is updated simultaneously through the con­trol signal LDAC. Signals A0, A1, WR, and CS select
which input latches to update. The 12-bit data is bro­ken down into nibbles (NB); NBL is the enable signal
for the lowest 4 bits (S0, S1, D0, D1), NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.

Refer to Figure 4 for the MAX503 write-cycle timing
diagram.

______________________________________________________________________________________ 11

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

DATA BUS

D0–D3

FROM

SYSTEM

RESET

MAX503

MC6800

R/W

A0–A15



∅2

ADDRESS BUS A0, A1

Figure 5. 4-Bit µP Interface

NBH

NBM

NBL

CS

WR

LDAC

Figure 6. 4-Bit µP Timing Sequence

D0–D3

S0, S1, D0, D1

CLR
A0, A1

WR CS

EN

DECODER

A13–A15

A0 = 1, A1 = 1

D0–D3

D2–D5

MAX503

LDAC

A0 = 1, A1 = 0

DATA BUS

D0–D7

FROM

MC6809

A0–A15

E

R/W

SYSTEM

RESET

ADDRESS BUS

CLR

A0–A1

EN

A0

Figure 7. 8-Bit and 16-Bit µP Interface

A0 = 0, A1 = 1

DAC UPDATE

D0–D7

S0, S1, D0–D5

WR

DECODER

A13–A15

MAX503

CS LDAC

NBH

NBL & NBM

CS

WR

LDAC

A0 = A1 = 1

A0 = A1 = 0

DAC UPDATE

Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC

12 ______________________________________________________________________________________

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

MAX503

V

OUT

A0 = A1 = 0

A0 = A1 = 1

DAC UPDATE

33µF

REFIN
REFOUT

ROFS

AGND
DGND
REFGND

+5V

V

DD

MAX503

V

SS

0V TO -5V

RFB

VOUT

G = 2

V

OUT

NBL & NBM

NBH

CS

WR

LDAC = 0 (DAC LATCH IS TRANSPARENT)

Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0

+5V

V

REFIN
REFOUT

33µF

AGND
DGND

REFGND

Figure 9. Unipolar Configuration (0V to +2.048V Output) Figure 10. Unipolar Configuration (0V to +4.096V Output)

DD

MAX503

V

SS

0V TO -5V

ROFS

RFB

VOUT

G = 1

Figure 5 shows the circuit configuration for a 4-bit µP
application. Figure 6 shows the corresponding timing
sequence. The 4 low bits (S0, S1, D0, D1) are connect­ed in parallel to the other 4 bits (D2–D5) and then to the
µP bus. Address lines A0 and A1 enable the input data
latches for the high, middle, or low data nibbles. The µP
sends chip select (CS) and write (WR) signals to latch
in each of three nibbles in three cycles when the data is
valid.

Figure 7 shows a typical interface to an 8-bit or a 16-bit
µP. Connect 8 data bits from the data bus to pins S0,
S1, and D0–D5 on the MAX503. With LDAC held high,
the user can load NBH or NBL + NBM in any order.
Figure 8a shows the corresponding timing sequence.
For fastest throughput, use Figure 8b’s sequence.
Address lines A0 and A1 are tied together and the DAC
is loaded in 2 cycles as 8 + 4. In this scheme, with
LDAC held low, the DAC latch is transparent. Always
load NBL and NBM first, followed by NBH.

______________________________________________________________________________________ 13

LDAC is asynchronous with respect to WR. If LDAC is
brought low before or at the same time WR goes high,
LDAC must remain low for at least 50ns to ensure the
correct data is latched. Data is latched into DAC regis­ters on LDAC’s rising edge.

Unipolar Configuration

The MAX503 is configured for a 0V to V

REFIN

unipolar
output range by connecting ROFS and RFB to VOUT
(Figure 9). The converter operates from either single or
dual supplies in this configuration. See Table 3 for the
DAC-latch contents (input) vs. the analog VOUT (output).
In this range, 1LSB = V

A 0V to 2V

REFIN

REFIN

unipolar output range is set up by con-

(2

-10

).

necting ROFS to AGND and RFB to VOUT (Figure 10).
Table 4 shows the DAC-latch contents vs. VOUT. The
MAX503 operates from either single or dual supplies in
this mode. In this range, 1LSB = (2)(V
(V

)(2-9).

REFIN

REFIN

)(2

-10

) =

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

Table 3. Unipolar Binary Code Table
(0V to V

INPUT*

1111 1111

MAX503

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

A -V

REFIN

necting ROFS to REFIN and RFB to VOUT, and operat­ing from dual (±5V) supplies (Figure 11). Table 5
shows the DAC-latch contents (input) vs. VOUT (out­put). In this range, 1LSB = V

The MAX503 can be used as a four-quadrant multiplier
by connecting ROFS to REFIN and RFB to VOUT, and
using (1) an offset binary digital code, (2) bipolar
power supplies, and (3) a bipolar analog input at
REFIN within the range VSS+ 2V to VDD- 2V, as shown
in Figure 12.

In general, a 10-bit DAC’s output is D(V
where “G” is the gain (1 or 2) and “D” is the binary rep­resentation of the digital input divided by 210or 1,024.
This formula is precise for unipolar operation. However,
for bipolar, offset binary operation, the MSB is really a
polarity bit. No resolution is lost because the number of
steps is the same. The output voltage, however, has
been shifted from a range of, for example, 0V to

4.096V (G = 2) to a range of -2.048V to +2.048V.
Keep in mind that when using the DAC as a four-quad-

rant multiplier, the scale is skewed. The negative full
scale is -V
+V

REFIN

- 1LSB.

Output), Gain = 1

REFIN

OUTPUT

(V

REFIN

(V

(V

(V

REFIN

REFIN

)

REFIN

REFIN

)

)

512

1024

)

)

OV

11(00)

01(00)

00(00)

11(00)

01(00)

00(00)

(V

Bipolar Configuration

to +V

bipolar range is set up by con-

REFIN

(2 -9).

REFIN

Four-Quadrant Multiplication

, while the positive full scale is

REFIN

1023
1024

513

1024

= +V

511

1024

1

1024

REFIN



REFIN

Table 4. Unipolar Binary Code Table
(0V to 2V

INPUT*

1111 1111

1000 0000

/2

1000 0000

0111 1111

0000 0000

0000 0000

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

Output), Gain = 2

REFIN

11(00)

01(00)

00(00)

11(00)

01(00)

00(00)

+2 (V

+2 (V

+2 (V

+2 (V

+2 (V

OUTPUT

1023

)

REFIN

1024

513

)

REFIN

1024

512

)

REFIN

1024

511

)

REFIN

1024

)

REFIN

1024

OV

= +V

REFIN

1

Table 5. Bipolar (Offset Binary) Code

)(G),

Table (-V

INPUT*

1111 1111

1000 0000

1000 0000

0111 1111

0000 0000

0000 0000

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

REFIN

11(00)

01(00)

00(00)

11(00)

01(00)

00(00)

to +V

REFIN

(+V

(+V

(-V

(-V

(-V

Output)

OUTPUT

511

)

REFIN

512

1

)

REFIN

512

0V

1

)

REFIN

512

511

)

REFIN

512

512

)

REFIN

512

= -V



REFIN

14 ______________________________________________________________________________________

5V, Low-Power, Parallel-Input,

Voltage-Output, 10-Bit DAC

REFGND

AGND

DGND

+5V

V

DD

REFIN

ROFS

MAX503

V

-5V

RFB

VOUT

SS

AC Considerations

Digital Feedthrough

Analog Feedthrough

+5V

REFIN
REFOUT

33µF

MAX503

AGND
DGND

REFGND

Figure 11. Bipolar Configuration (-2.048V to +2.048V Output) Figure 12. Four-Quadrant Multiplying Circuit

__________Applications Information

As with any amplifier, the MAX503’s output op amp off­set can be positive or negative. When the offset is posi­tive, it is easily accounted for. However, when the offset
is negative, the output cannot follow linearly when there
is no negative supply. In that case, the amplifier output
(VOUT) remains at ground until the DAC voltage is suffi­cient to overcome the offset and the output becomes
positive. The resulting transfer function is shown in

ROFS

RFB

V

VOUT

-5V

OUT

Single-Supply Linearity

ground connection may be achieved by connecting
the AGND, REFGND, and DGND pins together and
connecting that point to the system analog ground
plane. If DGND is connected to the system digital
ground, digital noise may get through to the DAC’s ana­log portion.

Bypass V

(and VSSin dual-supply mode) with a

DD

0.1µF ceramic capacitor connected between VDDand
AGND (and between VSSand AGND). Mount the
capacitors with short leads close to the device.

Figure 13.
Normally, linearity is measured after allowing for zero

error and gain error. Since, in single-supply operation,
the actual value of a negative offset is unknown, it can­not be accounted for during test. In the MAX503, linear­ity and gain error are measured from code 3 to code
1023 (see Note 2 under

Electrical Characteristics

). The
output amplifier offset does not affect monotonicity, and
these DACs are guaranteed monotonic starting with
code zero. In dual-supply operation, linearity and gain

High-speed data at any of the digital input pins may
couple through the DAC package and cause internal
stray capacitance to appear as noise at the DAC out­put, even though LDAC and CS are held high (see

Typical Operating Characteristics

feedthrough is tested by holding LDAC and CS high
and toggling the data inputs from all 1s to all 0s.

error are measured from code 0 to 1023.

Power-Supply Bypassing

and Ground Management

Best system performance is obtained with printed cir­cuit boards that use separate analog and digital ground
planes. Wire-wrap boards are not recommended. The
two ground planes should be connected together at the
low-impedance power-supply source.

Because of internal stray capacitance, higher-frequen­cy analog input signals at REFIN may couple to the
output, even when the input digital code is all 0s, as
shown in the

Typical Operating Characteristics

Analog Feedthrough vs. Frequency. It is tested by set­ting CLR to low (which sets the DAC latches to all 0s)
and sweeping REFIN.

AGND and REFGND should be connected together,
and then to DGND at the chip. For single-supply appli­cations, connect VSSto AGND at the chip. The best

REFIN

V

OUT

). This digital

graph

MAX503

______________________________________________________________________________________ 15

5V, Low-Power, Parallel-Input,
Voltage-Output, 10-Bit DAC

5

MAX503

Figure 13. Single-Supply DAC Transfer Function

4

3

2

OUTPUT (LSBs)

1

0

12345

DAC CODE (LSBs)

POSITIVE OFFSET

NEGATIVE OFFSET

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

© 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.