The MAX498/MAX499 are high-speed, quad/triple, single-pole/double-throw video switches with on-board
closed-loop buffer amplifiers. The buffer amplifiers feature +6dB gain (A
= 2V/V), 250MHz -3dB band-
VCL
width, 70MHz 0.1dB gain flatness, and 1250V/µs slew
rate. Fast switching time (3ns) and fast settling time
(12ns for a 4V step) make these devices excellent
choices for a wide variety of video applications. The low
differential gain/phase errors (0.03%/0.06°) and wide
bandwidth make them ideal for both composite-video
and RGB applications. The amplifiers are capable of
delivering ±2.5V into back-terminated 50Ω or 75Ω
cables, and they deliver ±2V to a 75Ω load, allowing
multiple cables to be driven from a single output.
For implementation of large switch arrays, a low-power
disable mode places the amplifier outputs in a highimpedance state. Channel selection and output
enable/disable are controlled by four TTL/CMOScompatible logic inputs. Each video input is isolated by
an AC-ground pin, which minimizes channel-to-channel
capacitance and reduces crosstalk to 90dB at 10MHz.
The four-channel MAX498 dissipates 390mW (typical)
from ±5VDC power supplies with all output buffers
enabled. Power consumption is reduced to 130mW with
all buffers disabled. The corresponding dissipation for
the three-channel MAX499 is 300mW enabled and
100mW disabled.
________________________Applications
Video Switching and Routing
Broadcast-Quality Composite-Video Multiplexing
Workstations
Video Editing
Broadcast and High-Definition TV Systems
Multimedia Products
Medical Imaging
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCCto VEE)................................................+12V
Voltage on IN__ to GND..................(V
Voltage on Digital Inputs
(LE, EN, A0, CS).........................................-0.3V to (V
Voltage on OUT_ (disabled)..................................................±4V
Output Short-Circuit Duration
to -4V ≤ OUT_ ≤ +4V ..................................................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
- 0.3V) to (VCC+ 0.3V)
EE
CC
+ 0.3V)
Continuous Power Dissipation (T
24-Pin SO (derate 11.76mW/°C above +70°C).............941mW
28-Pin SO (derate 12.5mW/°C above +70°C)......................1W
Operating Temperature Range .................................0°C to +70°
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
DC ELECTRICAL CHARACTERISTICS
(VCC= +5V, VEE= -5V, VIN__ = 0V, RL= 150Ω, LE = EN = CS = 0V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
= +25°C.)
T
A
MAX498/MAX499
Input Voltage Range
Voltage Gain
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Resistance
Input Capacitance
Output Short-Circuit Current
Output Current±27±40
On Output Resistance
Negative Power-Supply
Rejection
Logic Low Voltage
Logic High Voltage
Logic Input Current
= 0V, RL= 100Ω, LE = EN = CS = 0V, TA= +25°C, unless otherwise noted.)
IN__
CONDITIONS
VIN≤ 100mVp-pMHz250BW
-3dB
VIN≤ 100mVp-pMHz70±0.1dB Gain Flatness
V
= ±2VMHz135FPBWFull-Power, -3dB Bandwidth
OUT
V
= 4V stepV/µs1250SRSlew Rate
OUT
0.1%, V
s
f = 100kHz
f = 100kHz
f = 10MHz
fC= 3MHz
f = 10MHz (Note 2)
f = 10MHz (Note 3)
EN = 1, f = 10MHz (Note 4)
f = 3.58MHz (Note 5), RL= 150Ω
f = 3.58MHz (Note 5), RL= 150Ω
A0/EN to CS Setup Time
A0/EN to CS Hold Time
CS Pulse Width
Channel-Switching
Propagation Delay
Channel-Switching Time
Channel-Switching Transient
Enable/Disable Switching
Transient
Amplifier-Disable Time
Amplifier-Enable Time
Note 2: Test-channel input grounded through a 50Ω resistor. Adjacent channel driven to a 2Vp-p output with a 10MHz sine wave
Note 3: Same as Note 2, except all channels but the test channel are driven to a 2Vp-p output with a 10MHz sine wave (Figure 9).
Note 4: Test-channel input connected to a 2V
Note 5: Input test signal is a 3.58MHz sine wave of 40IRE amplitude, superimposed on a 0IRE to 100IRE linear ramp (Figure 10).
Note 6: Guaranteed by design.
Note 7: V
Note 8: V
Note 9: Delay from EN to 90% of V
Note 10: Delay from EN to 10% of V
(Figure 9).
disabled (Figure 9).
= +1V, V
INA
= +1V, V
INA
= 0V, RL= 150Ω, LE = EN = CS = 0V, TA= 0°C to +70°C. Typical values are at TA= +25°C, unless
IN_ _
CONDITIONS
LE = high (Note 6)
SU
LE = high (Note 6)
H
(Note 6)
CS
(Note 7)
PD
(Note 8)
SW
V
INA
V
INA
(Note 9)16nst
OFF
(Note 10)24nst
ON
p-p
= -1V, delay from CS to 10% of V
INB
= -1V, delay from CS to 10% of V
INB
OUT.
OUT.
= V
= 0V
INB
= V
= 0V
INB
sine wave at 10MHz. The test channel’s output is measured with the outputs
2IN1ASignal Input 1, Channel A
4IN2ASignal Input 2, Channel A
6IN3ASignal Input 3, Channel A
6, 18
8IN0BSignal Input 0, Channel B
7, 17
10
12
13, 15
14
16
19
20
21
22
23
NAMEFUNCTION
GND
1
3
5
—
8
—
—
Analog Ground. All ground pins are internally connected. Connect all ground pins externally to
ground to minimize impedance.
Positive Power-Supply Voltage. Connect VCCto +5V. VCCpins are internally connected.
Connect both pins externally to +5V to minimize supply impedance. Bypass each pin to
CC
ground with a 0.1µF ceramic capacitor.
Negative Power-Supply Voltage. Connect VEEto -5V. VEEpins are internally connected.
Connect both pins to -5V externally to minimize supply impedance. Bypass each pin to
EE
ground with a 0.1µF ceramic capacitor.
Chip-Select Input. When CS is low, the A0 and EN latches are transparent. The data present at A0
CS
is latched when CS goes high. LE’s status determines whether EN is latched along with A0, or if the
EN latch remains transparent independently of CS.
Address Input. A0 = 0 selects channel A, and A0 = 1 selects channel B if CS is low. A0 is
latched on CS’s low-to-high transition.
Output Buffer-Enable Input. EN = 0 enables the output buffer amplifiers, and EN = 1 disables
EN
the output buffers if CS is low. EN is latched during CS’s low-to-high transition if LE is high. EN
is not latched if LE is low.
Latch-Enable Input. With LE = 1, EN is latched along with A0 when CS goes high. When LE = 0,
the EN latch is transparent independently of CS’s state.
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
______________ Detailed Description
The MAX498/MAX499 are quad/triple video switches
with high-speed, closed-loop, voltage-feedback amplifiers set to a 2V/V gain. Figure 1 shows typical application circuits. The amplifiers use a unique two-stage,
voltage-feedback architecture that combines the benefits of conventional voltage-feedback and currentfeedback topologies to achieve wide bandwidths and
high slew rates while maintaining precision.
Figure 2 is a simplified block diagram of the MAX498/
MAX499. All four amplifier/switch blocks are identical to
that shown for Ch_0. A common control logic block
accepts external logic inputs A0, EN, CS, and LE,
and controls the status of switches S1, S2, and S3 of
each amplifier in parallel, as described in the
Interface
MAX498/MAX499
section.
S3 is open in the enabled state, and if Ch_A is selected, S1 is connected to IN_A and S2 is connected to
GND. If Ch_B is selected, S1 is connected to GND and
S2 is connected to IN_B. Connecting the deselected
GM_ block to GND ensures minimum feedthrough.
S3 is closed in the disabled state, and both S1 and S2
are connected to GND. Disconnecting both inputs and
connecting the amplifier’s inputs to GND significantly
improves off-isolation.
__________Applications Information
The MAX498/MAX499’s maximum output current is limited by the package’s maximum allowable power dissipation. The maximum junction temperature should not
exceed +150°C. Power dissipation increases with load,
and this increase can be approximated by one of the
following equations:
For V
For V
OUT
OUT
> 0V: |V
< 0V: |V
CC
EE
These devices can drive 100Ω loads connected to
each of the outputs over the entire rated output swing
and temperature range. While the output is short-circuit
protected to 120mA, this does not necessarily guarantee that under all conditions, the maximum junction
temperature will not be exceeded. Do not exceed the
derating values given in the
section.
Power Dissipation
- V
OUT|ILOAD
OR
- V
OUT|ILOAD
.
Absolute Maximum Ratings
Digital
IN0A
S1
C
IN0B
S2
R
G
S1S2S3
A0
EN
CS
LE
Figure 2. Block Diagram
The MAX498/MAX499’s low 2.6pA/√Hz input current
noise and 7.8nV/√Hz voltage noise provide for lower
total noise compared to typical current-mode feedback
amplifiers, which usually have significantly higher input
current noise. The input current noise multiplied by the
feedback resistor is the dominant noise source of current-mode feedback amplifiers.
Differential Gain and Phase Errors
Differential gain and phase errors are critical specifications for a buffer in composite (NTSC, PAL, SECAM) video
applications, because these errors correspond directly to
color changes in the displayed picture of composite video
systems. The MAX498/MAX499’s low differential gain and
phase errors (0.03%/0.06°) make them ideal in broadcastquality, composite video applications.
Figure 3a. Small-Signal Gain vs. Frequency and Load
Capacitor (R
V
VOLTAGE (V)
= 100Ω, R
L
+1
V
IN
-1
+2
OUT
-2
ISO
= 0Ω)
MAX498/MAX499
FULL POWER-DOWN
14
R
= 6.8Ω
ISO
12
10
8
6
4
GAIN (dB)
2
0
-2
-4
-6
150pF
1M
10M1G
FREQUENCY (Hz)
100pF
47pF
0pF
100M
Figure 3b. Small-Signal Gain vs. Frequency and Load
Capacitor (R
= 100Ω, R
L
+100
V
IN
-100
+200
V
OUT
VOLTAGE (mV)
-200
ISO
= 6.8Ω)
TIME (10ns/div)
Figure 4a. Large-Signal Pulse Response with CL= 100pF and
= 5.1Ω
R
ISO
Coaxial Cable Drivers
High-speed performance, excellent output current
capability, and an internally fixed gain of +2 make the
MAX498/MAX499 ideal for driving back-terminated 50Ω
or 75Ω coaxial cables to ±2.5V.
In a typical application, the MAX498/MAX499 drive a
back-terminated cable (Figure 1). The back-termination
resistor, at the output, matches the impedance of the
cable’s driven end to the cable’s impedance, eliminating
signal reflections. This resistor, along with the loadtermination resistor, forms a voltage divider with the load
impedance, which attenuates the signal at the cable’s
output by one-half. The MAX498/MAX499 operate with
an internal +2V/V closed-loop gain to provide unity gain
at the cable’s output.
Figure 4b. Small-Signal Pulse Response with CL= 100pF and
= 5.1Ω
R
ISO
Capacitive-Load Driving
In most amplifier circuits, driving large capacitive loads
increases the likelihood of oscillation. This is especially
true for circuits with high loop gains, such as voltage
followers. The amplifier’s output resistance and the
capacitive load form an RC filter that adds a pole to the
loop response. If the pole frequency is low enough (as
when driving a large capacitive load), the circuit-phase
margin is degraded and oscillation may occur.
The MAX498/MAX499 drive capacitive loads up to
100pF without sustained oscillation, although some
peaking may occur (Figures 3a and 3b). When driving
larger capacitive loads, or to reduce peaking, add an
isolation resistor (R
) between the output and the
ISO
capacitive load (Figures 4a, 4b, and 5).
Quad/Triple, SPDT, RGB Switches
MAX186/MAX188
COMPARATOR INPUT BIAS CURRENT
with 250MHz Video Buffer Amplifiers
8
7
6
5
4
ISOLATION RESISTOR (Ω)
3
2
MAX498/MAX499
Figure 5. Isolation Resistor vs. Capacitive Load
vs. SUPPLY VOLTAGE
47
100 150 200 270 390 510
CAPACITANCE (pF)
Switching Audio Signals
(Audio-Distortion Measurement)
When switching audio signals, distortion is the prime
consideration in performance. Figure 6 shows total
harmonic distortion vs. frequency, in the audio range,
for the MAX498/MAX499.
Large Switch Arrays
Large crosspoint switch arrays are possible with the
MAX498/MAX499 using the enable function EN. When
the amplifiers are disabled, output impedance is typically 1.2kΩ, due to the feedback and gain resistors.
This limits the number of outputs that can be paralleled
without a buffer. Since each output can drive 100Ω,
eight outputs can typically be connected together. If
additional outputs must be connected in parallel, a
MAX4178 (single), MAX496 (quad), or equivalent unitygain buffer can be used.
Whether enabled or disabled, each input represents
more than 200kΩ of resistance. Capacitance is the
prime consideration limiting the number of inputs that
can be connected to a single output. Since each output
can drive 100pF of capacitance without an isolation
resistor, 50 inputs (CIN= 2pF, typical) can be driven
by a single output. However, peaking will occur as
inputs are added (Figure 3), which reduces the 0.1dB
bandwidth.
1k
10
FULL POWER-DOWN
10010k
FREQUENCY (Hz)
-82
-84
-86
-88
-90
-92
DISTORTION (dBc)
-94
-96
-98
Figure 6. Total Harmonic Distortion (Audio) vs. Frequency
Digital Interface
The MAX498/MAX499 multiplexer architecture ensures
that no input channels are ever connected together.
Select a channel by changing A0’s state (A0 = 0 for
channel A, and A0 = 1 for channel B) and pulsing CS low
(see Tables 1a and 1b). Figure 7 shows the logic timing
diagram.
When the enable input (E—N–) is driven to a TTL low state, it
enables the MAX498/MAX499 amplifier outputs. When E—N
is driven high, it disables the amplifier outputs. When
disabled, the MAX498/MAX499 exhibit a 1.2kΩ disabled output resistance due to their internal feedback
resistors.
LE determines whether E—N–is latched by CS or operates
independently. When the latch-enable input (LE) is connected to V+, CS becomes the latch control for the E—N
input register. If CS is low, both the E—N–and A0 latches
are transparent; once CS returns high, both A0 and E—N
are latched.
When LE is connected to ground, the E—N–latch is transparent and independent of CS. This allows all
MAX498/MAX499 devices to be shut down simultaneously, regardless of CS’s input state. Simply connect
LE to ground and connect all E—N–inputs together
(Figure 8a). Hard wire LE to V+ or ground (rather than
driving LE with a gate) to prevent crosstalk from the
digital inputs to IN0A.
Another option for output disable is to connect LE to V+,
parallel the outputs of several MAX498/MAX499s, and use
E—N–to individually disable all devices but the one in use
(Figure 8b).
When the outputs are disabled, off-isolation from the
analog inputs to the amplifier outputs is typically 81dB
at 10MHz.
Grounding and Layout
The MAX498/MAX499 bandwidths are in the RF frequency range. Depending on the size of the PC board
used and the frequency of operation, it may be necessary to use Micro-strip or Stripline techniques.
To realize the full AC performance of these high-speed
buffers, pay careful attention to power-supply bypassing
and board layout. The PC board should have at least two
layers (wire-wrap boards are too inductive, and bread
boards are too capacitive), with one side a signal layer
and the other a large, low-impedance ground plane. With
multilayer boards, locate the ground plane on the layer
that is not dedicated to a specific signal trace. The ground
plane should be as free from voids as possible. Connect
all ground pins to the ground plane.
Connect both positive power-supply pins together and
bypass with a 0.10µF ceramic capacitor at each powersupply pin, as close to the device as possible. Repeat
for the negative power-supply pins. The capacitor lead
lengths should be as short as possible to minimize lead
inductance; surface-mount chip capacitors are ideal. A
large-value (10µF or greater) tantalum or electrolytic
bypass capacitor on each supply may be required for
high-current loads. The location of this capacitor is not
critical.
The MAX498/MAX499’s analog input pins are isolated
with ground pins to minimize parasitic coupling, which can
degrade crosstalk and/or amplifier stability. Keep signal
paths as short as possible to minimize inductance. Ensure
that all input channel traces are the same length, to maintain the phase relationship between the four channels. To
further reduce crosstalk, connect the coaxial-cable shield
to the ground side of the 75Ω terminating resistor at the
ground plane, and terminate all unused inputs to ground
and outputs with a 100Ωor 150Ω resistor to ground.
Table 1a. Amplifier and Channel
Selection with LE = V+
A0
Enables amplifier outputs. Selects
000
channel A.
Enables amplifier outputs. Selects
100
channel B.
Disables amplifiers. Outputs high-Z.X10
XX1
Latches A0, EN. Outputs unchanged.
FUNCTION
Table 1b. Amplifier and Channel
Selection with LE = GND
FUNCTION
Enables amplifier outputs. Selects
000
channel A.
Enables amplifier outputs. Latches A0
to output A or B, according to A0’s
X01
state at C—S–’s last edge.
Disables amplifiers. Outputs high-Z.
X1X
A0 latch = channel A.
Enables amplifier outputs. Selects
Quad/Triple, SPDT, RGB Switches
with 250MHz Video Buffer Amplifiers
____Pin Configurations (continued)___________________Chip Information
TOP VIEW
GND
1
IN1A
2
GND
3
IN2A
4
GND
IN3A
V
CC
IN0B
V
EE
MAX498/MAX499
IN1B
GND
IN2B
GND
IN3B
MAX498
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IN0A
LE
EN
A0
CS
OUT0
V
CC
V
EE
OUT1
GND
OUT2
N.C.
OUT3
N.C.
SUBSTRATE CONNECTED TO: V
TRANSISTOR COUNT: 813
SO
________________________________________________________Package Information
DIM
D
A
0.101mm
e
B
A1
0.004in.
C
0°- 8°
L
A
A1
B
C
E
e
H
L
EE
INCHESMILLIMETERS
MAX
MIN
0.093
0.004
0.014
0.009
0.291
0.394
0.016
0.050
0.104
0.012
0.019
0.013
0.299
0.419
0.050
MIN
2.35
0.10
0.35
0.23
7.40
10.00
0.40
1.27
MAX
2.65
0.30
0.49
0.32
7.60
10.65
1.27
DIM
HE
Wide SO
SMALL-OUTLINE
PACKAGE
(0.300 in.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600