MAXIM MAX4929E User Manual

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General Description
The MAX4929E low-frequency 2:1 switch is ideal for HDMI™/DVI™ switching applications. The device fea­tures a voltage clamp function to protect low-voltage systems at the output. The MAX4929E operates with a single 5V supply or dual or triple supplies. The MAX4929E provides clamping and voltage translation without additional components. All external inputs/out­puts are electrostatic-discharge (ESD)-protected to ±6kV Human Body Model (HBM).
The MAX4929E is available in 20-pin QSOP and 20-pin, 4mm x 4mm, TQFN packages. The device is specified for the extended -40°C to +85°C operating temperature range.
Applications
HD Television Receivers
HD Monitors
High-Resolution Computer Monitors
Features
o DDC Switches
Low 20pF (typ) Capacitance
o Protects EDID (Extended Display Identification
Data) EPROM or MCU from Excess Voltage
o Hot-Plug Detect Signal
Translates MCU Voltage to TTL Levels
o Two Devices Can Be Used to Form a 4:1 Switch
No Added Active Components Needed
o ±6kV ESD Protection HBM on All External I/Os
o Available in Lead-Free, 20-Pin TQFN or 20-Pin QSOP
Packages
MAX4929E
HDMI 2:1 Low-Frequency Translating Switch
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
HIZ1
HIZ2
CLP
SCLO
SDAO
V
DD
HPDHPIRO SEL
V+
+5V
MCU
EDID
EPROM
2kΩ
HPIR1 SCL1 SDA1 HPDO1
TMDS1
HPIR2 SCL2 SDA2 HPDO2
TMDS1
GND
SEL
HPIRO
HPD
VL
HDMI1
HDMI2
V
DD
2kΩ
+3.3V TO +5V
+2V to +3.3V
0.1μF
0.1μF
MAX4929E
0.1μF
EXESD
0.1μF
Typical Operating Circuit
19-0860; Rev 0; 10/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead-free package
*
EP = Exposed paddle.
Pin Configurations continued at end of data sheet.
19
20
18
17
7
6
8
SCL2
SDA1
9
SDA2
HPD
SDAO
SCLO
HIZ2
1 2
EXESD
45
15 14 12 11
HPDO2
HPIR2
*EP
VL
CLP
V+
SCL1
MAX4929E
HPDO1
HPIRO
3
13
GND
16
10
SEL
HIZ1
TQFN
(4mm x 4mm)
TOP VIEW
*EXPOSED PADDLE CONNECTED TO GND OR LEAVE EP UNCONNECTED
HPIR1
Pin Configurations
HDMI is a trademark of HDMI Licensing, LLC. DVI is a trademark of Digital Display Working Group (DDWG).
PART TEMP RANGE
PIN­PACKAGE
MAX4929EEEP+ -40°C to +85°C 20 QSOP E20-1
MAX4929EETP+ -40°C to +85°C 20 TQFN-EP* T2044-3
PKG
CODE
MAX4929E
HDMI 2:1 Low-Frequency Translating Switch
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V+ = +5V ±10%, CLP = VL = +3.3V ±10%, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND, unless otherwise noted.)
V+ ............................................................................-0.3V to +6V
All Pins (except GND) .............................................-0.3V to +6V
Continuous Current into Any I/O Terminal .........................25mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin QSOP (derate 9.1mW/°C above +70°C) ..........727mW
20-Pin TQFN (derate 16.9mW/°C above +70°C) ......1356mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
),
)
),
)
)
),
)
),
)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
V+ Supply Current I+ V+ = 5.5V, VL = CLP = 3.6V 3 8 µA
V+ Supply Current I+ V+ = 0V, VL = CLP = 0V, V
VL Supply Current I
CLP Supply Current I
VL
CLP
ANALOG SWITCH
R
On-Resistance
On-Resistance Match Between Channels
On-Resistance Flatness R
Off-Leakage Current
On-Leakage Current
Output Clamped Voltage
ON(SCL_
R
ON(SDA_
ΔR
ON
FLAT
I
SCL_(OFF
I
SDA_(OFF
I
SCL_(ON),
I
SDA_(ON
V
OV C ( S C L O) ,
V
OV C ( S D A O)
SWITCH DYNAMIC CHARACTERISTICS
C
SCL_, SDA_ Off-Capacitance
SCL_, SDA_ On-Capacitance
SCL_(OFF
C
SDA_(OFF
C
SCL_(ON
C
SDA_(ON
Bandwidth BW RS = RL = 50Ω, CL = 10pF 40 MHz
Crosstalk V
Off-Isolation V
CT
ISO
LOGIC INPUT (HPIR1, HPIR2)
Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Logic Leakage I
IL
IH
INL
V+ = 5.5V, VL = CLP = 3.6V 1 µA
V+ = 5.5V, VL = CLP = 3.6V 1 µA
V+ = 4.5V, CLP = 3V, V
1.5V; I
SCL_
V+ = 4.5V, CLP = 3V, V
1.5V; I
SCL_
V+ = 4.5V, CLP = 3V, V
1.5V; I
SCL_
V+ = 5.5V, V HIZ1 = HIZ2 = 0V or VL (Note 1)
V+ = 5.5V, V (Note 1)
V+ = 5V, CLP = 3.3V, VL = 5V, RP = 1kΩ (Note 2)
V+ = 5V, TA = +25°C, Figure 1 20 pF
V+ = 5V, TA = +25°C, Figure 1 30 pF
RS = RL = 50Ω, f = 1MHz, Figure 2 (Note 3) -75 dB
RS = RL = 50Ω, f = 1MHz, Figure 2 (Note 4) -70 dB
V+ = 4.5V 0.8 V
V+ = 5.5V 3.8 V
= +5.5V 200 µA
HPIR_
or I
or I
or I
SCL_
SCL_
SDA_
SDA_
SDA_
or V
or V
SCL_
= ±10mA
SCL_
= ±10mA
SCL_
= ±10mA
= 0V, 5.5V;
SDA_
= 0V, 5.5V
SDA_
or V
or V
or V
SDA_
SDA_
SDA_
= 0 to
= 0 to
= 0 to
10 25 Ω
28Ω
13 Ω
-5 +5 µA
-5 +5 µA
3.3 V
0.01 1 µA
MAX4929E
HDMI 2:1 Low-Frequency Translating Switch
_______________________________________________________________________________________ 3
)
)
)
)
)
)
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +5V ±10%, CLP = VL = +3.3V ±10%, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Leakage measured at SCLO or SDAO with SCL_ and SDA_ open. Note 2: Pullup resistor of R
P
= 1kΩ at SCLO and SDAO. These resistors are necessary for the clamp/translation to operate correctly.
Note 3: Crosstalk is measured between any two analog inputs, crosstalk = 20log(V
OUT
/ VIN).
Note 4: Off-isolation = 20log10 (V
SCLO
/ V
SCL_
), V
SCLO
= output, V
SCL_
= input to off switch.
Note 5: Referenced to GND. Note 6: Any combination of pin to any other pin.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC INPUT (SEL, HPD, HIZ1, HIZ2)
Input Logic-Low Voltage V
Input Logic-High Voltage V
Hysteresis V
Input Logic-Leakage Current I
IL
IH
HYST
INL
LOGIC OUTPUT (HPDO1, HPDO2, HPIRO)
H P D O _ O utp ut Log i c- Low V ol tag eV
H P D O_ Outp ut Log i c- H i g h V ol tag eV
H P IRO O utp ut Log i c- Low V ol tag eV
H P IRO O utp ut Log i c- H i g h V ol tag eV
Output-Logic Leakage Current I
OL(HPDO_
OH(HPDO_
OL(HPIRO
OH(HPIRO
O
TIMING CHARACTERISTICS
t
PD(HPDO_
Logic Delay
t
PD(HPIRO
ESD PROTECTION
ESD Protection, Human Body Model
EXESD Leakage Current 1.0 µA
V+ = 4.5V, VL = CLP = 3V 0.8 V
V+ = 5.5V, VL = CLP = 3.6V 2.0 V
3V VL = CLP 3.6V 150 mV
0.01 1 µA
V+ = 4.5V, VL = CLP = 3.0V, I
V + = 4.5V , V L = C LP = 3.0V , I
V+ = 4.5V, VL = CLP = 3.0V, I
V + = 4.5V , V L = C LP = 3.0V , I
= 4mA 0.5 V
SINK
S OU RC E
S OU RC E
= 4m A 4.0 V
= 2mA 0.5 V
SINK
= 2m A 2.5 V
HIZ1 = HIZ2 = 0V or VL 1 µA
V+ = 4.5V, VL = CLP = 3.0V, CL = 15pF, SEL = 0V or VL (Figure 3)
V+ = 4.5V, VL = CLP = 3.0V, CL = 15pF, (SEL = 0V or VL (Figure 3)
HPIR1, HPIR2, HPDO1, HPDO2, SCL1, SCL2, SDA1, SDA2 (Note 5)
HPIRO, HPD, SEL, SCLO, SDAO, HIZ1, HIZ2 (Note 6)
33
33
±6
±2
ns
kV
MAX4929E
HDMI 2:1 Low-Frequency Translating Switch
4 _______________________________________________________________________________________
Test Circuits/Timing Diagrams
Figure 1. Channel Off-/On-Capacitance
Figure 2. On-Loss, Off-Isolation, and Crosstalk
Figure 3. Logic Delay Timing
+5V
0.1μF
+3.3V
0.1μF 0.1μF
0V OR VL
50Ω
SEL
SDA1/ SCL1
HIZ1
VL
HIZ2
CAPACITANCE
+5V+3.3V
V+VLCLP
MAX4929E
GND
METER
f = 1MHz
SDAO/
SDA2/ SCL2*
SCLO
V
IN
V
OUT
V+
SDAO/SCLO
SDA_/ SCL_
GND
MAX4929E
NETWORK ANALYZER
50Ω
MEAS REF
50Ω 50Ω
CLP
SEL
HIZ1 HIZ2
VL
0.1μF
OR V
V
IL
IH
VL
V
OUT
V
IN
V
OUT
V
IN
V
OUT
V
IN
50Ω
OFF-ISOLATION = 20log
ON-LOSS = 20log
CROSSTALK = 20log
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN SDAO/SCLO AND "OFF" SDA_/SCL_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN SDAO/SCLO AND "ON" SDA_/SCL_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
*FOR CROSSTALK THIS PIN IS SCL2. SCL1 AND SCL0 ARE OPEN.
tr < 5ns tf < 5ns
0UT
HPD
HPIR_
HPDO_
HPIRO
V+ or V
0V
0V
L
50%
V
OUT
0.9 x V
t
PD(HPDO)
t
PD(HPIRO)
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