The single MAX473, dual MAX474, and quad MAX475
are single-supply (2.7V to 5.25V), unity-gain-stable op
amps with rail-to-rail output swing. Each op amp guarantees a 10MHz unity-gain bandwidth, 15V/µs slew
rate, and 600Ω drive capability while typically consuming only 2mA supply current. In addition, the input
range includes the negative supply rail and the output
swings to within 50mV of each supply rail.
Single-supply operation makes these devices ideal for
low-power and low-voltage portable applications. With
their fast slew rate and settling time, they can replace
higher-current op amps in large-signal applications.
The MAX473/MAX474/MAX475 are available in DIP and
SO packages in the industry-standard op-amp pin
configurations. The MAX473 and MAX474 are also
offered in the µMAX package, the smallest 8-pin SO.
________________________Applications
Portable Equipment
Battery-Powered Instruments
Signal Processing
Discrete Filters
Signal Conditioning
Servo-Loops
__________Typical Operating Circuit
____________________________Features
♦ 15V/µs Min Slew Rate
♦ +3V Single-Supply Operation
♦ Guaranteed 10MHz Unity-Gain Bandwidth
♦ 2mA Supply Current per Amplifier
♦ Input Range Includes Negative Rail
♦ Outputs Short-Circuit Protected
♦ Rail-to-Rail Output Swing (to within ±50mV)
♦ µMAX Package (the smallest 8-pin SO)
______________Ordering Information
PART
MAX473CPA
MAX473CSA
MAX473CUA0°C to +70°C8 µMAX
MAX473C/D0°C to +70°C
MAX473EPA-40°C to +85°C8 Plastic DIP
MAX473ESA-40°C to +85°C8 SO
MAX473MJA-55°C to +125°C8 CERDIP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
= +70°C)
A
to (V
CC
EE
+ 0.3V)
- 0.3V)
ELECTRICAL CHARACTERISTICS
(+3V ≤ VCC≤ +5V, VEE= 0V, VCM= 0.5V, V
Input Offset Voltage±0.70±2.0
Input Bias Current
MAX473/MAX474/MAX475
Input Offset Current
Common-Mode Voltage
Input Noise-Voltage Density
Large-Signal Gain
(Note 1)
Output Voltage
Unity-Gain Bandwidth
(Note 2)
V
V
A
V
GBW
= 0.5V, TA= +25°C, unless otherwise noted.)
OUT
CONDITIONSUNITSMINTYPMAXSYMBOLPARAMETER
MAX473
MAX474
OS
MAX475
Current flows out of terminals
B
OS
High
CM
Low
VEE≤ VCM≤ (VCC- 1.9V)
VCC= 2.7V to 6.0V
f = 10kHz
Offset Null Input. Connect to one end of 2kΩ potentiometer for offset voltage
trimming. Connect wiper to VEE. See Figure 1.
Amplifier A Output1—
Inverting Input—2
Amplifier A Inverting Input2—
Noninverting Input—3
Amplifier A Noninverting Input3—
Negative Power-Supply Pin. Connect to ground or a negative voltage.44
No Connect—not internally connected—5
Amplifier B Noninverting Input5—
Amplifier Output —6
Amplifier B Inverting Input6—
Amplifier B Output7—
Positive Power-Supply Pin. Connect to (+) terminal of power supply.87
Amplifier C OutputOUTC8——
Amplifier C Inverting InputINC-9——
Amplifier C Noninverting InputINC+10——
Amplifier D Noninverting InputIND+12——
Amplifier D Inverting InputIND-13——
Amplifier D OutputOUTD14——
MAX473/MAX474/MAX475
__________Applications Information
Power Supplies
The MAX473/MAX474/MAX475 operate from a single
2.7V to 5.25V power supply, or from dual supplies of
±1.35V to ±2.625V. For single-supply operation,
bypass the power supply with 0.1µF. If operating from
dual supplies, bypass each supply to ground. With
0.1µF bypass capacitance, channel separation
(MAX474/MAX475) is typically better than 120dB with
signal frequencies up to 300kHz. Increasing the
bypass capacitance (e.g. 10µF || 0.1µF) maintains
channel separation at higher frequencies.
Minimizing Offsets
The MAX473’s maximum offset voltage is ±2mV
(TA= +25°C). If additional offset adjustment is required,
connect a 2kΩ trim potentiometer between pins 1, 8, and
4 (Figure 1). Input offset voltage for the dual MAX474
and quad MAX475 cannot be externally trimmed.
The MAX473/MAX474/MAX475 are bipolar op amps
with low input bias currents. The bias currents at both
inputs flow out of the device. Matching the resistance
at the op amp’s inputs significantly reduces the offset
error caused by the bias currents. Place a resistor (R3)
from the noninverting input to ground when using the
inverting configuration (Figure 2a); place R3 in series
with the noninverting input when using the noninverting
configuration (Figure 2b). Select R3 such that the parallel combination of R2 and R1 equals R3. Adding R3 will
slightly increase the op amp’s voltage noise.
Output Loading and Stability
The MAX473/MAX474/MAX475 op amps are unity-gain
stable. Any op amp’s stability depends on the configuration, closed-loop gain, and load capacitance. The
unity-gain, noninverting buffer is the most sensitive gain
configuration, and driving capacitive loads decreases
stability.
Single/Dual/Quad, 10MHz
Single-Supply Op Amps
R2
2k
1
NULL
MAX473
4
V
EE
Figure 1. Offset Null Circuit
The MAX473/MAX474/MAX475 have excellent phase
MAX473/MAX474/MAX475
margin (the difference between 180° and the unity-gain
NULL
8
phase angle). It is typically 63° with a load of 10kΩ in
parallel with 20pF. Generally, higher phase margins
indicate greater stability.
Capacitive loads form an RC network with the op amp’s
output resistance, causing additional phase shift that
reduces the phase margin. Figure 3 shows the
MAX473/MAX474/MAX475 output response when driving a 390pF load in parallel with 10kΩ.
When driving large capacitive loads, add an output isolation resistor, as shown in Figure 4. This resistor
improves the phase margin by isolating the load
capacitance from the amplifier output. Figure 5 shows
the MAX473/MAX474/MAX475 driving a capacitive load
of 1000pF using the circuit of Figure 4.
Feedback Resistors
The feedback resistors appear as a resistance network
to the op amp’s feedback input (Figure 2). This resistance, combined with the op amp’s input and stray
capacitance (total input capacitance), forms a pole that
adds unwanted phase shift when either the total input
capacitance or feedback resistance is too large. For
example, using the noninverting configuration with a
gain of 10, if the total capacitance at the negative input
is 10pF and the effective resistance (R1 ||R2) is 9kΩ,
this RC network introduces a pole at fo= 1.8MHz. At
IN
V
IN
R3 = R2R1
R1
V
OUT
R3
R3 = R2R1
R3
V
OUT
R2
R1
, the pole introduces addi-
o
V
Figure 2a. Reducing Offset Error Due to Bias Current:
Inverting Configuration
Figure 2b. Reducing Offset Error Due to Bias Current:
Noninverting Configuration
input frequencies above f
tional phase shift, which reduces the overall bandwidth
and adversely affects stability. Choose feedback resistors small enough so they do not adversely affect the
op amp’s operation at the frequencies of interest.
Overdriving the Outputs
The output voltage swing for specified operation is from
(VEE+ 0.3V) to (VCC- 0.5V) (
see Electrical Characteristics
Exercising the outputs beyond these limits drives the output transistors toward saturation, resulting in bandwidth
degradation, response-time increase, and gain decrease
(which affects linearity). Operation in this region causes a
slight distortion in the output waveform, but does not
adversely affect the op amp.
The MAX473/MAX474/MAX475’s fast 15V/µs slew rate
maximizes full-power bandwidth (FPBW). The FPBW is
given by:
FPBW (Hz) = —————————————
π [V
SR
peak-to-peak(max)]
OUT
where the slew rate (SR) is 15V/µs min. Figure 6 shows
the full-power bandwidth as a function of the peak-topeak AC output voltage.
Figure 5. The MAX473 easily drives 1000pF using the
Capacitive-Load Driving Circuit (Figure 4).
100
SMALL-SIGNAL
10
1
FULL-POWER BANDWIDTH (MHz)
0.1
Figure 6. Full-Power Bandwidth vs. Peak-to-Peak AC Voltage
FULL-POWER
BANDWIDTH
01342
OUTPUT VOLTAGE SWING (Vp-p)
GAIN BANDWIDTH
MAX473-FIG6
Layout
A good layout improves performance by decreasing
the amount of stray capacitance at the amplifier’s
inputs and output. Since stray capacitance might be
unavoidable, minimize trace lengths and resistor leads,
and place external components as close to the pins as
possible.
MAX474CSA
MAX474CUA0°C to +70°C8 µMAX
MAX474C/D0°C to +70°C
MAX474EPA-40°C to +85°C8 Plastic DIP
MAX474ESA-40°C to +85°C8 SO
MAX474MJA-55°C to +125°C8 CERDIP
MAX475CPD
MAX475CSD0°C to +70°C14 SO
MAX475EPD-40°C to +85°C14 Plastic DIP
MAX475ESD-40°C to +85°C14 SO
MAX475MJD-55°C to +125°C14 CERDIP
* Dice are specified at TA= +25°C, DC parameters only.
TEMP. RANGEPIN-PACKAGE
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 SO
Dice*
0°C to +70°C14 Plastic DIP
____Pin Configurations (continued)
MAX473/MAX474/MAX475
TOP VIEW
OUTA
INAINA+
V
INB+
INB-
OUTB
1
2
A
3
CC
4
MAX475
5
B
6
7
OUTD
14
IND-
13
D
IND+
12
V
11
EE
INC+
10
C
INC-
9
OUTC
8
_________________Chip Topographies
MAX473
NULL
IN-
IN+
V
EE
0.052"
(1.321mm)
TRANSISTOR COUNT: 185
SUBSTRATE CONNECTED TO V
MAX474
V
CC
OUTA
INA-
INA+
EE
NULL
V
CC
0.065"
(1.651mm)
OUT
OUTB
INB-
0.084"
(2.134mm)
INB+
DIP/SO
VEE
0.058"
(1.473mm)
TRANSISTOR COUNT: 355
SUBSTRATE CONNECTED TO V
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
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