The MAX456 is the first monolithic CMOS 8 x 8 video
crosspoint switch that significantly reduces component
count, board space, and cost. The crosspoint switch
contains a digitally controlled matrix of 64 T-switches
that connect eight video input signals to any, or all, output channels. Each matrix output connects to eight
internal, high-speed (250V/µs), unity-gain-stable buffers
capable of driving 400Ω and 20pF to ±1.3V. For applications requiring increased drive capability, the
MAX456 outputs can be connected directly to two
MAX470 quad, gain-of-two video buffers, which are
capable of driving 75Ω loads.
Three-state output capability and internal, programmable active loads make it feasible to parallel multiple
MAX456s and form larger switch matrices.
In the 40-pin DIP package, crosstalk (70dB at 5MHz) is
minimized, and board area and complexity are simplified by using a straight-through pinout. The analog
inputs and outputs are on opposite sides, and each
channel is separated by a power-supply line or quiet
digital logic line.
________________________Applications
Video Test Equipment
Video Security Systems
Video Editing
________Typical Application Circuit
8 INPUT CHANNELS
MAX470
= 2
A
V
75Ω
WR
OUTPUT
SELECT
INPUT
SELECT
SERIAL
LATCH
MAX456
A2
A1
A0
8 X 8
T-SWITCH
MATRIX
D3
D2
OR
D1/SER OUT
D0/SER IN
I/O
AV = 2
MAX470
75Ω
____________________________Features
♦ Routes Any Input Channel to Any Output Channel
♦ Switches Standard Video Signals
♦ Serial or Parallel Digital Interface
♦ Expandable for Larger Switch Matrices
♦ 80dB All-Channel Off Isolation at 5MHz
♦ 8 Internal Buffers with:
Not Exceeding Package Power Dissipation.............Indefinite
Analog Input Voltage............................(V+ + 0.3V) to (V- - 0.3V)
MAX456
Digital Input Voltage.............................(V+ + 0.3V) to (V- - 0.3V)
Input Current, Power On or Off
Digital Inputs.................................................................±20mA
Analog Inputs ...............................................................±50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Operating Supply Voltage±4.5±5.5V
Supply Current, All Buffers On
(No External Load)
Supply Current, All Buffers Off
Power-Supply Rejection Ratio±4.5V to ±5.5V, DC measurement5064dB
Analog Input Current±0.1±10nA
Output Leakage Current
Internal Amplifier Load Resistor
(LOAD Pin = 5V)
Buffer Output Voltage SwingInternal load resistors on, no external load ±1.3V
Digital Input CurrentTA= T
Output Impedance at DC10Ω
Input Logic Low Threshold0.8V
Input Logic High Threshold2.4V
SER OUT Output Logic Low 0.4
SER OUT Output Logic High4
resistors on, no
external load,
V
= 0V to 1V
IN
TA= +25°C±7
TA= T
MIN
MIN
TA= +25°C3945
TA= T
MIN
TA= +25°C
TA= T
MIN
TA= T
MIN
Internal load resistors off, all buffers
off, TA= T
Additional capacitance for each output buffer connected to channel input
2pF
SWITCHING CHARACTERISTICS (Note 1)
(Figure 4, V+ = 5.0V, V- = -5.0V, -1.3V ≤ VIN≤ +1.3V, LOAD = +5V, internal load resistors on, AGND = DGND = 0V,
TA = T
Note 1: Guaranteed by design.
Note 2: See
Note 3: 3dB typical crosstalk improvement when R
Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
Note 1: Buffer inputs are internally grounded with a 1000 or 1001 command from the D3-D0 lines. AGND must be at 0.0V since the
gain setting resistors of the buffers are internally tied to AGND.
6, 8, 10, 13,
15, 17, 19, 21
28, 30, 32, 35,
37, 39, 41, 43
NAMEFUNCTION
Parallel Data Bit D1 when SER/P—A—R–= 0V. Serial Output for cascading
multiple parts when SER/P—A—R–= 5V.
Parallel Data Bit D0 when SER/P—A—R–= 0V. A Serial Input when
SER/P—A—R–= 5V.
IN0–IN7Video lnput Lines
Asynchronous control line. When LOAD = 1, all the 400Ω internal active
loads are on. When LOAD = 0, external 400Ω loads must be used. The
buffers MUST have a resistive load to maintain stability.
Digital Ground Pins. Both DGND pins must have the same potential and
be bypassed to AGND. DGND should be within ±0.3V of AGND.
When this control line is high, the 2nd-rank registers are loaded with the
rising edge of the LATCH line. If this control line is low, the 2nd-rank reg-
–
isters are transparant when LATCH is low, passing data directly from the
1st-rank registers to the decoders.
All V+ pins must be tied to each other and bypassed to AGND
separately (Figure 2).
–
5V = 32-Bit Serial, 0V = 7-Bit Parallel
Both V- pins must be tied to each other and bypassed to AGND
separately (Figure 2).
WRITE in the serial mode, shifts data in. In the parallel mode, WR loads
data into the 1st-rank registers. Data is latched on the rising edge.
If EDGE/–L—E—V—E—L–= 5V, data is loaded from the 1st-rank registers to the 2nd-
rank registers on the rising edge of LATCH. If EDGE/–L—E—V—E—L–= 0V, data is
loaded while LATCH = 0V. In addition, data is loaded during the execution
of parallel-mode functions 1011 through 1110, or if LATCH = 5V during the
execution of the parallel-mode "software-LATCH" command (1111).
–
OUT7-OUT0Output Buffers 7-0 (Note 1)
–C—h—i—p— —E—n—a—b—l—e–
Chip Enable. When –C—E–= 0V and CE = 5V, the WR line is enabled.
Analog Ground must be at 0.0V since the gain resistors of the buffers are
tied to these 3 pins.
Parallel Data Bit D3 when SER/ –P—A—R–= 0V. When D3 = 0V, D0-D2 specifies
the input channel to be connected to buffer. When D3 = 5V, then D0-D2
specify control codes. D3 is not used when SER/–P—A—R–= 5V.
Parallel Data Bit D2 when SER/–P—A—R–= 0V. Not used when
SER/–P—A—R–= 5V.
. When–C—E–= 0V and CE = 5V, the WR line is enabled.