Maxim MAX4455ECQ Datasheet

General Description

The MAX4455 is an eight-channel arbitrary graphics
on-screen display (OSD) video generator that inserts
arbitrary gray-scale bit-mapped graphics into eight
asynchronous composite video sources. Ideal for secu­rity camera surveillance systems, the MAX4455 sup­ports the insertion of graphics and text on up to eight
video output channels in 15 levels of brightness. It easi­ly displays information such as company logo, camera
location, time, and date with arbitrary fonts and sizes.
Arbitrary graphics capability enables the display of
unique languages and fonts, allowing manufacturers to
tailor their system for any geographic market. The
MAX4455 is designed to work with Maxim’s video
crosspoint switches, such as the MAX4356 and
MAX4358, which include circuitry that simplifies the
insertion of the OSD information. The MAX4455 can
also be used with discrete fast mux switches.

The MAX4455 operates from a 3V to 3.6V digital sup­ply, and a 2.7V to 5.5V analog supply. Independent
interface supplies enable the MAX4455 to communi­cate with microprocessors and OSD crosspoint switch
logic with logic levels ranging from 2.7V to 5.5V. The
MAX4455 uses an external 16Mb SDRAM for graphical
image storage for all eight video channels. The
MAX4455 manages all memory interface functions,
allowing a simple host µP interface. The MAX4455’s
multiple-channel memory sharing and multiple-location
write function allow fast memory updates of shared
graphics information necessary for rapidly changing
OSD information, such as a time stamp.

The MAX4455 is available in a thin 100-pin TQFP pack­age (200mm2area), and is fully specified over the
extended temperature range (-40°C to +85°C). The
MAX4455EVSYS is available to evaluate the MAX4455
along with the MAX4358 (32 × 16 video crosspoint
switch with OSD).

Applications

Security Systems

Video Routing

Industrial Applications

Features

♦ Generates Arbitrary Graphics Images

♦ 15-Level Gray Scale

♦ 8 Channels of Bit-Mapped OSD

♦ Loss-of-Signal Detector for All Channels

♦ Graphics Updatable Within the Vertical Interval

♦ Update Time Stamp on All Eight Channels

Simultaneously

♦ 3V and 5V Single-Supply Operation

♦ Works with MAX4356/MAX4358 Video Crosspoint

Devices and Fast Mux Switches

♦ Small 100-Pin TQFP Package (200mm

2

)

MAX4455

Arbitrary Graphics On-Screen Display

Video Generator

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-2463; Rev 2; 3/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

Functional Diagram

PART TEMP RANGE PIN-PACKAGE

MAX4455ECQ -40°C to +85°C 100 TQFP

4-BIT D/A

4-BIT D/A

4-BIT D/A

4 BIT D/A

V

K1

AGNDAVDDDGNDDV

MAX4455

OSD

CONTROL

AND TIMING

DAC

CURRENT

REF

OSDFILL0

OSDFILL1

OSDFILL2

RSET

OSDFILL7

OSDKEY0

OSDKEY1

OSDKEY2

OSDKEY7

XTAL1/SYNC

AD7–AD0

ADDR/DATA

VIDIN0

VIDIN1

VIDIN2

VIDIN7

RDY/BSY

DD

VIDEO TIMING

EXTRACTION

VIDEO TIMING

EXTRACTION

VIDEO TIMING

EXTRACTION

VIDEO TIMING

EXTRACTION

8

CPU

INTERFACE

RD

WR

CS

V

H1

WECASDQ RAS XTAL2

MEMORY

INTERFACE

BA

CK

11

MEMORY
ADDRESS

BUS

DIGITAL LINE

BUFFERS

DIGITAL LINE

BUFFERS

DIGITAL LINE

BUFFERS

DIGITAL LINE

BUFFERS

16

MEMORY

DATA
BUS

MAX4455

Arbitrary Graphics On-Screen Display
Video Generator

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

AVDDto DVDD.............................................................-6V to +6V

AV

DD

to AGND .........................................................-0.3V to +6V

AV

DD

to DGND .........................................................-0.3V to +6V

DV

DD

to AGND.........................................................-0.3V to +6V

DV

DD

to DGND.........................................................-0.3V to +6V

V

H1

, VK1to DGND....................................................-0.3V to +6V

V

H1

, VK1to AGND ....................................................-0.3V to +6V

AGND to DGND.....................................................-0.3V to +0.3V

Analog Inputs (VIDIN_) to AGND.............-0.3V to (AV

DD

+ 0.3V)

Analog Outputs (OSDFILL_) to AGND.....-0.3V to (AV

DD

+ 0.3V)

RSET to AGND .........................................-0.3V to (AV

DD

+ 0.3V)

Memory Interface to DGND .....................-0.3V to (DV

DD

+ 0.3V)

Host Interface to DGND ..............................-0.3V to (V

H1

+ 0.3V)

OSDKEY_ to DGND.....................................-0.3V to (V

K1

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

100-Pin TQFP (derate 37.0mW/°C above +70°C).......2963mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(DVDD= 3.0V to 3.6V, AVDD= 2.7V to 5.5V, V

K1

= VH1= 2.7V to 5.5V, AGND = DGND = 0, R

RSET

= 11.75kΩ±1%, R

OSDFILL_

= 75Ω,

f

XTAL1/SYNC

= 40.5MHz, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Analog Supply Voltage AV

Digital Supply Voltage DV

Host Supply Voltage V

OSDKEY Logic Supply Voltage V

Analog Supply Current AI

Digital Supply Current DI

Host Interface Static Supply
Current

Analog Power-Supply Rejection
Ratio

I

PSRR At DC 35 dB

VIDIN_ Input Resistance 100 kΩ

OSDFILL Slew Rate SR Output V

White Output Voltage Accuracy FSR Pixel data = 1111

Black Output Voltage Pixel data = 0001 ±1.5 IRE

OSDFILL DAC Linearity (Guaranteed monotonic) ±5 %FSR

Channel-to-Channel Crosstalk At 6MHz V

Key-to-Fill Timing Delay ±1 ns

RSET Pin Voltage 0.80 V

OSDKEY_ Logic Output Low V

OSDKEY_ Logic Output High V

OSDKEY_ Logic Supply Current I

DD

DD

H1

K1

All OSDFILL_ outputs at 100 IRE 190 mA

DD

f

DD

VH1

OL

OH

VK1

XTAL1/SYNC

Host interface logic levels driven to GND or
V

H1

P-P

OUT

VK1 = 5V, I

VK1 = 5V, I

SINK

SOURCE

OSDKEY_ logic levels driven to GND or V

2.7 5.5 V

3.0 3.6 V

2.7 5.5 V

2.7 5.5 V

= 40.5MHz 30 mA

10 µA

= 0.7V 140 V/µs

AVDD = 2.7V -8.2 +8.2

AV

= 5.5V -7.5 +7.5

DD

= 0.7V

P-P

60 dB

= 4mA 0.45 V

= 4mA 2.4 V

K1

10 µA

IRE

MAX4455

Arbitrary Graphics On-Screen Display

Video Generator

_______________________________________________________________________________________ 3

µP HOST INTERFACE—DC CHARACTERISTICS

(DVDD= 3.0V to 3.6V, AVDD= 2.7V to 5.5V, VK1= VH1= 2.7V to 5.5V, AGND = DGND = 0, R

RSET

= 11.75kΩ±1%, R

OSDFILL_

= 75Ω,

f

XTAL1/SYNC

= 40.5MHz, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

µP HOST INTERFACE—AC CHARACTERISTICS

(DVDD= 3.0V to 3.6V, AVDD= 2.7V to 5.5V, VK1= VH1= 2.7V to 5.5V, AGND = DGND = 0, R

RSET

= 11.75kΩ ±1%, R

OSDFILL_

= 75Ω,

f

XTAL1/SYNC

= 40.5MHz, C

HOST

= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

(Figure 1)

CLOCK TIMING CHARACTERISTICS

(DVDD= 3.0 to 3.6V, AVDD= 2.7V to 5.5V, VK1= VH1= 2.7V to 5.5V, AGND = DGND = 0, R

RSET

= 11.75kΩ ±1%, R

OSDFILL_

= 75Ω,

f

XTAL1/SYNC

= 40.5MHz, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 4) (Figure 2)

MEMORY INTERFACE—DC CHARACTERISTICS

(DVDD= 3.0V to 3.6V, AVDD= 2.7V to 5.5V, VK1= VH1= 2.7V to 5.5V, AGND = DGND = 0, R

RSET

= 11.75kΩ ±1%, R

OSDFILL_

= 75Ω,

f

XTAL1/SYNC

= 40.5MHz, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 2)

Logic Input Voltage Low V

Logic Input Voltage High V

Logic Input Current IIL / I

Logic Output Low V

Logic Output High V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IL

IH

Sinking or sourcing 10 µA

IH

OL

OH

VH1 = 5V, I

VH1 = 5V, I

= 4mA 0.45 V

SINK

= 4mA 2.4 V

SOURCE

CS, ADD/DATA, AD7–AD0 Setup
Time Before WR Deassertion

CS Hold After WR Deassertion t

Read Data Access Time t

Read Data Out to High-Z Time t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

t

1

2

(Note 3) 50 ns

4

5

( 0.2 × V

- 0.1

( 0.2 × V
+ 1.2

)

H 1

30 ns

30 ns

15 25 ns

H 1

)

V

V

Master Clock Frequency f

Master Clock Input Low Time t

Master Clock Input High Time t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLKIN

CLCXtCLKIN

CHCX

Crystal oscillator or externally driven for
specified performance

t

CLKIN

= 1 / f

= 1 / f

(Note 6) 10 ns

CLKIN

(Note 6) 10 ns

CLKIN

Logic Input Voltage Low V

Logic Input Voltage High V

Logic Input Current IIL / I

Logic Output Low V

Logic Output High V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IL

IH

Sinking or sourcing 10 µA

IH

OL

OH

DVDD = 3.3V, I

DVDD = 3.3V, I

= 4mA 0.45 V

SINK

= 0.5mA 2.4 V

SOURCE

40.5 40.6 MHz

( 0.2 × D V

- 0.1

( 0.2 × D V
+ 1.3

D D

)

)

D D

V

V

MAX4455

Arbitrary Graphics On-Screen Display
Video Generator

4 _______________________________________________________________________________________

MEMORY INTERFACE TIMING CHARACTERISTICS

(DVDD= 3.0V to 3.6V, AVDD= 2.7V to 5.5V, VK1= VH1= 2.7V to 5.5V, AGND = DGND = 0, R

RSET

= 11.75kΩ ±1%, R

OSDFILL_

= 75Ω,

f

XTAL1/SYNC

= 40.5MHz, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)

Note 1: f

XTAL1/SYNC

is production tested at 1MHz. Application operating frequency is f

XTAL1/SYNC

= 40.5MHz.

Note 2: Pertains to host interface pins: ADDR/DATA, CS, WR, RD, AD7–AD0, RDY/BSY. V

H1

is connected to µP host power supply

rail (2.7V to 5.5V).

Note 3: Read operation is combinational. Access time is from the latter of either RD or CS.
Note 4: Pertains to XTAL1/SYNCIN and XTAL2 pins (external clock is supplied to XTAL1/SYNCIN pin). All input signals are specified

with t

R

= tF= 5ns (10% to 90% of DVDD), and timed from a voltage level of 1.6V.

Note 5: Specified using 10% and 90% points.

Figure 2. Clock and Memory Timing Diagram

Figure 1. µP Host Interface Timing

Timing Diagrams

Digital Output Maximum Rise
Time

Digital Output Maximum Fall Time t

Maximum Digital Out to Digital
Out Skew

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

t

CLCH

CHCL

t

SKEW

15pF load (Note 5) 3 ns

15pF load (Note 5) 3 ns

15pF load, except D0–D15 ±2.5 ns

t

1

t

CHCX

V

IH

V

IL

t

CLCX

V

IH

V

IL

t

CHCL

ADD/DATA

AD7–AD0

WR

ADD/DATA

AD7–AD0

CS

HOST ADDRESS OR DATA WRITE OPERATION

CS

t

4

RD

ADDR/DATA IN

READ DATA OUT

t

2

XTAL1/SYNC

t

CLCH

t

3

MEMORY
LOGIC I/O

t

5

HOST DATA READ OPERATION

MAX4455

Arbitrary Graphics On-Screen Display

Video Generator

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(AVDD= 5V, DVDD= 3.3V, R

RSET

= 11.75kΩ, TA= +25°C, unless otherwise noted.)

FULL-SCALE OUTPUT vs. R

225

200

175

150

125

100

75

FULL-SCALE OUTPUT (IRE)

50

25

0

415

R

(kΩ)

RSET

RSET

141311 126 7 8 9 105

VIDEO LINE OUTPUT WITH OSD

A

B

MAX4455 toc01

110

R

RSET

100

90

80

70

60

50

40

DAC OUTPUT (IRE)

30

20

10

0

115

MAX4455 toc04

DAC OUTPUT vs. DAC CODE

= 11.75kΩ

DAC CODE

0

A

0

B

DAC OUTPUT vs. DAC CODE

225

200

MAX4455 toc02

175

150

125

R

= 11.75kΩ

RSET

100

DAC OUTPUT (IRE)

75

50

25

141311 124 5 6 7 8 9 102 3

0

115

VIDEO LINE OUTPUT WITH OSD

(EXPANDED TIME SCALE)

MAX4455 toc05

R

RSET

vs. R

RSET

R

= 5.716kΩ

RSET

= 17.516kΩ

DAC CODE

0

0

R

RSET

R

RSET

MAX4455 toc03

= 7.636kΩ

= 14.598kΩ

141311 124 5 6 7 8 9 102 3

C

D

10µs/div

A: V

(NTSC COMPOSITE), 500mV/div

CAMERA

B: V

CAMERA + OSDFILL

C: V

OSDFILL

D: V

OSDKEY

NOTE: MEASUREMENT MADE WITH MAX4455EVSYS.

, 500mV/div
, 5V/div

, 500mV/div

0

0

C

D

A: V

CAMERA

B: V

CAMERA + OSDFILL

C: V

OSDFILL

, 5V/div

D: V

OSDKEY

NOTE: MEASUREMENT MADE WITH MAX4455EVSYS.

1µs/div

(NTSC COMPOSITE), 500mV/div

, 500mV/div

, 500mV/div

0

0

MAX4455

Arbitrary Graphics On-Screen Display
Video Generator

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(AVDD= 5V, DVDD= 3.3V, R

RSET

= 11.75kΩ, TA= +25°C, unless otherwise noted.)

Figure 3. On-Screen Display Capability of the MAX4455

MAX4455

Arbitrary Graphics On-Screen Display

Video Generator

_______________________________________________________________________________________ 7

Pin Description

PIN NAME FUNCTION

2, 1, 100, 99, 98, 97,

96, 95

3V

4, 25, 33, 42, 50, 58,

66, 72, 75

5 CS Host Chip Select Digital Input. Drive CS logic high to enable the host data interface.

6
7 RD Host Read Strobe Digital Input

8 ADDR/DATA Host Address or Data Select Digital Input

9–16 AD7–AD0 Host Address/Data Bus Digital I/O

17 RDY/BSY Host Ready/Busy Handshake Digital Output

18–23, 26, 27, 37,
36, 35, 34, 31, 30,

29, 28

24, 32, 41, 49, 57, 71 DV

38 DQM

39 CLK Memory Clock Digital Output
48 WE Memory Write Enable Digital Output
51 CAS Memory Column Address Strobe Digital Output
52 RAS Memory Row Address Strobe Digital Output

53 BA Memory Bank Address Digital Output

55, 56, 59, 60, 47,

46, 45, 44, 43, 40, 54

61–64, 67–70

VIDIN0–VIDIN7

DGND Digital Ground

D0–D15 Memory Data Digital I/O

A0–A10 Memory Address Digital Outputs

OSDKEY0–

OSDKEY7

Analog Video Inputs. The MAX4455 extracts video timing information from each VIDIN_
input. AC-couple the input signal with a 0.1µF capacitor.

H1

WR Host Write Strobe Digital Input

DD

Host Interface Supply Voltage Input. VH1 supplies the level shifters for logic outputs to the
host µP interface. Connect V

Positive Digital Power Supply. Bypass each DVDD pin with a 0.1µF capacitor to DGND.

Memory DQM Digital Output. DQM controls the memory output buffer in read mode, and
masks input data in write mode.

OSDKEY Digital Outputs. OSDKEY_ logic low controls the fast mux switches (available in
the Maxim crosspoint switches, MAX4356/MAX4358) to insert OSDFILL_ signal.

to the µP logic supply.

H1

65 V

73 XTAL1/SYNC

74 XTAL2

76, 78, 80, 82, 84,

86, 88, 90, 92

77, 79, 81, 83, 85,

87, 89, 91

K1

AV

DD

OSDFILL7–

OSDFILL0

OSDKEY Interface Power-Supply Input. VK1 supplies the level shifters for OSDKEY_ logic
outputs to the fast mux switches (available in the Maxim crosspoint switches,
MAX4356/MAX4358). Connect V
the MAX4356/MAX4358).

Crystal Oscillator/External Clock Input. Connect a crystal oscillator module to
XTAL1/SYNC, or connect a fundamental mode crystal oscillator between XTAL1/SYNC and
XTAL2.

Crystal Oscillator Output. Leave XTAL2 unconnected when using a crystal oscillator
module, or connect a fundamental mode crystal oscillator between XTAL1/SYNC and
XTAL2.

Positive Analog Power Supply. Bypass each AVDD pin with a 0.1µF capacitor to AGND.

OSDFILL Analog Outputs. OSDFILL_ are video DAC current outputs and require a
termination resistor (nominally 75Ω) to AGND.

to the digital supply of the fast mux switches (VDD of

K1

MAX4455

Arbitrary Graphics On-Screen Display
Video Generator

8 _______________________________________________________________________________________

Detailed Description

The MAX4455 provides 4-bit gray-scale graphics video
to eight simultaneous independent composite video
inputs. The bit-mapped approach allows an arbitrary
message to be inserted into the camera video when
used in conjunction with the MAX4356/MAX4358 video
crosspoint switch or discrete fast mux switch. The
inserted graphics can include camera location, date,
time, company logo, or warning prompts.

The graphics palette for each of the eight video channels
in the MAX4455 is logically organized into 1024 pixels by
512 lines. This memory arrangement facilitates easy
row/column pixel addressing by the host processor. The
actual displayed area is 712 × 484 NTSC (712 × 512 PAL)
pixels. The remaining 312 logical pixels per line are
blanked. The remaining 28 NTSC (0 PAL) horizontal lines
are also blanked as shown in Figure 4.

The MAX4455 controls a 16Mb SDRAM (such as
MT48LC1M16A) that stores video graphics insertion data.
The MAX4455 performs all SDRAM support functions,
including refresh, RAS/CAS timing, video addressing, and
CPU access cycles for host processor read/write support.

Since the SDRAM is organized as a 16-bit wide × 1 mil­lion deep array, each SDRAM memory location holds 4
pixels (based on the fact that a pixel is 4 bits and mem­ory is 16 bits wide). The host processor thus accesses
pixels four at a time. The host processor interface is 8
bits wide so the 16 bit wide SDRAM data is written into
(or read from) the pixel data register as two separate
8-bit bytes.

The MAX4455 establishes a video raster time base by
sensing the video signal on either the output of the
Maxim crosspoint switch, or the output buffer of the fast
mux switch. The MAX4455 uses this raster timing to
produce an OSD image signal that can be inserted into
the camera video by controlling the OSDKEY input to
the Maxim crosspoint switch or fast mux switch. The
OSD image is inserted wherever the OSD video level
pixel code has a nonzero value, and the crosspoint
switch or discrete fast mux is made to pass the original
video wherever the OSD video level pixel code is zero.
When the OSD video level is nonzero, it represents a
gray-level code such that level 1 is near black and
code 15 (the maximum possible with a 4-bits-per-pixel

code) is maximally white (Table 1). The host computer
fills the external OSD frame memory with a bit-mapped
image such that each pixel has a value between zero
and 15, controlling both insertion locations and the
brightness levels within an inserted video image. There
are eight channels in the MAX4455 that share memory
resources but are logically completely independent.
Writing/reading image data to/from any channel’s mem­ory does not disrupt other channels.

The MAX4455 features a memory-sharing function
where the even channels or the odd channels can be
updated simultaneously by writing to a designated
source channel. The memory-sharing function mini­mizes the number of memory writes by the host proces­sor. This is useful for updating information that changes
rapidly (i.e., time stamp).

Video Inputs

The MAX4455’s eight VIDIN_ inputs include circuitry to
extract video timing from each asynchronous video
channel for proper display of the OSD specific to that
channel. Each VIDIN_ time-base circuitry includes a
horizontal sync detector, vertical sync detector, vertical
interval detector, horizontal line counter, and even/odd
field counter. The VIDIN_ inputs sense a standard 1V

P-P

video signal at the output of the crosspoint switch, or
fast mux buffer in order to make video timing insensitive
to delays through the switch/mux. AC-couple the input
with a 0.1µF capacitor.

OSDFILL_ Video Outputs

The MAX4455 has eight independent current output
video DACs that provide 7 IRE to 100 IRE video levels
(R

RSET

= 11.75kΩ) when terminated with 75Ω to
AGND. Connect OSDFILL_ to either the OSDFILL_
input of the Maxim crosspoint switch (MAX4356/
MAX4358) or to one of the inputs of the fast mux switch.

OSDKEY Control Outputs

Each OSD channel has an OSDKEY_ logic output that
drives low when OSDFILL_ output video is to be multi­plexed into the active video. The OSDKEY_ output
interfaces directly to the OSDKEY_ inputs of the
MAX4356/MAX4358 or control inputs of the fast mux
switch to allow pixel-by-pixel OSD insertion. The V

K1

supply sets the OSDKEY_ logic output voltage levels.

Pin Description (continued)

PIN NAME FUNCTION

93 RSET

94 AGND Analog Ground

OSDFILL Reference Voltage. Connect a resistor (typically 11.75kΩ) from RSET to AGND to
set the full-scale output current of all eight OSDFILL_ outputs.

MAX4455

Arbitrary Graphics On-Screen Display

Video Generator

_______________________________________________________________________________________ 9

Connect VK1to the MAX4356/MAX4358 VDDlogic sup­ply, or a 5V logic supply for TTL output compatibility.

OSDFILL_ Reference Voltage (RSET)

Set the video DAC’s full-scale output current for all
eight channels by connecting a resistor between RSET
and ground. The nominal 11.75kΩ R

RSET

provides a
100 IRE video output level when OSDFILL_ outputs are
terminated with 75Ω resistors to ground. R

RSET

can typ-

ically range between 5kΩ and 15kΩ.

The full-scale OSD DAC output current = (106.5) / R

RSET

.
The full-scale OSD DAC output voltage is the OSD DAC
output current × R

OSDFILL

, where ROSDFILL_ is the termi-

nation resistor to AGND at OSDFILL_.

Crystal Oscillator

The MAX4455 requires a 40.5MHz clock. Connect a 3.3V
crystal oscillator module to XTAL1/SYNC and leave
XTAL2 unconnected, or connect a lower cost 40.5MHz
fundamental mode crystal between XTAL1/SYNC and
XTAL2. The MAX4455 is designed to operate with a 50%
clock duty cycle, but typically operates with up to 40% to
60% duty cycles. The oscillator circuitry typically requires
10ms to settle after the DV

DD

supply is powered up.

Microprocessor Interface

The MAX4455 µP interface includes a byte-wide
address/data bus (AD7–AD0) for parallel programming
of the MAX4455, write strobe input (WR), read strobe
input (RD), active-high chip-select input (CS), address
or data-select input (ADDR/DATA), and a ready/busy
hand-shaking output (RDY/BSY) (Figures 5 and 6). The
MAX4455 allows for interfacing to a µP powered from a
different supply than the MAX4455 by connecting V

H1

to the µP supply. For example, the MAX4455 can be
operated with a single 3.3V supply, while the µP inter­face can be operated with 3.3V or 5V logic levels by
connecting VH1to the µP power supply.

Host Access Protocol Sequence

1) Host sets ADD/DATA = 1.

2) Host outputs register address on AD7–AD0.

3) Host pulses WR low, then high to write register

address.

4) Host checks RDY/BSY = 1 (host waits if RDY/BSY = 0).

For register data writes:

1) Host sets ADD/DATA = 0.

2) Host drives register data on AD7–AD0.

3) Host pulses WR low, then high.

For register data reads:

1) Host removes drive from AD7–AD0 in anticipation of

register read operation and sets ADD/DATA = 0.

2) Host then pulses RD low and reads register data.

3) The MAX4455 three states when RD is deasserted

(high).

SDRAM Memory Interface

The MAX4455 interfaces directly to a 16Mb SDRAM
with 16-bit-wide data bus. The MAX4455 performs all
SDRAM support functions, including refresh, RAS/CAS
timing, data addressing, and CPU access cycles for
host processor read/write support.

MAX4455 Register Description

OSD Register Organization

The host processor controls each of the MAX4455’s
eight video channels through eight groups (blocks) of 8­bit command, status, data, and address registers, plus
one multichannel register block. The register set descrip­tion for a single channel is described in Table 2. The
eight identical sets of 16 registers (14, plus 2 reserved)
are selected by 4 LSB bits in the host interface address
field as described in Tables 3 and 4. The lower address
bits select which register is accessed within any given
channel. Even channels can share buffer data for display

Table 1. Pixel Data Mapping (4 Bits per
Pixel)

PIXEL DATA GRAY SCALE DESCRIPTION

Transparent—no OSD

0000 0

0001 1 7 IRE (black)

0010 2 13 IRE

0011 3 20 IRE

0100 4 27 IRE

0101 5 33 IRE

0110 6 40 IRE

0111 7 47 IRE

1000 8 53 IRE

1001 9 60 IRE

1010 10 67 IRE

1011 11 73 IRE

1100 12 80 IRE

1101 13 87 IRE

1110 14 93 IRE

1111 15 100 IRE (white)

insertion. Background
video appears normally.