The MAX4358 is a 32 ✕ 16 highly integrated video
crosspoint switch matrix with input and output buffers
and On-Screen Display (OSD) Insertion. This device
operates from dual ±3V to ±5V supplies or from a single +5V supply. Digital logic is supplied from an independent single +2.7V to +5.5V supply. Individual
outputs can be switched between an input video signal
source and OSD information through an internal, dedicated fast 2:1 mux (40ns switching times) located
before the output buffer. All inputs and outputs are
buffered, with all outputs able to drive standard 75Ω
reverse-terminated video loads.
The switch matrix configuration and output buffer gain
are programmed through an SPI/QSPI™-compatible,
three-wire serial interface and initialized with a single
update signal. The unique serial interface operates in
two modes facilitating both fast updates and initialization. On power-up, all outputs are initialized in the disabled state to avoid output conflicts in large-array
configurations.
Superior flexibility, high integration, and space-saving
packaging make this nonblocking switch matrix ideal
for routing video signals in security and video-ondemand systems.
The MAX4358 is available in a 144-pin TQFP package
and specified over an extended -40°C to +85°C temperature range. The MAX4358 evaluation kit is available
to speed designs.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Analog Supply Voltage (VCC- VEE) .....................................+11V
Digital Supply Voltage (V
DD
- DGND) ...................................+6V
Analog Supplies to Analog Ground
(V
CC
- AGND) and (AGND - VEE) ..................................... +6V
Analog Ground to Digital Ground .........................-0.3V to +0.3V
IN__, OSDFILL__ Voltage Range .... (V
CC
+ 0.3V) to (VEE- 0.3V)
OUT__ Short-Circuit Duration to AGND, V
CC
, or VEE....Indefinite
SCLK, CE, UPDATE, MODE, A_, DIN, DOUT,
RESET, AOUT, OSDKEY__..........(V
DD
+ 0.3V) to (DGND - 0.3V)
Current Into Any Analog Input Pin (IN_, OSDFILL_).........±50mA
Current Into Any Analog Output Pin (OUT_).....................±75mA
Not ValidSetup Time: UPDATE to Clk with UPDATE Low
t
HdHUd
Not ValidHold Time: Clk to UPDATE with UPDATE Low
t
PdDiDo
t
MnMd
t
MxTr
t
MnLRst
t
PdRstVo
TIMING PARAMETER DEFINITIONS
NAMEDESCRIPTION
t
PdUdVo
t
PdUdAo
t
PdOkVo
t
PdOfVo
t
PdDo
t
PdHOeVo
t
PdLOeVo
t
SuCe
t
SuDi
Hold Time: Clock to Data In
Min High Time: Clk
Min Low Time: Clk
Min Low Time: Update
Setup Time: UPDATE to Clk with UPDATE High
Hold Time: Clk to UPDATE with UPDATE high
Asynchronous Delay: Data In to Data Out
Min Low Time: MODE
Max Rise Time: Clk, Update
Min Low Time: Reset
Delay: Reset to Video Output
Delay: Update to Video Out
Delay: UPDATE to Aout
Delay: OSD Key to Video Output
Delay: OSD Fill to Video Output
Delay: Clk to Data Out
Delay: Output Enable to Video Output
(High: Disable)
Delay: Output Enable to Video Output
(Low: Enable)
Setup: Clock Enable to Clock
Setup Time: Data In to Clock
Of: OSDFILL
Ok: OSDKEY
OUT
i
i
i
t
PdHOkVo
(WITH SUPERIMPOSED OSD)
t
PdLOkVo
t
PdLOfVo
VIDEO OUTPUT
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
Serial Interface Mode Select Input. Drive high for Complete Matrix Mode
(Mode 1), or drive low for Individual Output Address Mode (Mode 0).
Update Input. Drive UPDATE low to transfer data from Mode Registers to the
switch matrix.
Asynchronous Reset Input/Output. Drive RESET low to initiate hardware reset.
All analog outputs are disabled. Additional power-on reset delay may be set
by connecting a small capacitor from RESET to DGND.
Serial Data Output. In Complete Matrix Mode, data is clocked through the 112bit Matrix Control shift register. In Individual Output Address Mode, data at DIN
passes directly to DOUT.
Digital Control Input. Control for the fast 2:1 OSD Insertion multiplexer routing
signal to output buffers. A logic high routes programmed IN_ analog input
signal to output buffer. A logic low routes the dedicated OSDFILL_ input to
corresponding output buffer.
Digital Logic Supply. Bypass VDD with a 0.1µF capacitor to DGND.
Buffered Analog Outputs. Gain is individually programmable for A
= +2V/V via the serial interface. Outputs may be individually disabled (high
A
V
impedance). On power-up, or assertion of RESET, all outputs are disabled.
The MAX4358 is a highly integrated 32 ✕ 16 nonblocking video crosspoint switch matrix . All inputs and outputs are buffered, with all outputs able to drive
standard 75Ω reverse-terminated video loads.
A three-wire interface programs the switch matrix and
initializes with a single update signal. The unique serial
interface operates in one of two modes, Complete
Matrix Mode (Mode 1) or Individual Output Address
Mode (Mode 0).
The signal path of the MAX4358 is from the buffered
inputs (IN0–IN31), through the switching matrix,
buffered by the output amplifiers, and presented at the
outputs (OUT0–OUT15) (Functional Diagram). The
other functional blocks are the serial interface and control logic. Each of the functional blocks is described in
detail below.
Analog Outputs
The MAX4358 outputs are high-speed amplifiers capable of driving 150Ω (75Ω back-terminated) loads. The
gain, AV= +1V/V or +2V/V, is selectable via programming bit 5 of the serial control word. Amplifier compensation is automatically optimized to maximize the
bandwidth for each gain selection. Each output can be
individually enabled and disabled via bit 6 of the serial
control word. When disabled, the output is high impedance presenting typically 4kΩ load, and 3pF output
capacitance, allowing multiple outputs to be connected
together for building large arrays. On power-up (or
asynchronous RESET) all outputs are initialized in the
disabled state to avoid output conflicts in large array
configurations. The programming and operation of the
MAX4358 is output referred. Outputs are configured
individually to connect to any one of the 32 analog
inputs, programmed to the desired gain (AV= +1V/V or
+2V/V), and enabled or disabled in a high-impedance
state.
Functional Diagram
RESET
UPDATE
IN0
IN1
IN2
IN31
DIN
SCLK
OSDFILL1
OSDFILL0OSDFILL15
MAX4358
AV*
32 x 16
SWITCH MATRIX
POWER-ON
RESET
SERIAL
CE
INTERFACE
THERMAL
SHUTDOWN
DISABLE ALL OUTPUTS
DECODE LOGIC
MATRIX REGISTER
UPDATE REGISTER
512
LATCHES
112 BITS
16 BITS
16
2:1
OSD
MUX
AV*
AV*
AV*
16
ENABLE/DISABLE
OUT0
OUT1
OUT2
OUT15
V
CC
V
EE
AGND
V
DD
DGND
DOUT
AOUT
A0-A3 MODE
*A
= +1V/V OR +2V/V
V
OSDKEY0OSDKEY15
OSDKEY1
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
The MAX4358 offers 32 analog input channels. Each
input is buffered before the crosspoint matrix switch,
allowing one input to cross-connect up to 16 outputs.
The input buffers are voltage feedback amplifiers with
high-input impedance and low input bias current. This
allows the use of very simple input clamp circuits.
OSDFILL and OSDKEY Inputs
Intended for on-screen display insertion, the 16 OSDFILL inputs are buffered analog signal inputs that are
routed to a dedicated output buffer through a fast 2:1
MUX. The signal presented to the output buffer is
selected from the programmed analog input signal
(IN_) and the dedicated OSDFILL input signal.
Switch Matrix
The MAX4358 has 512 individual T-switches making a
32 ✕ 16 switch matrix. The switching matrix is 100%
nonblocking, which means that any input may be routed to any output. The switch matrix programming is
output-referred. Each output may be connected to any
one of the 32 analog inputs. Any one input can be routed to all 16 outputs with no signal degradation.
Digital Interface
The digital interface consists of the following pins: DIN,
DOUT, SCLK, AOUT, UPDATE, CE, A3–A0, MODE, and
RESET. DIN is the serial-data input, DOUT is the serialdata output.
Note: "X" = Don’t Care
CEUPDATE
1XXXXXX1No change in logic
01 ↓
00 X X X 1 1 1
01 ↓
SCLKDINDOUTMODE
D
i
D
i
D
i-112
D
i
11 1
01 1
AOUTRESET
OPERATION/COMMENTS
Data at DIN is clocked on
negative edge of SCLK into 112bit Complete Matrix Mode
register. DOUT supplies original
data in 112 SCLK pulses later.
Data in serial 112-bit Complete
Matrix Mode register is
transferred into parallel latches
which control the switching
matrix.
Data at DIN is routed to
Individual Output Address Mode
shift register. DIN is also
connected directly to DOUT so
that all devices on the serial bus
may be addressed in parallel.
00 X
XX XX XXX 0
D
i
D
i
00 1
4-bit chip address A3–A0 is
compared to D14–D11. If equal,
remaining 11 bits in Individual
Output Address Mode Register
are decoded, allowing
reprogramming for a single
output. AOUT signals successful
individual matrix update.
Asynchronous reset. All outputs
are disabled. Other logic remains
unchanged.
SCLK is the serial-data clock which clocks data into the
data input registers (Figure 3). Data at DIN is loaded in
at each falling edge of SCLK. DOUT is the data shifted
out of the 112-bit Complete Matrix Mode register (Mode
= 1). DIN passes directly to DOUT when in Individual
Output Address Mode (Mode = 0).
The falling edge of UPDATE latches the data and programs the matrix. When using Individual Output
Address Mode, the address recognition output AOUT
drives low when control-word bits D14 to D11 match
the address programming inputs (A3–A0) and UPDATE
is low (Table 1). Table 1 is the operation truth table.
Programming the Matrix
The MAX4358 offers two programming modes:
Individual Output Address Mode and Complete Matrix
Mode. These two distinct programming modes are
selected by toggling a single MODE pin high or low.
Both modes operate with the same physical board layout. This flexibility allows initial programming of the IC
by daisy-chaining and sending one long data word
while still being able to immediately address and
update individual outputs in the matrix.
Individual Output Address Mode (MODE = 0)
Drive MODE to logic low to select Mode 0. Individual
outputs are programmed via the serial interface with a
single 16-bit control word. The control word consists of
a don’t care MSB, the chip address bits, output
address bits, an output enable/disable bit, an output
gain-set bit, and input address bits (Table 2 through
Table 6, and Figure 2).
Figure 2. Serial Interface Block Diagram
4
SCLK
MODE
CE
A0–A3
CHIP ADDRESS
4
SCLK
CE
MODE
DIN
16-BIT INDIVIDUAL OUTPUT
ADDRESS MODE REGISTER
11
112-BIT COMPLETE MATRIX MODE REGISTER
11
OUTPUT ADDRESS DECODE
UPDATE
EN
SWITCH MATRIX
112-BIT PARALLEL LATCH
51216
7
SWITCH DECODE
7
112
MODE
1
OUTPUT ENABLE
112
AOUT
112
MODE
A
DATA
ROUTING
GATE
B
MODE
S
DOUT
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
In Mode 0, data at DIN passes directly to DOUT
through the data routing gate (Figure 3). In this configuration, the 16-bit control word is simultaneously sent to
all chips in an array of up to 16 addresses.
Complete Matrix Mode (MODE = 1)
Drive MODE to logic high to select Mode 1. A single
112-bit control word, consisting of sixteen 7-bit control
words, programs all outputs. The 112-bit control word’s
first 7-bit control word (MSBs) programs output 15, and
the last 7-bit control word (LSBs) programs output 0
(Table 7 and Figures 4 and 5). Data clocked into the
112-bit complete matrix mode register is latched on the
falling edge of UPDATE, and the outputs are immediately updated.
Initialization String
Complete Matrix Mode (Mode = 1) is convenient for
programming the matrix at power-up. In a large matrix
consisting of many MAX4358s, all the devices can be
programmed by sending a single bit stream equal to n
x 112 bits where n is the number of MAX4358 devices
on the bus. The first 112-bit data word programs the
last in-line MAX4358 (see Matrix Programming under
the Applications Information section).
On-Screen-Display (OSD) Fast MUX
The MAX4358 features an asynchronous dedicated 2:1
Mux for each output buffer amplifier. Fast 40ns switching times enable pixel switching for on-screen-display
(OSD) information such as text or other picture-in-picture signals (Figure 1). OSDFILL_ inputs are buffered
analog inputs connected to each dedicated OSD Mux.
Drive the dedicated OSDKEY_ digital input to switch
between the programmed IN_ input from the crosspoint
switch matrix and the OSDFILL_. A logic low on
OSDKEYi routes the analog signal at OSDFILLi to the
OUTi output buffer. OSDKEY_ control does not affect
the crosspoint switch matrix programming or the output-buffer enable/disable or gain-set programming.
RESET
The MAX4358 features an asynchronous bidirectional
RESET with an internal 20kΩ pullup resistor to VDD.
When RESET is pulled low either by internal circuitry, or
driven externally, the analog output buffers are latched
into a high-impedance state. After RESET is released,
the output buffers remain disabled. The outputs may be
enabled by sending a new 112-bit data word or a 16-bit
individual output address word. A reset is initiated from
any of three sources. RESET can be driven low by
external circuitry to initiate a reset, or RESET can be
pulled low by internal circuitry during power-up (poweron-reset) or thermal shutdown.
Table 2. 16-Bit Serial Control Word Bit Assignments (Mode 0: Individual Output
Address Mode)
BITNAMEFUNCTION
15 (MSB)XDon’t Care
14IC Address A3MSB of selected chip address
13IC Address A2
12IC Address A1
11IC Address A0LSB of selected chip address
10Output Address B3MSB of output buffer address
9Output Address B2
8Output Address B1
7Output Address B0LSB of output buffer address
6Output EnableEnable bit for output, 0 = disable, 1 = enable.
5Gain SetGain Select for output buffer, 0 = gain of +1V/V, 1 = gain of +2V/V.
4Input Address 4MSB of input channel select address
3Input Address 3
2Input Address 2
1Input Address 1
0 (LSB)Input Address 0LSB of input channel select address
Since driving RESET low only clears the output-bufferenable bit in the matrix control latches, RESET can be
used to disable all outputs simultaneously. If no new
data has been loaded into the 112-bit complete matrix
mode register, a single UPDATE restores the previous
matrix control settings.
Power-On-Reset
The power-on-reset ensures all output buffers are in a
disabled state when power is initially applied. A V
DD
voltage comparator generates the power-on-reset.
When the voltage at V
DD
is less than 2.5V, the power-
on-reset comparator pulls RESET low via internal circuitry. As the digital-supply voltage ramps up crossing
2.5V, the MAX4358 holds RESET low for 40ns (typ).
Connecting a small capacitor from RESET to DGND
extends the power-on-reset delay. (see the Power-On-
Reset vs. RESET Capacitance graph in TypicalOperating Characteristics).
Thermal Shutdown
The MAX4358 features thermal shutdown protection
with temperature hysteresis. When the die temperature
exceeds 150°C, the MAX4358 pulls RESET low, disabling the output buffer. When the die cools by 20°C,
the RESET pulldown is deasserted, and output buffers
remain disabled until the device is programmed again.
Applications Information
Building Large Video-Switching Systems
The MAX4358 can be easily used to create larger
switching matrices. The number of ICs required to
implement the matrix is a function of the number of
input channels, the number of outputs required, and
whether the array needs to be nonblocking or not.
Figure 3. Mode 0, Individual Output Address Mode Timing and Programming Example
16-BIT INDIVIDUAL OUTPUT ADDRESS MODE:
FIRST BIT IS A DON'T CARE BIT, LAST 15 BITS CLOCKED INTO DIN WHEN MODE = 0, CREATES ADDRESS WORD; IC ADDRESS A3–A0 IS COMPARED TO DIN14–DIN11
WHEN UPDATE IS LOW; IF EQUAL, ADDRESSED OUTPUT IS UPDATED
UPDATE
t
MODE
SCLK
SuMd
DIN
t
HdMd
DON'T CARE X
IC ADDRESS A3
IC ADDRESS A2
IC ADDRESS = 2OUTPUT ADDRESS = 9
IC ADDRESS A0
IC ADDRESS A1
OUTPUT ADDRESS B1
OUTPUT ADDRESS B2
OUTPUT ADDRESS B3
EXAMPLE OF 16-BIT SERIAL CONTROL WORD FOR OUTPUT CONTROL IN INDIVIDUAL OUTPUT ADDRESS MODE
OUTPUT ENABLE
OUTPUT ADDRESS B0
GAIN SET = +1V/V
INPUT ADDRESS 1 = 0
INPUT ADDRESS 2 = 0
INPUT ADDRESS 3 = 0
INPUT ADDRESS 4 (MSB) = 1
OUTPUT (i) ENABLED, A
CONNECTED TO INPUT 16
= +1V/V,
V
INPUT ADDRESS 0 (LSB) = 0
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
Figure 4. 7-Bit Control Word and Programming Example (Mode 1: Complete Matrix Mode)
SCLK
t
SuDi
DIN
UPDATE
DOUT
EXAMPLE OF 7-BIT
SERIAL CONTROL WORD
FOR OUTPUT CONTROL
OUTPUT (i) ENABLED, AV = +1V/V,
CONNECTED TO INPUT 28
t
HdDi
t
PdDo
t
MnLCk
SCLK
DIN
t
MnHCk
+1V/V
t
SuHUd
t
MnLUd
NEXT CONTROL WORD
ENABLE OUTPUT
GAIN SET =
INPUT ADDRESS 3 = 1
INPUT ADDRESS 4 (MSB) = 1
INPUT ADDRESS 2 = 1
INPUT ADDRESS 1 = 0
INPUT ADDRESS 0 (LSB) = 0
1
UPDATE
1
MODE
DIN
MOST SIGNIFICANT BITS OF THE 7-BIT CONTROL WORD ARE SHIFTED IN FIRST; I.E. OUT15, THEN OUT14, ETC.
LAST 7 BITS SHIFTED IN PRIOR TO UPDATE FALLING EDGE PROGRAM OUT0.
The most straightforward technique for implementing
nonblocking matrices is to arrange the building blocks
in a grid. The inputs connect to each vertical bank of
devices in parallel with the other banks. The outputs of
each building block in a vertical column connect
together in a wired-OR configuration. Figure 6.shows a
128-input, 32-output, nonblocking array using eight
MAX4358 crosspoint devices.
The wire-OR connection of the outputs shown in the
diagram is possible because the outputs of the IC
devices can be placed in a disabled, or high-impedance-output state. This disable state of the output
buffers is designed for a maximum impedance vs. frequency while maintaining a low output capacitance.
These characteristics minimize the adverse loading
effects from the disabled outputs. Larger arrays are
constructed by extending this connection technique to
more devices.
Driving a Capacitive Load
Figure 6 shows an implementation requiring many outputs to be wired together. This creates a situation
where each output buffer sees not only the normal load
impedance, but also the disabled impedance of all the
other outputs. This impedance has a resistive and a
capacitive component. The resistive components
reduce the total effective load for the driving output.
Table 5. Output Selection Programming
Figure 6. 128 x 32 Nonblocking Matrix Using 32 x 16
Crosspoint Devices
Total capacitance is the sum of the capacitance of all
the disabled outputs and is a function of the size of the
matrix. Also, as the size of the matrix increases, the
length of the PC board traces increases, adding more
capacitance. The output buffers have been designed to
drive more than 30pF of capacitance while still maintaining a good AC response. Depending on the size of
the array, the capacitance seen by the output can
exceed this amount. There are several ways to improve
the situation. The first is to use more building-block
crosspoint devices to reduce the number of outputs
that need to be wired together (see Figure 7).
In Figure 7, the additional devices are placed in a second bank to multiplex the signals. This reduces the
number of wired-OR connections. Another solution is to
put a small resistor in series with the output before the
capacitive load to limit excessive ringing and oscillations. Figure 8 shows the graph of the Optimal Isolation
Table 6. Input Selection Programming
Figure 7. 128 x 16 Nonblocking Matrix with Reduced Capacitive
Loading
Figure 8. Optimal Isolation Resistor vs. Capacitive Load
INPUTS (0–31)
INPUTS (32–63))
INPUTS (64–95)
INPUTS (96–127)
32
IN
32
IN
32
IN
32
IN
MAX4358
MAX4358
MAX4358
MAX4358
OUT
OUT
OUT
OUT
16
16
16
IN
MAX4358
16
16
16
IN
OUT
16
OUTPUTS (0–15)
OPTIMAL ISOLATION RESISTANCE
vs. CAPACITIVE LOAD
30
25
20
15
10
ISOLATION RESISTANCE (Ω)
5
0
0500
200100300400
CAPACITIVE LOAD (pF)
B4
(MSB)
000000
000011
000102
000113
001004
001015
001106
001117
010008
010019
0101010
0101111
0110012
0110113
0111014
0111115
1000016
1000117
1001018
1001119
1010020
1010121
1011022
1011123
1100024
1100125
1101026
1101127
1110028
1110129
1111030
1111131
INPUT ADDRESS BIT
B3B2B1
B0
(LSB)
SELECTED
INPUT
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
Resistor vs. Capacitive Load. A lowpass filter is created
from the series resistor and parasitic capacitance to
ground. A single R-C do not affect the performance at
video frequencies, but in a very large system there may
be many R-Cs cascaded in series. The cumulative
effect is a slight rolling off of the high frequencies causing a "softening" of the picture. There are two solutions
to achieve higher performance. One way is to design
the PC board traces associated with the outputs such
that they exhibit some inductance. By routing the traces
in a repeating "S" configuration, the traces that are
nearest each other will exhibit a mutual inductance
increasing the total inductance. This series inductance
causes the amplitude response to increase or peak at
higher frequencies, offsetting the rolloff from the parasitic capacitance. Another solution is to add a smallvalue inductor to the output.
On-Screen Display Insertion
The MAX4358 facilitates the insertion of on-screen
graphics and characters by using the built-in fast 2:1
multiplexer associated with each of the 16 outputs
(Functional Diagram). This mux switches in 40ns, much
less than the width of a single pixel. Access to this fast
mux is through 16 dedicated OSDFILL analog inputs
and 16 dedicated OSDKEY input controls. OSD timing
is externally controlled and applied to the OSDKEY
inputs (Figure 1). Pulling OSDKEYilow switches the
signal on the OSDFILLiinput to the OUTioutput. When
the OSDKEY signal is logic high, the signal at IN_ is
switched to the output. This switching action is repeated on a pixel-by-pixel basis for each scan line. In this
way any synchronized video signal, including arbitrary
graphics, can be inserted on the screen (Figure 9).
This technique for inserting OSD display information is
an improvement over the way it has traditionally been
done. Other OSD techniques require an external fast
mux and a buffer for each output.
Crosstalk and Board Routing Issues
Improper signal routing causes performance problems.
The MAX4358 has a typical crosstalk rejection of
-62dB at 6MHz. A bad PC board layout degrades the
crosstalk rejection by 20dB or more. To achieve the
best crosstalk performance:
1.Place ground isolation between long critical signal
PC board trace runs. These traces act as a shield to
potential interfering signals. Crosstalk can be
degraded from parallel traces as well as directly
above and below on adjoining PC board layers.
Table 7. 7-Bit Serial Control Word Bit Assignments (Mode 1: Complete Matrix Mode
Programming)
Figure 9. Improved Implementation of On-Screen Display
BITNAMEFUNCTION
6 (MSB)Output EnableEnable bit for output, 0 = disable, 1 = enable.
5Gain SetGain Select for output buffer, 0 = gain of +1V/V, 1 = gain of +2V/V.
4Input Address 4MSB of input channel select address.
3Input Address 3
2Input Address 2
1Input Address 1
0 (LSB)Input Address 0LSB of input channel select address
many of the PC board traces as possible to be 75Ω
transmission lines. This lowers the impedance of the
traces reducing a potential source of crosstalk. More
power will be dissipated due to the output buffer driving a lower impedance.
3.Minimize ground current interaction by using a good
ground plane strategy.
In addition to crosstalk, another key issue of concern is
isolation. Isolation is the rejection of undesirable feedthrough from input-to-output with the output disabled.
The MAX4358 achieves a -110dB isolation at 6MHz by
selecting the pinout configuration such that the inputs
and outputs are on opposite sides of the package.
Coupling through the power supply is a function of the
quality and location of the supply bypassing. Use
appropriate low-impedance components and locate
them as close as possible to the IC. Avoid routing the
inputs near the outputs.
Power-Supply Bypassing
The MAX4358 operates from a single +5V or dual ±3V
to ±5V supplies. For single-supply operation, connect
all VEEpins to ground and bypass all power-supply
pins with a 0.1µF capacitor to ground. For dual-supply
systems, bypass all supply pins to ground with 0.1µF
capacitors.
Power in Large Systems
The MAX4358 has been designed to operate with split
supplies down to ±3V or a single supply of +5V.
Operating at the minimum supply voltages reduces the
power dissipation by as much 40% to 50%. At ±5V, the
MAX4358 consumes 195mW (0.38mW/point).
Driving a PC-Board Interconnect or Cable
(A
V
= +1V/V or +2V/V)
The MAX4358 output buffers can be programmed to
either AV= +1V/V or +2V/V. The +1V/V configuration is
typically used when driving short lengths (less than
3cm), high impedance, "local" PC board traces. To
drive a cable or a 75Ω transmission line trace, program
the gain of the output buffer to +2V/V and place a 75Ω
resistor in series with the output. The series termination
resistor and the 75Ω load impedance act as a voltage
divider that divides the video signal in half. Set the gain
to +2V/V to transmit a standard 1V video signal down a
cable. The series 75Ω resistor is called the backmatch, reverse termination, or series termination. This
75Ω resistor reduces reflections and provides isolation,
increasing the output capacitive driving capability.
Matrix Programming
The MAX4358’s unique digital interface simplifies programming multiple MAX4358 devices in an array.
Multiple devices are connected with DOUT of the first
Figure 10. Matrix Mode Programming
CHIP ADDRESS = 0CHIP ADDRESS = 1
DOUT
DIN
HOST
CONTROLLER
MAX4358
SCLK
CE
MODE
UPDATE
A3
A2
A1
A0
VIRTUAL SERIAL BUS (MODE 0: INDIVIDUAL OUTPUT ADDRESS MODE)
CHIP ADDRESS = 2
DIN
MAX4358
SCLK
CE
MODE
UPDATE
DOUT
A3
A2
V
A1
A0
DD
DOUTNEXT DEVICE
DIN
MAX4358
SCLK
CE
MODE
UPDATE
A3
V
A2
A1
A0
DD
MAX4358
32 x 16 Nonblocking Video Crosspoint Switch
with On-Screen Display Insertion and I/O Buffers
device connecting to DIN of the second device, and so
on (Figure 11). Two distinct programming modes,
Individual Output Address Mode (MODE = 0) and
Complete Matrix Mode (MODE = 1) are selected by
toggling a single MODE control pin high or low. Both
modes operate with the same physical board layout.
This allows initial programming of the IC by daisychaining and sending one long data word while still
being able to immediately address and update individual locations in the matrix.
Individual Output Address Mode
(Mode = 0)
In Individual Output Address Mode, the devices are
connected in a serial-bus configuration, with the data
routing gate (Figure 3) connecting DIN to DOUT, making each device a virtual node on the serial bus. A single 16-bit control word is sent to all devices
simultaneously. Only the device with the corresponding
chip address responds to the programming word and
updates its output. In this mode the chip address is set
via hardware pin strapping of A3–A0. The host communicates with the device by sending a 16-bit word consisting of 1 don’t care bit, 4-chip address bits, 11 bits of
data to make the word exactly two bytes in length. The
11 data bits are broken down into 4 bits to select the
output to be programmed, 1 bit to set the output
enable, 1 bit to set gain and 5 bits to the select the
input to be connected to that output. In this method, the
matrix is programmed one output at a time.
Complete Matrix Mode (Mode = 1)
In Complete Matrix Mode, the devices are connected in
a daisy-chain fashion where n 5112 bits are sent to
program the entire matrix, where n = the number of
MAX4358 devices connected in series. The data word
is structured such that the first bit is the LSB of the last
device in the chain and the last data bit is the MSB of
the first device in the chain. The total length of the data
word is equal to the number of crosspoint devices to be
programmed in series times 112 bits per crosspoint
device. This programming method is most often used
at start-up to initially configure the switching matrix.
Operating at +5V Single-Supply with
A
V
= +1V/V or +2V/V
The MAX4358 guarantees operation with a single +5V
supply and a gain of +1V/V for standard video-input
signals (1Vp-p). To implement a complete video matrix
switching system capable of gain = +2V/V while operating with a +5V single supply, combine the MAX4358
crosspoint switch with Maxim’s low-cost, high-performance video amplifiers optimized for single +5V supply
operation (Figure 11). The MAX4450 single and
MAX4451 dual op amps are unity-gain-stable devices
that combine high-speed performance with Rail-to-
Figure 11. Typical Single +5V Supply Application
+5V
V
CC
1V
IN0
IN1
OUT0
OUT1
IN31
AGNDV
OUT15
MAX4358
EE
P-P
U2
500Ω
500Ω
+5V
= 75Ω
Z
220µF
0
MONITOR 0
75Ω
2V
P-P
75Ω
U2 = MAX4450
OR 1/4 MAX4383
Rail®outputs. The common-mode input voltage range
extends beyond the negative power-supply rail (ground
in single-supply applications). The MAX4450 is available in the ultra-small 5-pin SC70 package, while the
MAX4451 is available in a space-saving 8-pin SOT23
package. The MAX4383 is a quad op amp available in
a 14-pin TSSOP package. The MAX4380/MAX4381/
MAX4382 and MAX4384 offer individual output-highimpedance disable making these amplifiers suitable for
wired-OR connections.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 43