Jim Pedicord Bryan J. Preeshl
Quality Assurance Quality Assurance
Reliability Lab Manager Executive Director
ConclusionThe MAX4172 successfully meets the quality and reliability standards required of all Maxim products. In addition,
Maxim’s continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim’s quality
and reliability standards.
Table of Contents
I. ........Device Description V. ........Quality Assurance Information
II. ........Manufacturing Information VI. .......Reliability Evaluation
III. .......Packaging Information
IV. .......Die Information ......Attachments
I. Device Description
A. General
The MAX4172 is a low-cost, precision, high-side current-sense amplifier for portable PCs, telephones, and
other systems where battery/DC power-line monitoring is critical. High-side power-line monitoring is
especially useful in battery-powered systems, since it does not interfere with the battery charger’s ground
path. Wide bandwidth and ground-sensing capability make the MAX4172 suitable for closed-loop battery charger and general-purpose current-source applications. The 0V and 32V input common-mode range is
independent of the supply voltage, which ensures that current-sense feedback remains viable, even when
connected to a battery in deep discharge.
To provide a high level of flexibility, the MAX4172 functions with an external sense resistor to set the range of
load current to be monitored. It has a current output that can be converted to a ground-referred voltage with a
single resistor, accommodating a wide range of battery voltages and currents.
An open-collector power-good output (/PG) indicates when the supply voltage reaches an adequate level to
guarantee proper operation of the current -sense amplifier. The MAX4172 operates with a 3.0V to 32V supply
voltage.
B. Absolute Maximum Ratings
Item Rating
V+, RS+, RS -, /PG -0.3V to +36V
OUT -0.3V to (V+ + 0.3V)
Differential Input Voltage, V
RS+
-V
±700mV
RS
Current into Any Pin ±50mAStorage Temp. -65°C to +150°C
Lead Temp. (10 sec.) +300°C
A. Description/Function: Low-Cost, Precision, High-Side Current -Sense Amplifier
B. Process: SG3 - Standard 3 micron silicon gate CMOS
C. Number of Device Transistors: 177
D. Fabrication Location: Oregon, USA
E. Assembly Location: Malaysia, Philippines or Thailand
F. Date of Initial Production: December, 1996
III. Packaging InformationA. Package Type: 8 Lead µMAX 8-Lead NSO B. Lead Frame: Copper Copper
C. Lead Finish: Solder Plate Solder Plate
D. Die Attach: Silver-filled Epoxy Silver-filled Epoxy
E. Bondwire: Gold (1.3 mil dia.) Gold (1.3 mil dia.)
F. Mold Material: Epoxy with silica filler Epoxy with silica filler
G. Assembly Diagram: Buildsheet # 05-3001-0063 Buildsheet # 05-3001-0062
H. Flammability Rating: Class UL94-V0 Class UL94-V0
I. Classification of Moisture Sensitivity
per JEDEC standard JESD22-A112: Level 1 Level 1
IV. Die Information
A. Dimensions: 84 x 58 mils
B. Passivation: Si3N4/SiO2 (Silicon nitride/ Silicon dioxide)
C. Interconnect: Aluminum/Si (Si = 1%)
D. Backside Metallization: None
E. Minimum Metal Width: 3 microns (as drawn)
F. Minimum Metal Spacing: 3 microns (as drawn)
G. Bondpad Dimensions: 5 mil. Sq.
H. Isolation Dielectric: SiO
2
I. Die Separation Method: Wafer Saw
V. Quality Assurance Information
A. Quality Assurance Contacts: Jim Pedicord (Reliability Lab Manager)
Bryan Preeshl (Executive Director of QA)
Kenneth Huening (Vice President)
B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet.
0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate: < 50 ppm
D. Sampling Plan: Mil-Std-105D
VI. Reliability EvaluationA. Accelerated Life Test
The results of the 135°C biased (static) life test are shown in Table 1. Using these results, the Failure
Rate (λ ) is calculated as follows:
λ = 1 = 1.83 (Chi square value for MTTF upper limit)
MTTF 192 x 4389 x 160 x 2
Temperature Acceleration factor assuming an activation energy of 0.8eV
λ = 6.79 x 10-9 λ = 6.79 F.I.T. (60% confidence level @ 25°C)
This low failure rate represents data collected from Maxim’s reliability qualification and monitor programs.
Maxim also performs weekly Burn-In on samples from production to assure reliability of its processes. The
reliability required for lots which receive a burn-in qualification is 59 F.I.T. at a 60% confidence level, which equates
to 3 failures in an 80 piece sample. Maxim performs failure analysis on rejects from lots exceeding this level. The
Burn-In Schematic 06-5243 shows the static circuit used for this test. Maxim also performs 1000 hour life test
monitors quarterly for each process. This data is published in the Product Reliability Report (RR-1M) located on
the Maxim website at http://www.maxim-ic.com .
B. Moisture Resistance Tests
Maxim evaluates pressure pot stress from every assembly process during qualification of each new design.
Pressure Pot testing must pass a 20% LTPD for acceptance. Additionally, industry standard 85°C/85%RH or
HAST tests are performed quarterly per device/package family.
C. E.S.D. and Latch-Up Testing
The OP11 die type has been found to have all pins able to withstand a transient pulse of ±400V, per Mil-
Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device
withstands a current of ±250mA and/or ±20V.
Table 1
Reliability Evaluation Test Results
MAX4172ExA
TEST ITEM TEST CONDITION FAILURE SAMPLE NUMBER OF
IDENTIFICATION PACKAGE SIZE FAILURES
Static Life Test (Note 1)
Ta = 135°CDC Parameters 160 0 Biased & functionality
Time = 192 hrs.
Moisture Testing (Note 2)
Pressure Pot Ta = 121°CDC Parameters uMax 77 0
P = 15 psi. & functionality NSO 77 0
RH= 100% Time = 168hrs.
85/85 Ta = 85°CDC Parameters 77 0
RH = 85% & functionality Biased Time = 1000hrs.
Mechanical Stress (Note 2)
Temperature -65°C/150°C DC Parameters 77 0
Cycle 1000 Cycles & functionality
Method 1010
Note 1: Life Test Data may represent plastic D. I.P. qualification lots.
Note 2: Generic Process/Package Data
Mil Std 883D
TERMINAL D
TABLE II. Pin combination to be tested. 1/ 2/
3.4 Pin combinations to be tested.
a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All
pins except the one being tested and the ground pin(s) shall be open.
b. Each pin individually connected to terminal A with respect to each different set of a combination of all named
power supply pins (e.g., V
tested and the power supply pin or set of pins shall be open.
c. Each input and each output individually connected to terminal A with respect to a combination of all the other input
and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of
all the other input and output pins shall be open.
Terminal A
(Each pin individually
connected to terminal A
with the other floating)
1. All pins except V
2. All input and output pins All other input -output pins
1/ Table II is restated in narrative form in 3.4 below.
2/ No connects are not to be tested.
3/ Repeat pin combination I for each named Power supply and for ground
(e.g., where V
is VDD, VCC, VSS, VBB, GND, +VS, -VS, V
PS1
, or V
SS1
Attachment #1
PS1
or V
SS2
SS3
3/
or V
CC1
, or V
Terminal B
(The common combinati on
of all like-named pins
connected to terminal B)
All V
pins
PS1
, etc).
REF
) connected to terminal B. All pins except the one being
CC2
Method 3015.7
Notice 8
REGULATED
HIGH VOLTAGE
SUPPLY
R1
TERMINAL C
S1
C1
S2
R2
DUT
SOCKET
TERMINAL A
SHORT
TERMINAL B
R = 1.5kΩΩ
C = 100pf
CURRENT
PROBE
(NOTE 6)
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