MAXIM MAX3987 User Manual
19-4973; Rev 2; 4/12
EVALUATION KIT
AVAILABLE
8.5Gbps Quad Equalizer and
Preemphasis Driver
General Description
The MAX3987 is a 4-channel receive and transmit equalizer (EQ). It compensates for transmission medium
losses encountered with FR4 stripline/microstrip and/or
high-speed cable. The device can be used at the beginning, middle, or end of a channel. The input equalization
requires no setting, and the output preemphasis (PE) is
programmable.
For each channel, the preemphasis level, output drive
level, output polarity, and powering down of unused outputs are programmable through an I2C serial interface. It
can also be configured globally through pins.
The device operates from a 2.5V or 3.3V supply, and is
packaged in a 7mm x 7mm, 48-pin TQFN.
Applications
Preemphasis and Receive Equalization
Redrive
FR4 and Cable Equalization
XAUI and XAUI2, Fibre Channel, Interlaken,
InfiniBand
TM/SM
, SAS-2 and SATA Revision 3 OOB
PCIe® Compatible
InfiniBand is a trademark/service mark of InfiniBand Trade
Association.
PCIe is a registered trademark of PCI-SIG Corp.
Typical Application Circuit
Features
S Up to 8.5Gbps NRZ Data Speed
S Receive Equalization Up to 30in FR4
S Preemphasis Drive Up to 30in FR4
S Global and Individual Programming of
Preemphasis, Output Drive Levels, Polarity
Inversion, and Offset Cancellation
S Signal Detect and Internal Output Squelch
S Compliant with SAS-2 and SATA Revision 3 OOB
S Coding Independent, 8B/10B, 64B/66B,
Scrambled, and Others
S Differential CML Data-Output Drive
S I2C Serial Interface and Pin Programmable
S Software Power-Down of Unused Outputs
S 0.5W Typical Power Dissipation for Drive Level 1
at VCC = 2.5V
S High-Performance, Lead-Free, 7mm x 7mm, 48-Pin
TQFN Package
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX3987ETM+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
-40NC to +85NC
48 TQFN-EP*
MAX3987
MAX3987
FABRIC
CARD
Rx Tx
SerDes SerDes
2in < L < 30in
_______________________________________________________________ Maxim Integrated Products 1
AS AN
EQUALIZER
MAX3987
AS A DRIVER
BACKPLANE
MIDPLANE
2in < L < 30in
LINE
CARD
RxTx
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
8.5Gbps Quad Equalizer and
Preemphasis Drive
ABSOLUTE MAXIMUM RATINGS
Termination Supply Voltage Range .....................-0.5V to +3.9V
Signal Voltage Range on Any One
Signal Wire (TTL) ................................. -0.5V to (VCC + 0.3V)
Signal Voltage Range on Any One
Signal Wire (CML) ................................ -0.5V to (VCC + 0.3V)
CML Output Loading (Shorted to Ground) ........................90mA
Operating Ambient Temperature Range ........... -40NC to +85NC
MAX3987
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
SPECIFICATION TABLES
(Typical values measured at VCC = 3.3V, TA = +25NC, unless otherwise specified.)
OPERATING CONDITIONS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage
(Note 1)
Operating Ambient
Temperature
Supply Noise Tolerance 100kHz < f < 200MHz 50 mV
AC Common-Mode Noise at the
Input
Bit Rate NRZ data (Note 2) 8.5 Gbps
CID Consecutive identical digits (bits) 100 Bits
Time to Reach 50% Mark/Space
Ratio
DC-Blocking Capacitor For bursty traffic such as SAS/SATA 12 nF
2.5V supply 2.375 2.5 2.625
3.3V supply 2.97 3.3 3.63
2.5V supply 0 +25 +85
3.3V supply -40 +25 +85
2MHz < f < 200MHz 150 mV
For continuous traffic 1
Continuous Power Dissipation (TA = +70NC)
48-Pin TQFN (derate 27.8mW/NC above +70NC) ............2.22W
Storage Ambient Temperature Range ............. -65NC to +150NC
ESD Human Body Model, Any Pin ................................. Q2000V
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
V
NC
P-P
P-P
Fs
SUPPLY CHARACTERISTICS: 2.5V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
Supply Current I
Inrush Current
Power-On Delay t
2 ______________________________________________________________________________________
CC
CC
DI
CC
POWERON
Four outputs in level 3 drive; squelch
turned on
Four outputs in level 3 drive; squelch
turned off
Four outputs in level 2 drive; squelch
turned on
Four outputs in level 2 drive; squelch
turned off
Four outputs in level 1 drive; squelch
turned on
Four outputs in level 1 drive; squelch
turned off
(Note 3) +10 %
(Note 3) 100 ms
-5% 2.5 +5% V
320 385
306 365
286 340
271 325
235 280
221 265
mA
8.5Gbps Quad Equalizer and
Preemphasis Drive
SUPPLY CHARACTERISTICS: 3.3V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
Supply Current I
Inrush Current
Power-On Delay t
CC
CC
DI
CC
POWERON
Four outputs in level 3 drive; squelch
turned on
Four outputs in level 3 drive; squelch
turned off
Four outputs in level 2 drive; squelch
turned on
Four outputs in level 2 drive; squelch
turned off
Four outputs in level 1 drive; squelch
turned on
Four outputs in level 1 drive; squelch
turned off
(Note 3) +10 %
(Note 3) 100 ms
LVCMOS INPUT
(ADDR[4:1], I2C_EN, SDSF, SQ, OC_EN, TX_EN, TX_LV0, TX_LV1, TX_PE0, TX_PE1, RESET, TEST.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input-Voltage High V
Input-Voltage Low V
Input Current I
IH, IIL
IH
IL
VCC = 2.5V ±5%, 3.3V ±10%
VCC = 2.5V ±5%, 3.3V ±10% -0.3
VIN = VCC or GND -200 +200
-10% 3.3 +10% V
0.7 x
V
CC
370 445
354 430
334 405
318 390
272 330
257 315
VCC +
0.3
0.3 x
V
CC
MAX3987
mA
V
V
FA
HIGH-SPEED INPUTS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Propagation Delay from Any
Input to Any Output
Output Channel-to-Channel
Delay Skew
Input Sensitivity at the Device
Pin (Note 5)
Residual Deterministic Jitter:
6.5Gbps (Notes 6, 7, 9)
_______________________________________________________________________________________ 3
t
PD
t
SKEW
V
SENSITIVITY
(Point B in
Figure 2)
DJ
RX
Output at level 3 250 ps
Output at level 3 (Note 4) 20 40 ps
Offset cancellation off 75
mV
Offset cancellation on 50
Less than 2in FR4 at the output; max
reach 24in FR4; Maxim stress pattern
(Note 8)
Less than 2in FR4 at the output; max
reach 30in FR4; PRBS7 pattern
0.1 0.2
UI
0.07
P-P
8.5Gbps Quad Equalizer and
Preemphasis Drive
HIGH-SPEED INPUTS (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Less than 2in FR4 at the output; max
Residual Deterministic Jitter:
7.5Gbps (Notes 6, 7, 9)
MAX3987
Residual Deterministic Jitter:
8.5Gbps (Notes 6, 7, 9)
DJ
DJ
RX
RX
reach 24in FR4; Maxim stress pattern
(Note 8)
Less than 2in FR4 at the output; max
reach 24in FR4; PRBS7 pattern
Less than 2in FR4 at the output; max
reach 20in FR4; Maxim stress pattern
(Note 8)
Less than 2in FR4 at the output; max
reach 20in FR4; PRBS7 pattern
0.12 0.26
UI
0.07
0.10 0.22
UI
0.1
Squelch-Deassert Voltage for
Slow Response Signal Detect
(Notes 8 to 11)
Squelch-Deassert Voltage for
Fast Response Signal Detect
(Notes 9, 11, 12, 13)
Squelch-Assert Voltage for Slow
Response Signal Detect
(Notes 8 to 11)
Squelch-Assert Voltage for Fast
Response Signal Detect
(Notes 9, 11, 12)
Signal Detect and Squelch
Delay (Note 14)
Voltage Input Swing Launched
Differentially at the Source
(Point A in Figure 2 before the
signal encountering any loss)
Input Resistance R
Differential Input Return Loss SDD11 TQFN, 100MHz to 4.25GHz 17 dB
V
SQ_DEAS_S
V
SQ_DEAS_F
V
SQ_AS_S
V
SQ_AS_F
t
SD_SQ
V
LAUNCH
IN
SDL = 0 120
SDL = 1 (default state) 170
SDL = 0 155
SDL = 1 (default state) 220
SDL = 0 50
SDL = 1 (default state) 100
SDL = 0 65
SDL = 1 (default state) 120
Slow-signal detect and squelch is
enabled (Note 8)
Fast-signal detect and squelch is
enabled (Note 12)
Offset cancellation off 400 1800
Offset cancellation on 200 1800
Between signal and V
CC
200
2.5 5.4
50
mV
mV
mV
mV
ns
mV
I
P-P
P-P
P-P
P-P
P-P
4 ______________________________________________________________________________________
HIGH-SPEED OUTPUTS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Residual Deterministic Jitter:
6.5Gbps
(Notes 6, 8, 9, 15, 16, 17)
Residual Deterministic Jitter:
7.5Gbps
(Notes 6, 8, 9, 15, 16, 17)
Residual Deterministic Jitter:
8.5Gbps
(Notes 6, 8, 9, 15, 16, 17)
Serial-Data Output Rise and
Fall Time
Differential Output Swing:
Level 1 Drive
Differential Output Swing:
Level 2 Drive
Differential Output Swing:
Level 3 Drive
Differential Output Swing:
Level 1 Drive
Differential Output Swing:
Level 2 Drive
Differential Output Swing:
Level 3 Drive
Differential Output Swing:
AC Output Disabled
AC Common-Mode Voltage
Change
DC Common-Mode Voltage
Change
DJ
DJ
DJ
tR/t
V
AC_OUT
V
AC_OUT
V
AC_OUT
V
AC_OUT
V
AC_OUT
V
AC_OUT
V
AC_OUT
V
AC_COM
V
DC_COM
TX
TX
TX
8.5Gbps Quad Equalizer and
Preemphasis Drive
MAX3987
PE = 00, up to 2in FR4; PE = 01, up to
10in FR4; PE = 10, up to 18in FR4;
PE = 11, up to 30in FR4; Maxim stress
pattern
PE = 00, up to 2in FR4; PE = 01, up to
10in FR4; PE = 10, up to 18in FR4;
PE = 11, up to 30in FR4; PRBS7 pattern
PE = 00, up to 2in FR4; PE = 01, up to
10in FR4; PE = 10, up to 16in FR4;
PE = 11, up to 24in FR4; Maxim stress
pattern
PE = 00, up to 2in FR4; PE = 01, up to
10in FR4; PE = 10, up to 16in FR4;
PE = 11, up to 24in FR4; PRBS7 pattern
PE = 00, up to 2in FR4; PE = 01, up to
10in FR4; PE = 10, up to 18in FR4; PE =
11, up to 24in FR4; Maxim stress pattern
PE = 00, up to 2in FR4; PE = 01, up to
10in FR4; PE = 10, up to 18in FR4; PE =
11, up to 24in FR4; PRBS7 pattern
F
20% to 80% of settled value; level 3
drive (Note 4)
When output is enabled; PE = 00;
VCC = 2.5V Q5% (Notes 4, 10)
When output is enabled; PE = 00;
VCC = 2.5V Q5% (Notes 4, 10)
When output is enabled; PE = 00;
VCC = 2.5V Q5% (Notes 4, 10)
When output is enabled; PE = 00;
VCC = 3.3V Q10% (Notes 4, 10)
When output is enabled; PE = 00;
VCC = 3.3V Q10% (Notes 4, 10)
When output is enabled; PE = 00;
VCC = 3.3V Q10% (Notes 4, 10)
When output is powered down; input at
7.5Gbps with D24.3 pattern
(Note 18) 40 mV
(Note 19) -25 +25 mV
30 50 ps
530 600 660 mV
740 840 930 mV
900 1000 1150 mV
530 630 730 mV
750 900 1050 mV
900 1100 1250 mV
0.15 0.20
0.09
0.15 0.23
0.12
0.10 0.15
0.06
50 mV
UI
UI
UI
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
_______________________________________________________________________________________ 5
8.5Gbps Quad Equalizer and
Preemphasis Drive
HIGH-SPEED OUTPUTS (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Average DC Offset Voltage
Change
Output Resistance R
Differential Output Return
Loss
MAX3987
Random Jitter t
Channel Isolation SDD
I2C CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-Level Input Voltage V
High-Level Input Voltage V
Low-Level Output Voltage V
SDATA Leakage Current I
Output Fall Time V
V
ILMAX
Input Current Each I/O Pin I
SCLK Clock Frequency f
Note 1: 2.5V covers 0NC to +85NC, and 3.3V covers -40NC to +85NC.
Note 2: With offset cancellation off, the minimum data rate is limited by the DC-blocking capacitor value; with offset cancellation
on, the minimum data rate is limited above 1Gbps.
Note 3: Supply voltage ramp-up time of less than 200Fs. Power-on delay interval measured from the 50% level of the final volt-
age at the device side of filter to 50% of final current. See Figure 1 for a typical supply filter.
Note 4: Guaranteed by design and characterization with a K28.7 pattern at 7.5Gbps, PE = 00.
Note 5: Minimum input amplitude to generate full output swing (PE = 00, squelch disabled). Guaranteed by design and charac-
terization with 1010 clock pattern at 6Gbps. Input sensitivity can be frequency dependent because of the input equalization network. Outputs reach within 90% of settled value at level 3 drive.
Note 6: Difference in deterministic jitter between reference data source and equalizer output. Residual DJ = Output DJ - Source
DJ. The deterministic jitter at the output of the transmission line must be from media-induced loss and not from clock
source modulation.
Note 7: Input signal at point A in Figure 2. No more than 2in FR4 at the output. PE setting = 00, output drive at level 3, offset can-
cellation off. Signal is applied differentially at input to a 6-mil wide, loosely coupled microstrip up to 30in.
Note 8: Maxim stress pattern is 464 bits: PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101.
Note 9: All four channels are populated with traffic of the same data pattern to the channel under test with outputs set at level 3.
Note 10: Guaranteed by test at 7.5Gbps.
Note 11: Less than 2in FR4 at the input and less than 2in FR4 at the output.
Note 12: Guaranteed at 1.5Gbps and 3Gbps.
Note 13: Tested with ALIGN (0) pattern at 6.0Gbps.
Note 14: For the channel under test, time from the input differential peak-to-peak level rising above the squelch-deassert voltage
(dropping below the squelch-assert voltage) to the output data reaching 90% of maximum differential peak-to-peak level
for input transition from idle to active (10% of maximum differential peak-to-peak level for inputs transition from active to
idle). Squelch of individual output is completed (see Figure 3).
Note 15: No more than 2in FR4 at the input. Output drive is applied differentially to a 6-mil wide, loosely coupled differential
microstrip up to 30in. Output measured at the point C in Figure 4. Input level = 100mV
IHMAX
to
DV
OFFSET
OUT
SD22
LEAKAGE
RJ
ISO
OL1
t
OF
SCL
(Note 20) -25 +25 mV
Between signal and VCC 50
100MHz to 4.25GHz; output on; PE = 11,
LV = 10
(Note 21) 1 ps
Up to 5GHz (Note 22) 38 dB
IL
IH
At IOL = 3mA sink current 0 0.4
IOL = 6mA 0 0.6
I2C output high 0 10
I
0.1VCC < VI < 0.9V
CC
-0.5
0.7 x
V
CC
60 250 ns
-10 +10
P-P
17 dB
.
0.3 x
V
CC
VCC +
0.5
400 kHz
P-P
I
RMS
V
V
V
FA
FA
6 ______________________________________________________________________________________
8.5Gbps Quad Equalizer and
Preemphasis Drive
Note 16: The output PE level is defined as the ratio of peak-to-peak voltage of a transition bit to the peak-to-peak voltage of a non-
transition bit.
Note 17: For lowest (level 1) drive, Tx DJ spec must be met for PE = 00 and 01 only.
Note 18: PE = maximum preemphasis, load is 50I ±1% at each side, output is configured for level 3 drive. The pattern is
11001100 (50% edge density) at 7.5Gbps. AC common-mode output is computed as:
V
where:
VP = time-domain voltage measured at true terminal
VN = time-domain voltage measured at complementary terminal
V
Note 19: The maximum difference in the average DC voltage (V
Note 20: The maximum difference in the average differential voltage (DC offset) component between data present and output on,
Note 21: Guaranteed by design and characterization with a K28.7 pattern at 7.5Gbps with 100mV
Note 22: Measured using a vector-network analyzer (VNA). The VNA detects the signal at the output of the victim channel. All
DC_COM
between data present and output on, and data absent and output squelched. PE = lowest preemphasis, load is 50I
±1% at each side, output is configured for level 3 drive.
and data absent and output squelched. PE = lowest preemphasis, load is 50I ±1% at each side, output is configured
for level 3 drive.
level 3 drive, offset cancellation off.
other inputs and outputs are terminated with 50I. The obtained value excludes the forward gain of the victim amplifier.
= DC common-mode voltage (VP + VN)/2
AC_COM
= ((VP + VN)/2 - V
DC_COM
- DC common-mode voltage (VP + VN)/2) component
DC_COM
)
input swing. Output set at
P-P
MAX3987
3.3V/2.5V
SUPPLY
Figure 1. Recommended Supply Filtering
100µF
1µF
0.1µF 100µF 0.1µF
V
CC
_______________________________________________________________________________________ 7
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