Maxim MAX3984UTE+, MAX3984 Datasheet

General Description

The MAX3984 is a single-channel, preemphasis driver
with input equalization that operates from 1Gbps to

10.3Gbps. It provides compensation for copper links,
such as 8.5Gbps Fibre Channel and 10.3Gbps
Ethernet, allowing spans of up to 10m with 24 AWG
cable. The driver provides four selectable preemphasis
levels, and the selectable input equalizer compensates
for up to 10in of FR-4 circuit board material at 10Gbps.

The MAX3984 also features SFP-compliant loss-of-sig­nal (LOS) detection and TX_DISABLE. Selectable out­put swing reduces EMI and power consumption. The
MAX3984 is packaged in a lead-free, 3mm x 3mm,
16-pin thin QFN and operates from a 0°C to +85°C tem­perature range.

Applications

Features

♦ Drives Up to 10m of 24 AWG Cable

♦ Drives Up to 30in of FR-4

♦ Selectable 1000mV

P-P

or 1200mV

P-P

Differential

Output Swing

♦ Selectable Output Preemphasis

♦ Selectable Input Equalization

♦ LOS Detection with Built-In Squelch

♦ Transmit Disable

♦ Hot Pluggable

MAX3984

1Gbps to 10Gbps Preemphasis Driver with

Receive Equalizer

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

19-0868; Rev 0; 7/07

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

+

Denotes a lead-free package.

*EP = Exposed pad.

Pin Configuration appears at end of data sheet.

Typical Operating Circuits continued at end of data sheet.

8.5Gbps Fibre Channel

10.3Gbps Ethernet

Active Cable Assemblies

STM-64

TX_DISABLE

PE1

IN_LEV

PE0

OUT_LEV

IN+

IN-

LOS

V

CC

OR

GND

GND

V

CC

+3.3V

OUT+

OUT-

MAX3984

0.01μF

0.01μF

LOS

PE1

IN_LEV

PE0

OUT_LEV

V

CC

OR

GND

GND

+3.3V

IN+

IN-

MAX3984

OUT+

OUT-

0.01μF

0.01μF

22pF

39Ω

22pF

0.01μF

0.01μF

39Ω

22pF

39Ω

22pF

39Ω

LOS

LOS

PE1

IN_LEV

PE0

OUT_LEV

IN+

IN-

V

CC

OR
GND

GND

+3.3V

OUT+

OUT-

MAX3984

0.01μF

0.01μF

LOS

PE1

IN_LEV

PE0

OUT_LEV

TX_DISABLE

V

CC

OR
GND

GND

V

CC

+3.3V

IN+

IN-

MAX3984

OUT+

OUT-

0.01μF

0.01μF

0.01μF

0.01μF

≤ 10m (24 AWG)

UP TO 10Gbps

COPPER CABLE

DIFFERENTIAL

100Ω TWIN-AX

ACTIVE CABLE ASSEMBLY

Tx+

Tx-

Rx+

Rx-

DISK

ENCLOSURE

SWITCH

OR

SERDES

≤ 5V

≥ 4.7kΩ

Rx+

Rx-

Tx+

Tx-

FABRIC SWTCH

SWITCH

OR

SERDES

≤ 5V

R

PULLUP

≥ 4.7kΩ

Typical Operating Circuits

PART

TEMP

RANGE

PIN-PACKAGE

MAX3984UTE+ 0°C to +85°C 16 Thin QFN-EP* T1633F-3

PKG

CODE

MAX3984

1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

OPERATING CONDITIONS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage Range (VCC).................................-0.5V to +4.1V

Continuous Output Current Range

(OUT+, OUT-) ...............................................-25mA to +25mA

Input Voltage Range (IN+, IN-) ..................-0.5V to (VCC+ 0.5V)

Logic Inputs Range (PE1, PE0,

TX_DISABLE, IN_LEV, OUT_LEV) ..........-0.5V to (V

CC

+ 0.5V)

LOS Open-Collector Supply Voltage Range

(with ≥ 4.7kΩ pullup) .........................................-0.5V to +5.5V

Storage Ambient Temperature Range (T

STG

) ...-55°C to +150°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V

Supply Noise Tolerance 1MHz  f < 2GHz 40 mV

Operating Ambient Temperature T

Bit Rate NRZ data 1.0 8.5 10.3 Gbps

Consecutive Identical Digits
(CID)

Input Swing (Measured
different ially at data source,
point A of Figure 2 and 3. Pins
LOS and TX_DISABLE are
floating.)

Time to Reach 50%
Mark/Space Ratio

CC

3.0 3.3 3.6 V

0 25 85 °C

A

CID (bits) 100 B its

IN_LEV = high, Figure 2;

4.25Gbps < data rate  10.3Gbps

IN_LEV = high, Figure 2;

1.25Gbps < data rate  4.25Gbps

IN_LEV = high, Figure 2;

1.0Gbps  data rate  1.25Gbps

IN_LEV = low, F igure 3;

1.0Gbps < data rate  10.3Gbps

1 μs

360 1200

360 1600

360 2400

100 360

P-P

mV

P-P

MAX3984

1Gbps to 10Gbps Preemphasis Driver with

Receive Equalizer

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)

Supply Current I

Inrush Current Beyond steady state supply current (Note 1) 10 mA

Power-On Delay (Note 1) 1 30 ms

EQUALIZER AND DRIVE SPECIFICATIONS

Input Return Loss S11 100MHz to 5GHz 10 dB

Input Resistance Measured differentially (Note 2) 85 100 115 

Different Output Swing
(Notes 3, 4)

Common-Mode Output (AC)
(Note 4)

Output Resistance R

Output Return Loss S22 100MHz to 5GHz 12 dB

Output Transition Time 20%
to 80%

Random Jitter (Note 4) Measured at point D in Figure 3 (Note 7) 0.8 ps

Output Preemphasis Figure 1 (Note 3)

Residua l Output Determinist ic
Jitter at 1.0Gbps
(Notes 4, 8, and 9)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CC

OUT

t

r

OUT_LEV = low, TX_DISABLE = low 100 124

OUT_LEV = high, TX _DISABLE = low 120 148

Measured differential ly at point B in Figure
2; TX_DISABLE = low, OUT_LEV = high,
PE1 = PE0 = high

Measured differential ly at point B in Figure
2; TX_DISABLE = low, OUT_LEV = low,
PE1 = PE0 = high

TX_DISABLE = high, PE1 = PE0 = high 10

Measured at point B in Figure 2;
TX_DISABLE = low, OUT_LEV = high (Note 5)

OUT+ or OUT-, single-ended 42 50 58 

, tf 20% to 80% (Note 6) 32 40 ps

PE1 PE0

0 0 3.5

0 1 6.5

1 0 9.5

1 1 13

Source to IN

6-mil, 10in of

FR-4

OUT to

load

3m,

24 AWG

5m,

24 AWG

7m,

24 AWG

10m,

24 AWG

PE1 PE0

0 0

0 1

1 0

1 1

1000 1300

800 1100

25 mV

0.02 UI

mV

mA

P-P

RMS

RMS

dB

P-P

MAX3984

1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Source to IN

Residua l Output Determinist ic
Jitter at 5.0Gbps
(Notes 4, 8, and 9)

Residua l Output Determinist ic
Jitter at 8.5Gbps
(Notes 4, 8, and 9)

Residua l Output Determinist ic
Jitter at 10Gbps
(Notes 4, 8, and 9)

Residua l Output Determinist ic
Jitter at 10.0Gbps
(Notes 4, 8, and 10)

Propagation Delay 230 ps

STATUS OUTPUT: LOS

LOS Deassert

LOS Assert IN_LEV = high (Note 11) 80

LOS Hysteresis (Note 4)

6-mil, 10in of

FR-4

Source to IN

6-mil, 10in of

FR-4

Source to IN

6-mil, 10in of

FR-4

10in of FR-4 at OUT±; no
cable; see Figure 3

IN_LEV = high (Note 11) 300

IN_LEV = low (Note 11) 100

IN_LEV = high (Note 11) 20

IN_LEV = low (Note 11) 10

OUT to

load

3m,

24 AWG

5m,

24 AWG

7m,

24 AWG

10m,

24 AWG

OUT to

load

3m,

24 AWG

5m,

24 AWG

7m,

24 AWG

10m,

24 AWG

OUT to

load

3m,

24 AWG

5m,

24 AWG

7m,

24 AWG

10m,

24 AWG

PE1 PE0

0 1

1 0

1 0

1 1

PE1 PE0

0 1

1 0

1 0

1 1

PE1 PE0

0 1

1 0

1 1

1 1

PE1 PE0

0 0

0.09 0.12 UI

0.15 0.20 UI

0.18 0.25 UI

0.10 UI

mV

mV

P-P

P-P

P-P

P-P

P-P

P-P

MAX3984

1Gbps to 10Gbps Preemphasis Driver with

Receive Equalizer

_______________________________________________________________________________________ 5

Note 1: Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured

from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or
above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are
limited to less than 100mV.

Note 2: IN+ and IN- are single-ended, 50Ω terminations to (V

CC

- 1.5V) ±0.2V.

Note 3: Load is 50Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Note 4: Guaranteed by design and characterization.
Note 5: PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω ±1% at each side. The pattern is 11001100 (50% edge den-

sity) at 10Gbps. AC common-mode output is computed as:

V

ACCM_RMS

= RMS[(VP+ VN) / 2) - V

DCCM

]
where:
V

P

= time-domain voltage measured at OUT+ with at least 10GHz bandwidth.
VN= time-domain voltage measured at OUT- with at least 10GHz bandwidth.
AC common-mode voltage (V

ACCM_RMS

) expressed as an RMS value.

DC common-mode voltage (V

DCCM

) = average DC voltage of (VP+ VN) / 2.

Note 6: Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within

2in of the output pins with Rogers 4350 dielectric, or equivalent, and ≥ 10-mil line width. For transition time, the 0% refer­ence is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state
level after four consecutive logic ones.

Note 7: Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mV

P-P

differential swing. IN_LEV = logic-low and PE0 =
PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz band­width) or equivalent. See Figure 3 for setup.

Note 8: Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Note 9: Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip

(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A
and the load jitter point D in Figure 2. The deterministic jitter (D

J

) at the output of the transmission line must be from media

induced loss and not from clock source modulation. D

J

is measured at point D of Figure 2.

Note 10: Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point

A and the load jitter point D in Figure 3. The deterministic jitter (D

J

) at the output of the transmission line must be from

media induced loss and not from clock source modulation. D

J

is measured at point D of Figure 3.

Note 11: Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input.
Note 12: True open-collector outputs. V

CC

= 0 and the external 4.7kΩ pullup resistor is connected to +5.5V.

ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)

LOS Open-Collector Current
Sink

LOS Response Time
(Note 4)

LOS Transition Time

CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV

Logic-High Voltage V

Logic-Low Voltage V

Logic-High Current I

Logic-Low Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LOS asserted 0 25 μA

LOS a sserted; VOL 0.4V 1.0 mA

(Note 12) 0 25 μA

Time from V
or rising above a ssert level to 50% point of
LOS output transition

Rise time or fal l time (10% to 90%);
pullup supply = 5.5V; external pullup
R  4.7 k

2.0 V

IH

0.8 V

IL

Current required to maintain logic-high state

IH

IL

> +2.0V

at V

IH

Current required to maintain logic-low state

< +0.8V

at V

IL

dropping below deassert level

IN

10 μs

200 ns

-150 μA

350 μA

MAX3984

Figure 1. TX Preemphasis in dB

Figure 2. Transmit Test Setup (The points labeled A, B, and D are referenced for AC parameter test conditions. Deterministic jitter
and eye diagrams measured at point D.)

1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer

6 _______________________________________________________________________________________

V

LOW_PPVHIGH_PP

A

SIGNAL

SOURCE

SMA CONNECTORS

⎡

⎛

V

⎢

PCB (FR-4)

⎜

⎢

V

⎝

⎣

PE(dB) = 20 log

TRANSMIT TEST SETUP

HIGH_PP

LOW_PP

⎡

⎛

⎢

⎜

⎢

⎝

⎣

MAX3984

6 MILS

1in ≤ L ≤ 10in L = 2in

L ≤ 1in

6 MILS

6 MILSIN OUT

B

24 AWG 100Ω TWIN-AX

SMA CONNECTORS

FR-4

ε

≤ 4.4

OSCILLOSCOPE OR

ERROR DETECTOR

D

4.0 ≤

R

tanδ = 0.022