The MAX3984 is a single-channel, preemphasis driver
with input equalization that operates from 1Gbps to
10.3Gbps. It provides compensation for copper links,
such as 8.5Gbps Fibre Channel and 10.3Gbps
Ethernet, allowing spans of up to 10m with 24 AWG
cable. The driver provides four selectable preemphasis
levels, and the selectable input equalizer compensates
for up to 10in of FR-4 circuit board material at 10Gbps.
The MAX3984 also features SFP-compliant loss-of-signal (LOS) detection and TX_DISABLE. Selectable output swing reduces EMI and power consumption. The
MAX3984 is packaged in a lead-free, 3mm x 3mm,
16-pin thin QFN and operates from a 0°C to +85°C temperature range.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage Range (VCC).................................-0.5V to +4.1V
Continuous Output Current Range
(OUT+, OUT-) ...............................................-25mA to +25mA
Input Voltage Range (IN+, IN-) ..................-0.5V to (VCC+ 0.5V)
Logic Inputs Range (PE1, PE0,
TX_DISABLE, IN_LEV, OUT_LEV) ..........-0.5V to (V
CC
+ 0.5V)
LOS Open-Collector Supply Voltage Range
(with ≥ 4.7kΩ pullup) .........................................-0.5V to +5.5V
Storage Ambient Temperature Range (T
STG
) ...-55°C to +150°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply Voltage V
Supply Noise Tolerance 1MHz f < 2GHz 40 mV
Operating Ambient Temperature T
Bit Rate NRZ data 1.0 8.5 10.3 Gbps
Consecutive Identical Digits
(CID)
Input Swing (Measured
different ially at data source,
point A of Figure 2 and 3. Pins
LOS and TX_DISABLE are
floating.)
Note 1:Supply voltage to reach 90% of final value in less than 100µs, but not less than 10µs. Power-on delay interval measured
from the 50% level of the final voltage at the filter’s device side to 50% level of final current. The supply is to remain at or
above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are
limited to less than 100mV.
Note 2:IN+ and IN- are single-ended, 50Ω terminations to (V
CC
- 1.5V) ±0.2V.
Note 3:Load is 50Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Note 4:Guaranteed by design and characterization.
Note 5:PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω ±1% at each side. The pattern is 11001100 (50% edge den-
sity) at 10Gbps. AC common-mode output is computed as:
V
ACCM_RMS
= RMS[(VP+ VN) / 2) - V
DCCM
]
where:
V
P
= time-domain voltage measured at OUT+ with at least 10GHz bandwidth.
VN= time-domain voltage measured at OUT- with at least 10GHz bandwidth.
AC common-mode voltage (V
ACCM_RMS
) expressed as an RMS value.
DC common-mode voltage (V
DCCM
) = average DC voltage of (VP+ VN) / 2.
Note 6:Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within
2in of the output pins with Rogers 4350 dielectric, or equivalent, and ≥ 10-mil line width. For transition time, the 0% reference is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state
level after four consecutive logic ones.
Note 7:Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mV
P-P
differential swing. IN_LEV = logic-low and PE0 =
PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz bandwidth) or equivalent. See Figure 3 for setup.
Note 8:Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Note 9:Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip
(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A
and the load jitter point D in Figure 2. The deterministic jitter (D
J
) at the output of the transmission line must be from media
induced loss and not from clock source modulation. D
J
is measured at point D of Figure 2.
Note 10: Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point
A and the load jitter point D in Figure 3. The deterministic jitter (D
J
) at the output of the transmission line must be from
media induced loss and not from clock source modulation. D
J
is measured at point D of Figure 3.
Note 11: Measured with 101010… pattern at 10Gbps with less than 1in of FR-4 at the input.
Note 12: True open-collector outputs. V
CC
= 0 and the external 4.7kΩ pullup resistor is connected to +5.5V.
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= 0°C to +85°C. Typical values are at TA= +25°C, VCC= +3.3V, unless otherwise noted.)
LOS Open-Collector Current
Sink
LOS Response Time
(Note 4)
LOS Transition Time
CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV
Logic-High Voltage V
Logic-Low Voltage V
Logic-High Current I
Logic-Low Current I
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LOS asserted 0 25 μA
LOS a sserted; VOL 0.4V 1.0 mA
(Note 12) 0 25 μA
Time from V
or rising above a ssert level to 50% point of
LOS output transition
Rise time or fal l time (10% to 90%);
pullup supply = 5.5V; external pullup
R 4.7 k
2.0 V
IH
0.8 V
IL
Current required to maintain logic-high state
IH
IL
> +2.0V
at V
IH
Current required to maintain logic-low state
< +0.8V
at V
IL
dropping below deassert level
IN
10 μs
200 ns
-150 μA
350 μA
MAX3984
Figure 1. TX Preemphasis in dB
Figure 2. Transmit Test Setup (The points labeled A, B, and D are referenced for AC parameter test conditions. Deterministic jitter
and eye diagrams measured at point D.)
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
The MAX3984 is composed of a receiver, a driver, and
an LOS detector with selectable threshold. Equalization
is provided in the receiver. Selectable preemphasis
and selectable output amplitude are included in the
transmitter. The MAX3984 also includes transmit disable control for the output.
Receiver
Data is fed into the MAX3984 through a CML input stage
and a selectable equalization stage. The fixed equalizer
in the receiver corrects for up to 10in of PCB loss on
FR-4 material at 10Gbps. The fixed equalizer can be
bypassed by setting the IN_LEV pin to a logic-low.
Driver
The driver includes four-state preemphasis to compensate for up to 10m of 24 AWG, 100Ω balanced cable,
or 30in of FR-4. The OUT_LEV pin selects the output
amplitude. When OUT_LEV is low, the peak-to-peak
amplitude is 1000mV
P-P
. When OUT_LEV is high, the
peak-to-peak amplitude is 1200mV
P-P
.
Loss of Signal (LOS)
Input LOS detection is provided. This is an open-collector output and requires an external pullup resistor
(≥ 4.7kΩ). The pullup resistors should be connected
from LOS to a supply in the +3.0V to +5.5V range. The
LOS output is not valid until power-up is complete.
PINNAMEFUNCTION
1 V
2 IN+ Positive Data Input, CML. This input is internally terminated with 50.
3 IN- Negative Data Input, CML. This input is internally terminated with 50.
4, 8, 9, 16 GND Circuit Ground
5 OUT_LEV
6 PE1
7 PE0
10 OUT- Negative Data Output, CML. This output is terminated with 50 to V
11 OUT+ Positive Data Output, CML. This output is terminated with 50 to V
12 V
13 TX_DISABLE
14 LOS
Power-Supply Connection for Inputs. Connect to +3.3V.
CC1
Output-Swing Control Input, LVTTL with 20k Internal Pullup. Set to TTL high or open for maximum
output swing, or set to TTL low for reduced swing.
Output Preemphasis Control Input, LVTTL with 10k Internal Pullup. This pin is the most significant
bit of the 2-bit preemphasis control. Set high or open to assert this pin.
Output Preemphasis Control Input, LVTTL with 10k Internal Pullup. This pin is the least significant
bit of the 2-bit preemphasis control. Set high or open to assert this pin.
Power-Supply Connection for Output. Connect to +3.3V.
CC2
Transmitter Disable Input, LVTTL with 10k Internal Pullup. When high or open, differential output is
less than 10mV
Loss-of-Signal Detect, Open-Collector TTL Output. Requires an external pullup 4.7k (+5.5V
maximum). This output sinks current when the input signal is above the LOS deassert level. To
disable squelch pull LOS to ground.
. Set low for normal operation.
P-P
CC2
CC2
.
.
Receive Equalization Control Input, LVTTL 40k Internal Pullup. Set to TTL high or open for higher
15 IN_LEV
— EP
LOS assert/deassert levels and 10in FR-4 compensation. Set to TTL low for lower LOS assert/deassert
levels and to bypass the FR-4 equalization.
Exposed Pad. For optimal thermal conductivity, this pad must be soldered to the circuit board
ground.
The IN_LEV pin sets the LOS assert and deassert levels. When IN_LEV is LVTTL high or open, the LOS
assert threshold is 300mV
P-P
. When IN_LEV is LVTTL
low, the LOS assert threshold is 100mV
P-P
.
TX_DISABLE provides manual control for turning the
output off. The MAX3984 has a squelch function that
disables the output when there is an LOS condition. To
disable the squelch function, connect LOS to ground
(see the
Squelch
section).
Applications Information
Squelch
The MAX3984 can automatically detect an incoming
signal and enable or disable the data outputs. To
enable squelch, the LOS pin must be connected to a
TTL high or V
CC
with a pullup resistor (≥ 4.7kΩ).
Internally, TX_DISABLE and LOS are connected through
an OR-gate to control the CML outputs. The outputs are
disabled if LOS asserts. To turn off the squelch function,
LOS must be pulled to TTL low. The output can also be
disabled when TX_DISABLE is forced high.
Figure 4. Functional Diagram
GND
MAX3984
IN_LEV
LVTTL
V
CC2
40kΩ
V
CC2
TX_DISABLE
LVTTL
V
CC2
10kΩ
V
CC2
OUT_LEV
LVTTL
V
CC2
20kΩ
V
CC2
PEOV
CC2
OUT+
OUT-
LOS
PE1
IN+
IN-
LVTTL
10kΩ
V
CC2
V
CC2
1
0
CMLCML
FIXED
EQUALIZER
PREEMPHASIS
SIGNAL
DETECT
LIMITER
22
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
Note 1: Load is 50Ω ±1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps.
Note 2: PE1 = PE0 = logic-high (maximum preemphasis), load is 50Ω ±1% at each side. The pattern is 11001100 (50% edge densi-
ty) at 10Gbps. AC common-mode output is computed as:
V
ACCM_RMS
= RMS[(VP+ VN) / 2) - V
DCCM
]
where:
V
P
= time-domain voltage measured at OUT+ with at least 10GHz bandwidth.
V
N
= time-domain voltage measured at OUT- with at least 10GHz bandwidth.
AC common-mode voltage (V
ACCM_RMS
) expressed as an RMS value.
DC common-mode voltage (V
DCCM
) = average DC voltage of (VP+ VN) / 2.
Note 3: Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mV
P-P
differential swing. IN_LEV = logic-low and PE0 = PE1
= logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz bandwidth) or
equivalent. See Figure 3 for setup.
Note 4: Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7.
Note 5: Input range selection is IN_LEV = logic-high for FR4 input equalization. Cables are unequalized, Amphenol Spectra-Strip
(160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A and
the load jitter point D in Figure 2. The deterministic jitter (D
J
) at the output of the transmission line must be from media
induced loss and not from clock source modulation. D
J
is measured at point D of Figure 2.
Table 1. Typical Characteristics at -40°C (continued)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Source to IN
Residua l Output Determinist ic
Jitter at 10Gbps (Notes 4, 5)
6-mil, 10in of
FR-4
OUT to
load
3m,
24 AWG
5m,
24 AWG
7m,
24 AWG
10m,
24 AWG
PE1 PE0
0 1
1 0
1 1
1 1
0.25 UI
P-P
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
Circuit board layout and design can significantly affect
the performance of the MAX3984. Use good high-frequency design techniques, including minimizing
ground inductance and using controlled-impedance
transmission lines on the data signals. Power-supply
decoupling should also be placed as close as possible
to the VCCpins. Always connect all VCCpins to a
power plane. Take care to isolate the input from the
output signals to reduce feed through.
Exposed-Pad Package
The exposed-pad, 16-pin thin QFN package incorporates features that provide a very low thermal resistance path for heat removal from the IC. The exposed
pad on the MAX3984 must be soldered to the circuit
board for proper thermal performance. Refer to Maxim
Application Note
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
E/2
AAAA
L
(NE - 1) X e
E2/2
E2
D2/2
b
C
L
D2
0.10 M C A B
L
E
(ND - 1) X e
e
C
L
k
C
L
C
L
A
A2
A1
L
MARKING
D/2
D
0.10 C0.08 C
12x16L QFN THIN.EPS
e
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
e
21-0136
1
I
2
MAX3984
1Gbps to 10Gbps Preemphasis Driver with
Receive Equalizer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
MIN.
0.70 0.75 0.80
A
b
0.25 0.30 0.35
2.90
D
2.90 3.00 3.10
E
e
0.35
L
ND
NE
0
A1
A2
k
0.25
8L 3x3
NOM. M
3.00 3.10
0.65 BSC.
0.55 0.75
8
2
2
0.02
0.20 REF
-
PKG
REF.MIN.
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED
0.05
AX.
12L 3x3
NOM. MAX.NOM.
0.70
0.20
2.90
2.90
0.50 BSC.
0.45
0
0.20 REF
-
0.25
0.75
0.25
3.00
3.00
0.55
0.02
12N
3
3
-
MIN.MAX.
0.80
0.30
2.90
3.10
3.10
0.65
0.30
0.05
-
0.25
0.10mm.
16L 3x3
0.70
0.20
2.90
0.50 BSC.
040.02
0.20 REF
0.75
0.25
3.00
3.00
0.40
EXPOSED PAD VARIATIONS
PKG.
0.80
0.30
3.10
3.10
0.50
16
4
0.05
-
-
CODES
TQ833-11.250.250.700.35 x 45°WEEC1.250.700.25
T1233-1
3
T1233-
T1233-4
T1633-20.95
T1633F-3
T1633FH-30.650.80 0.95
T1633-40.95
T1633-50.95
D2
MIN.
0.95
0.95
0.95
0.65
MAX.
NOM.
1.25
1.10
1.25
1.10
1.251.10
1.25
1.10
0.95
0.80
1.10 1.250.95 1.10
1.25
1.10
E2
NOM.
MIN.
0.95
0.95 1.100.35 x 45°1.25WEED-1
0.95
0.65
0.650.80
MAX.
1.10
1.25
1.100.95
1.10
1.25
0.80
0.95
0.95
1.25
1.25
1.10
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
ID
PIN
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.225 x 45°
0.225 x 45°
0.35 x 45°
0.35 x 45°
JEDEC
WEED-1
WEED-11.25
WEED-2
WEED-2
WEED-2
WEED-2
WEED-20.95
21-0136
2
I
2
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