The MAX395 8-channel, serially controlled, single-pole/single-throw (SPST) analog switch offers eight separately
controlled switches. The switches conduct equally well in
either direction. On-resistance (100Ω max) is matched
between switches to 5Ω max and is flat (10Ω max) over
the specified signal range.
These CMOS devices can operate continuously with
dual power supplies ranging from ±2.7V to ±8V or a
single supply between +2.7V and +16V. Each switch
can handle rail-to-rail analog signals. The off leakage
current is only 0.1nA at +25°C or 5nA at +85°C.
Upon power-up, all switches are off, and the internal shift
registers are reset to zero. The MAX395 is electrically
equivalent to two MAX391 quad switches controlled by a
serial interface, and is pin compatible with the MAX335.
The serial interface is compatible with SPI™/QSPI™ and
____________________________Features
♦ SPI™/QSPI™, Microwire™-Compatible Serial
Interface
♦ 8 Separately Controlled SPST Switches
♦ 100Ω Signal Paths with ±5V Supplies
♦ Rail-to-Rail Signal Handling
♦ Asynchronous RESET
♦ Pin Compatible with Industry-Standard MAX335
♦ ±2.7V to ±8V Dual Supplies
+2.7V to +16V Single Supply
♦ >2kV ESD Protection per Method 3015.7
♦ TTL/CMOS-Compatible Inputs (with +5V or
±5V Supplies)
Input
Microwire™. Functioning as a shift register, it allows data
(at DIN) to be clocked in synchronously with the rising
edge of clock (SCLK). The shift register’s output (DOUT)
enables several MAX395s to be daisy chained.
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring both TTL- and CMOS-logic compatibility when using
±5V supplies or a single +5V supply.
________________________Applications
Serial Data-Acquisition Industrial and ProcessSystemsControl Systems
AvionicsATE Equipment
Audio Signal RoutingNetworking
__________________Pin Configuration
TOP VIEW
SCLK
1
V+
DIN
GND
NO0
COM0
NO1
COM1
NO2
COM2
NO3
COM3
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
V+ to V-...................................................................-0.3V, +17V
SCLK, CS
NO, COM.................................................(V- - 2V) to (V+ + 2V)
Continuous Current into Any Terminal..............................±30mA
MAX395
Peak Current, NO_ or COM_
(pulsed at 1ms,10% duty cycle)..................................±100mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
, DIN, DOUT, RESET .................-0.3V to (V+ + 0.3V)
MAX395C_ G .......................................................0°C to +70°C
MAX395E_ G ....................................................-40°C to +85°C
MAX395MRG..................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
ELECTRICAL CHARACTERISTICS—Dual Supplies
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, TA= T
SYMBOLPARAMETER
ANALOG SWITCH
Analog Signal Range
COM, NO On-Resistance
COM, NO On-Resistance Match
Between Channels (Note 2)
COM, NO On-Resistance
Flatness (Note 2)
NO Off Leakage Current
(Note 3)
COM Off Leakage Current
(Note 3)
COM On Leakage Current
(Note 3)
DIGITAL I/O
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold High
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold Low
DIN, SCLK, CS, RESET Input
Current Logic High or Low
DOUT Output Voltage Logic High
DOUT Output Voltage Logic Low
SCLK Input Hysteresis
COM
R
ON
∆R
ON
R
FLAT(ON)
I
NO(OFF)
I
COM(OFF)
COM(ON)
IH
IL
IH, IIL
DOUT
DOUT
to T
MIN
MAX
, V
NO
V+ = 5V, V- = -5V,
V
= ±3V, INO= 1mA
COM
V+ = 5V, V- = -5V,
V
= ±3V, INO= 1mA
COM
V+ = 5V, V- = -5V, INO= 1mA,
V
= -3V, 0V, 3V
COM
V+ = 5.5V, V- = -5.5V,
V
= -4.5V, VNO= 4.5V
COM
V+ = 5.5V, V- = -5.5V,
V
= 4.5V, VNO= -4.5V
COM
V+ = 5.5V, V- = -5.5V,
V
= -4.5V, VNO= 4.5V
COM
V+ = 5.5V, V- = -5.5V,
V
= 4.5V, VNO= -4.5V
COM
V+ = 5.5V, V- = -5.5V,
V
= VNO= ±4.5V
COM
V
, V
DIN
SCLK
VCS= 0.8V or 2.4V
I
= 0.8mA
DOUT
I
= -1.6mA
DOUT
HYST
, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONSUNITS
C, E, M
TA= +25°C
C, E, M
TA= +25°C5
C, E, M
TA= +25°C10
C, E, M
TA= +25°C-0.10.0020.1
C, E, M
TA= +25°C-0.10.0020.1
C, E, M
TA= +25°C-0.10.0020.1
C, E, M
TA= +25°C0.10.0020.1
C, E, M
TA= +25°C-0.20.010.2
C, E, M
SCLK Low Time
Data Setup Timet
Data Hold Time
DIN Data Valid after Falling SCLK
(Note 4)
Rise Time of DOUT (Note 4)t
Allowable Rise Time at DIN, SCLK
(Note 4)
Fall Time of DOUT (Note 4)t
Allowable Fall Time at DIN, SCLK
(Note 4)
RESET Minimum Pulse Widtht
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
Note 7: Between any two switches. See Figure 3.
= R
ON
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
ON(max)
- R
ON(min)
SCLK
t
CH +tCL
t
CSS
CSH2
t
CH
t
CL
DS
t
DH
t
DO
DR
t
SCR
DF
t
SCF
RW
. On-resistance match between channels and on-resistance flatness are guaranteed only with
10VCOM/VNO
to T
MIN
50% of SCLK to 10% of DOUT,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
, unless otherwise noted. Typical values are at TA= +25°C.)
CS Lead Time (Note 4)
CS Lag Time (Note 4)t
SCLK High Time (Note 4)
SCLK Low Time (Note 4)
Data Setup Time (Note 4)t
Data Hold Time (Note 4)
DIN Data Valid after Falling SCLK
(Note 4)
Rise Time of DOUT (Note 4)t
Allowable Rise Time at DIN,
SCLK (Note 4)
Fall Time of DOUT (Note 4)
Allowable Fall Time at DIN,
SCLK (Note 4)
RESET Minimum Pulse Widtht
to T
MIN
SCLK
t
CH +tCL
t
CSS
CSH2
t
t
t
t
t
SCR
t
SCF
, unless otherwise noted. Typical values are at TA= +25°C.)
MAX
CONDITIONS
CH
CL
DS
DH
DO
DR
DF
RW
50% of SCLK to 10% of
DOUT, CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
TA= +25°C
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
MINTYPMAX
(Note 2)
02.1MHz
480
240ns
240ns
190
190ns
20017ns
0-17
85
70nsTA= +25°C
UNITS
400
100ns
2µs
2µs
ns
ns
ns
ns
ns100t
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
Note 7: Between any two switches. See Figure 3.
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
ON(max)
- R
. On-resistance match between channels and on-resistance flatness are guaranteed only with
ON(min)
, V
10VCOM/VNO
= output. NO = input to off switch.
COM
Serially Controlled, Low-Voltage,
8-Channel SPST Switch
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +3.0V to +3.6V, V- = 0V, TA= T
ANALOG SWITCH
COM, NO On-Resistance
NO Off Leakage Current
(Notes 4, 5)
COM Off Leakage Current
(Notes 4, 5)
COM On Leakage Current
(Notes 4, 5)
DIGITAL I/O
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold High
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold Low
DIN, SCLK, CS, Input
Current Logic High or Low
DOUT Output Voltage Logic High
DOUT Output Voltage Logic Low
SCLK Input Hysteresis
SWITCH DYNAMIC CHARACTERISTICS
Turn-On Time
Turn-Off Time
Break-Before-Make Delay
Charge Injection (Note 4)
Off Isolation (Note 6)
Channel-to-Channel Crosstalk
(Note 7)
POWER SUPPLY
to T
MIN
SYMBOLPARAMETER
, V
COM
R
ON
NO(OFF)
I
COM(OFF)
COM(ON)
IH
IL
IH, IIL
DOUT
DOUT
t
ON
t
OFF
BBM
CTE
ISO
CT
I+V+ Supply Current
, unless otherwise noted. Typical values are at TA= +25°C.)
CS Lead Time (Note 4)
CS Lag Time (Note 4)t
SCLK High Time (Note 4)
SCLK Low Time (Note 4)
Data Setup Time (Note 4)t
Data Hold Time (Note 4)
DIN Data Valid after Falling SCLK
(Note 4)
Rise Time of DOUT (Note 4)t
Allowable Rise Time at DIN,
SCLK (Note 4)
Fall Time of DOUT (Note 4)t
Allowable Fall Time at DIN,
SCLK (Note 4)
RESET Minimum Pulse Widtht
to T
MIN
SCLK
t
CH +tCL
t
CSS
CSH2
t
t
t
t
t
SCR
t
SCF
, unless otherwise noted. Typical values are at TA= +25°C.)
MAX
CONDITIONS
CH
CL
DS
DH
DO
DR
DF
RW
50% of SCLK to 10% of
DOUT, CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
20% of V+ to 70% of V+,
CL= 10pF
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
TA= +25°C
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
MINTYPMAX
(Note 2)
02.1MHz
480
240ns
240ns
190
190ns
20038ns
0-38
150
105nsTA= +25°C
UNITS
400
300ns
2µs
300ns
2µs
ns
ns
ns
ns
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
Note 7: Between any two switches. See Figure 3.
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
ON(max)
- R
. On-resistance match between channels and on-resistance flatness are guaranteed only with
Ground. Connect to digital ground. (Analog signals have no ground reference;
they are limited to V+ and V-.)
Reset Input. Connect to digital (logic) supply (or V+). Drive low to set all switches off and set internal shift registers to 0.
MAX395 TOC12
8
Serially Controlled, Low-Voltage,
8-Channel SPST Switch
_______________Detailed Description
The MAX395’s interface can be thought of as an 8-bit
shift register controlled by CS (Figure 2). While CS is
low, input data appearing at DIN is clocked into the
shift register synchronously with SCLK’s rising edge.
The data is an 8-bit word, each bit controlling one of
eight switches in the MAX395 (Table 1). DOUT is the
shift register’s output, with data appearing synchronously with SCLK’s falling edge. Data at DOUT is simply the input data delayed by eight clock cycles.
When shifting the input data, D7 is the first bit in and
out of the shift register. While shifting data, the switches
remain in their previous configuration. When the eight
bits of data have been shifted in, CS is driven high. This
updates the new switch configuration and inhibits further data from entering the shift register. Transitions at
DIN and SCLK have no effect when CS is high, and
DOUT holds the first input bit (D7) at its output.
More or less than eight clock cycles can be entered
during the CS low period. When this happens, the shift
CS
t
CSH0
SCLK
DIN
Basic Operation
t
CSS
t
t
CH
DS
t
DH
t
DO
register will contain only the last eight serial data bits,
regardless of when they were entered. On the rising
edge of CS
, all the switches will be set to the corre-
sponding states.
The MAX395’s three-wire serial interface is compatible
with SPI™, QSPI™, and Microwire™ standards. If interfacing with a Motorola processor serial interface, set
CPOL = 0. The MAX395 is considered a slave device
(Figures 2 and 3). Upon power-up, the shift register
contains all zeros, and all switches are off.
The latch that drives the analog switch is updated on
the rising edge of CS, regardless of SCLK’s state. This
meets all the SPI and QSPI requirements.
Daisy Chaining
For a simple interface using several MAX395s, “daisy
chain” the shift registers as shown in Figure 5. The CS
pins of all devices are connected together, and a
stream of data is shifted through the MAX395s in series.
When CS is brought high, all switches are updated
simultaneously. Additional shift registers may be included anywhere in series with the MAX395 data chain.
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
XXXXX11XSwitch 0 closed (on)X
D5
X
XX
X
X
0
1
X
X
X
X
X
X
X
X
X
DATA BITS
D4
X
X
XX
X
X
X
0
1
X
X
X
X
X
X
X
When several serial devices are configured as slaves,
Addressable Serial Interface
addressable by the processor, DIN pins of each
decode logic individually control CS of each slave
device. When a slave is selected, its CS pin is driven
low, data is shifted in, and CS is driven high to latch the
data. Typically, only one slave is addressed at a time.
DOUT is not used.
__________Applications Information
The MAX395 can be used as a multiplexer, but to
obtain the same electrical performance with slightly
improved programming speed, use the MAX349 8channel mux or the MAX350 dual 4-channel mux, both
in 18-pin packages.
D3
X
XX
X
X
X
X
X
X
0
1
X
X
X
X
X
D2
D1
X
X
XX
X
X
X
X
X
X
X
0
1
X
X
X
X
XX
X
X
X
X
X
X
X
X
X
X
0
1
X
D0
X
X
XX
X
X
X
X
X
X
X
X
X
X
X
0
FUNCTION
All switches open, D7–D0 = 0
Switch 7 open (off)
Switch 7 closed (on)
Switch 6 open (off)
Switch 6 closed (on)
Switch 5 open (off)
Switch 5 closed (on)
Switch 4 open (off)
Switch 4 closed (on)
Switch 3 open (off)
Switch 3 closed (on)
Switch 2 open (off)
Switch 2 closed (on)
Switch 1 open (off)
Switch 1 closed (on)
Switch 0 open (off)
To use the MAX395 as an 8x1 multiplexer, connect all
8x1 Multiplexer
common pins together (COM0–COM7) to form the mux
output; the mux inputs are NO0–NO7.
The mux can be programmed normally, with only one
channel selected for every eight clock pulses, or it can
be programmed in a fast mode, where channel changing occurs on each clock pulse. In this mode, the channels are selected by sending a single high pulse
(corresponding to the selected channel) at DIN, and a
corresponding CS low pulse for every eight clock pulses. As this is clocked through the register by SCLK,
each switch sequences one channel at a time, starting
with Channel 7.
SCLK
MAX395
DIN
DOUT
CS
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX395, BUT MAY BE USED FOR DATA-ECHO PURPOSES.
Figure 3. Connections for Microwire
SK
SO
SI
I/O
MICROWIRE
PORT
Dual, Differential 4-Channel Multiplexer
To use the MAX395 as a dual (4x2) mux, connect
COM0–COM3 together and connect COM4–COM7
together, forming the two outputs. The mux input pairs
become NO0/NO4, NO1/NO5, NO2/NO6, and NO3/NO7.
The mux can be programmed normally, with only one
differential channel selected for every eight clock pulses, or it can be programmed in a fast mode, where
channel changing occurs on each clock pulse.
In fast mode, the channels are selected by sending two
high pulses spaced four clock pulses apart (corresponding to the two selected channels) at DIN, and a
corresponding CS low pulse for each of the first eight
clock pulses. As this is clocked through the register by
DOUT
MAX395
DIN
SCLK
CS
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX395, BUT MAY BE USED FOR DATA-ECHO PURPOSES.
SCLK, each switch sequences one differential channel
at a time, starting with channel 7/0. After the first eight
bits have been sent, subsequent channel sequencing
can occur by repeating this sequence or, even faster,
by sending only one DIN high pulse and one CS low
pulse for each four clock pulses.
SPDT Switches
To use the MAX395 as a quad, single-pole/doublethrow (SPDT) switch, connect COM0 to NO1, COM2 to
NO3, COM4 to NO5, and COM6 to NO7, forming the
four “common” pins. Program these four switches with
pairs of instructions, as shown in Table 2.
CS
MAX395
SCLK
DIN
CS
MAX395
SCLK
DIN
Reset Function
RESET is the internal reset pin. It is usually connected
to a logic signal or V+. Drive RESET low to open all
switches and set the contents of the internal shift register to zero simultaneously. When RESET is high, the
part functions normally and DOUT is sourced from V+.
RESET must not be driven beyond V+ or GND.
Power-Supply Considerations
The MAX395 construction is typical of most CMOS analog switches. It has three supply pins: V+, V-, and
GND. V+ and V- are used to drive the internal CMOS
switches and to set the limits of the analog voltage on
any switch. Reverse ESD-protection diodes are internally connected between each analog signal pin and
both V+ and V-. If any analog signal exceeds V+ or V-,
one of these diodes will conduct. During normal operation, these (and other) reverse-biased ESD diodes leak,
forming the only current drawn from V+ or V-.
Virtually all the analog leakage current is through the
ESD diodes. Although the ESD diodes on a given signal pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages vary as the signal varies. The difference in the
two diode leakages to the V+ and V- pins constitutes
the analog signal-path leakage current. All analog leak-
X
1
0
X
X
X
X
XXXXX110Switch 1 off and 0 onX
XXXXX101Switch 0 off and 1 onX
D5
X
X
X
0
1
X
X
age current flows to the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of either the same or
opposite polarity.
There is no connection between the analog signal
paths and GND.
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic limits. The logic-level translators convert the logic levels to
switched V+ and V- signals to drive the analog signal
gates. This drive signal is the only connection between
the logic supplies (and signals) and the analog supplies. V+, and V- have ESD-protection diodes to GND.
The logic-level inputs and output have ESD protection
to V+ and to GND.
The logic-level thresholds are CMOS and TTL compatible when V+ is +5V. As V+ is raised, the threshold
increases slightly. So when V+ reaches +12V, the
threshold is about 3.1V; slightly above the TTL guaranteed high-level minimum of 2.8V, but still compatible
with CMOS outputs.
The MAX395 operates with bipolar supplies between
±3.0V and ±8V. The V+ and V- supplies need not be
symmetrical, but their sum cannot exceed the absolute
maximum rating of 17V. Do not connect the MAX395
V+ to +3V and connect the logic-level pins to TTL
logic-level signals. This exceeds the absolute maximum ratings and can damage the part and/or external circuits.
DATA BITS
D4
X
X
X
1
0
X
X
D3
Bipolar Supplies
D2
X
X
X
X
X
0
1
X
X
X
X
X
1
0
D1
X
X
X
X
X
X
X
D0
X
X
X
X
X
X
X
FUNCTION
All switches open, D7–D0 = 0
Switch 7 off and 6 on
Switch 6 off and 7 on
Switch 5 off and 4 on
Switch 4 off and 5 on
Switch 3 off and 2 on
Switch 2 off and 3 on
The MAX395 operates from a single supply between
+3V and +16V when V- is connected to GND. All of the
bipolar precautions must be observed.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat up
to 50MHz (see
Typical Operating Characteristics)
Above 20MHz, the on-response has several minor
peaks that are highly layout dependent. The problem is
not turning the switch on, but turning it off. The off-state
switch acts like a capacitor and passes higher frequencies with less attenuation. At 10MHz, off isolation is
about -45dB in 50Ω systems, becoming worse (approximately 20dB per decade) as frequency increases.
Higher circuit impedances also make off isolation
worse. Adjacent channel attenuation is about 3dB
above that of a bare IC socket, and is due entirely to
capacitive coupling.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600