VCC ....................................................................... -0.3V to +4.0V
Voltage Range at SDA, SCL, CSEL,
LOS, CAZ, RPMIN ................................. -0.3V to (V
Voltage Range at ROUT+, ROUT- ........(V
Voltage Range at RIN+, RIN- ........ (V
Current Range Into LOS ...................................... -1mA to +5mA
Current Range Into SDA ..................................... -1mA to +1mA
MAX3945
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
- 2V) to (VCC + 0.3V)
CC
- 1.7V) to (VCC + 0.3V)
CC
+ 0.3V)
CC
Current Out of ROUT+, ROUT- ..........................................40mA
Operating Junction Temperature Range ......... -55NC to +150NC
Storage Temperature Range ............................ -65NC to +160NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
= +70NC)
A
ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, C
are set to default values, unless otherwise noted. Typical values are at V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY
Includes the CML output current,
V
DIFF_ROUT
Power-Supply Current I
Power-Supply VoltageV
Power-Supply Noise
GENERAL
Input Data Rate1.0610.3211.3Gbps
Input/Output SNR14.1
BER10E-12
POWER-ON RESET (POR)
POR Deassert Threshold2.552.75V
POR Assert Threshold2.32.45V
INPUT SPECIFICATIONS
Differential Input Resistance
RIN+/RIN-
Input Sensitivity
(Note 1)
Input OverloadV
Input Return Loss
RPMIN Input-Current HighI
CC
CC
R
IN_DIFF
V
INMIN
INMAX
SDD11
SCC11
IH
LOS1_EN = 1, LOS2_EN = 0
Includes the CML output current,
V
DIFF_ROUT
LOS1_EN = 0, LOS2_EN = 1
f < 10MHz100
10MHz < f < 20MHz10
RATE_SEL = 1, input transition time 25ps,
10.32Gbps, PRBS23-1 pattern
RATE_SEL = 0, input transition time 260ps,
1.25Gbps, K28.5 pattern
DUT is powered on, f P 5GHz
DUT is powered on, f P 16GHz
DUT is powered on, 1GHz < f P 5GHz
DUT is powered on, 1GHz < f P 16GHz
(VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, C
are set to default values, unless otherwise noted. Typical values are at V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
External RPMIN Filter Capacitor100pF
OUTPUT SPECIFICATIONS
Differential Output Resistance
ROUT+/ROUT-
Output Return Loss
Differential Output-Voltage High
Differential Output-Voltage
Medium
SET_CML DAC Range60255Decimal
Differential Output Signal When
Squelched (Note 1)
Data Output Transition Time
(20% to 80%) (Note 1)
TRANSFER CHARACTERISTICS
Deterministic Jitter
(Notes 1, 2)
R
OUTDIFF
SDD22
SCC22
t
R/tF
DJ
DUT is powered on, f P 5GHz
DUT is powered on, f P 16GHz
DUT is powered on, 1GHz < f P 5GHz
DUT is powered on, 1GHz < f P 16GHz
5mV
P VIN P 1200mV
P-P
SET_CML[7:0] = 169d (decimal)
10mV
SET_CML[7:0] = 181d
10mV
RATE_SEL = 1, SET_CML[7:0] = 91d
Outputs AC-coupled, SET_CML[7:0] =
181d, at 8.5Gbps, SQ_EN = 1
60mV
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 25ps,
pattern 11110000
10mV
RATE_SEL = 0, V
input transition time 260ps, pattern 11110000
10mV
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 28ps
60mV
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 28ps
60mV
RATE_SEL = 1, V
RXDE_EN = 0, input transition time 28ps
(VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, C
are set to default values, unless otherwise noted. Typical values are at V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Input = 60mV
Random Jitter
(Note 1)
MAX3945
Low-Frequency Cutoff
(Simulated Value)
Small-Signal Bandwidth
(Simulated Value)
Rx INPUT-BASED LOS SPECIFICATIONS (LOS1_EN = 1 and LOS2_EN = 0) (Note 1)
LOS Assert Sensitivity Range(Note 3)1477mV
SET_LOS DAC Range763Decimal
LOS Hysteresis10log(V
LOS Assert/Deassert Time(Note 4)2.32080
Low Assert Level
Low Deassert Level141822
Medium Assert Level
Medium Deassert Level658295
High Assert Level
High Deassert Level127158182
LOS Output Masking Time
Range
LOS Output Masking DAC
Resolution
RSSI MONITOR-BASED LOS SPECIFICATIONS (LOS1_EN = 0 and LOS2_EN = 1) (Note 1)
LOS Assert Sensitivity Range(Note 5)8.390mV
SET_LOS DAC Range463Decimal
LOS Hysteresis10log(V
LOS Assert/Deassert Time(Note 4)2.32080
Low Assert Level
Low Deassert Level9.010.812.7
Medium Assert Level
Medium Deassert Level778592
High Assert Level
High Deassert Level153167180
(VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, C
are set to default values, unless otherwise noted. Typical values are at V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
OUTPUT LEVEL VOLTAGE DAC (SET_CML)
100I differential resistive load,
RXDE_EN = 0
Full-Scale VoltageV
Resolution
Integral NonlinearityINLSET_CML[7:0] > 60d
LOS THRESHOLD VOLTAGE DAC (SET_LOS)
Full-Scale VoltageV
Resolution
Integral NonlinearityINLSET_LOS[5:0] > 3d
CONTROL I/O SPECIFICATIONS
LOS Output High VoltageV
LOS Output Low VoltageV
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High VoltageV
Input Low VoltageV
Input HysteresisV
Input Leakage CurrentI
Output High VoltageV
Output Low VoltageV
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 5)
(VCC = 2.85V to 3.63V, CML receiver output is AC-coupled to differential 100I load, C
are set to default values, unless otherwise noted. Typical values are at V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CSEL Leading Time Before the
First SCL Edge
MAX3945
CSEL Trailing Time After the Last
SCL Edge
SDA, SCL External LoadC
Note 1: Guaranteed by design and characterization, T
Note 2: Deterministic jitter is measured with a repeating K28.5 pattern [00111110101100000101] for 1.25Gbps to 8.5Gbps data.
At 10.32Gbps and 11.3Gbps, a repeating K28.5 plus 59 0s and K28.5 plus 59 1s pattern is used. Deterministic jitter is
defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 3: LOS1_EN = 1, data rates of 1.25Gbps to 8.5Gbps with K28.5 pattern, and 6.4GHz input filter. For data rates of 10.32Gbps
to 11.3Gbps, the input filter is 12.5GHz and the pattern is PRBS23-1.
Note 4: Measurement includes an input AC-coupling capacitor of 100nF and C
is switched between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload
Signal_OFF = 0
Signal_ON = 1.2V
max_deassert_level and min_assert_level are measured for one SET_LOS setting
Note 5: LOS1_EN = 0, LOS2_EN = 1, DC voltage applied to the RPMIN input.
(VCC = 3.3V, TA = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface
is static during measurements.)
(VCC = 3.3V, TA = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface
is static during measurements.)
DEEMPHASIS VALUE
DIFFERENTIAL OUTPUT SIGNAL LEVEL
vs. SET_CML DAC SETTING
1200
)
P-P
MAX3945
1100
1000
900
800
700
600
500
DIFFERENTIAL OUTPUT AMPLITUDE (mV
400
RXDE1 = 0, RXDE0 = 0
RXDE1 = 0, RXDE0 = 1
RXDE1 = 1,
RXDE0 = 0
50300
RSSI MONITOR-BASED LOS THRESHOLDS
(LOS1_EN = 0 AND LOS2_EN = 1)
180
160
140
120
100
80
60
LOS THRESHOLD (mV)
40
20
0
070
RXDE_EN = 0
RXDE1 = 1,
RXDE0 = 1
SET_CML DAC SETTING
DEASSERT
ASSERT
SET_LOS[5:0] DAC CODE
vs. SET_CML DAC SETTING
(RATE_SEL = 1)
MAX3945 toc10
250200100150
6
RXDE1 = 0, RXDE0 = 1
4
RXDE1 = 0,
RXDE0 = 0
2
DEEMPHASIS LEVEL (dB)
RXDE_EN = 0
0
50250
RXDE1 = 1, RXDE0 = 1
RXDE1 = 1, RXDE0 = 0
SET_CML DAC SETTING
MAX3945 toc11
200150100
LOS MASKING TIME vs. DAC SETTING
5000
MAX3945 toc13
4000
3000
2000
MASKING TIME (µs)
1000
605030402010
0
0
SET_LOSTIMER[6:0] DAC CODE
MAX3945 toc14
12010080604020
Rx INPUT-BASED LOS THRESHOLD vs. DAC
CODE (LOS1_EN = 1 AND LOS2_EN = 0)
160
140
)
120
P-P
100
80
60
LOS THRESHOLD (mV
40
20
0
070
DEASSERT
ASSERT
SET_LOS[5:0] DAC CODE
DETERMINISTIC JITTER vs. INPUT AMPLITUDE AT 1.25Gbps
(VCC = 3.3V, TA = +25NC, unless otherwise noted. Registers are set to default values, unless otherwise noted, and the 3-wire interface
is static during measurements.)
INPUT RETURN GAIN (SDD11)
(INPUT POWER OF 0dBm, ENABLED)
0
-10
-20
SDD11 (dB)
-30
-40
0100
FREQUENCY (GHz)
101
OUTPUT COMMON-MODE RETURN GAIN (SCC22)
(INPUT POWER OF 0dBm, ENABLED)
0
-10
-20
SCC22 (dB)
-30
-40
1100
FREQUENCY (GHz)
OUTPUT RETURN GAIN (SDD22)
(INPUT POWER OF 0dBm, ENABLED)
0
MAX3945 toc19
-10
-20
SDD22 (dB)
-30
-40
0100
FREQUENCY (GHz)
101
TRANSIENT RESPONSE (10.3Gbps,
10 ONES 10 ZEROS PATTERN, SET_CML[7:0] = 92d)
0.25
0.20
MAX3945 toc22
10
0.15
0.10
A = 1.39dB, RXDE1 = 0, RXDE0 = 0
B = 2.12dB, RXDE1 = 0, RXDE0 = 1
0.05
C = 3.27dB, RXDE1 = 1, RXDE0 = 0
0
D = 4.37dB, RXDE1 = 1, RXDE0 = 1
-0.05
-0.10
-0.15
-0.20
-0.25
01000
INPUT COMMON-MODE RETURN GAIN (SCC11)
(INPUT POWER OF 0dBm, ENABLED)
0
MAX3945 toc20
-10
-20
-30
-40
1100
TIME (ps)
FREQUENCY (GHz)
A
C
B
D
800600400200
10
MAX3945 toc23
MAX3945 toc21
MAX3945
ELECTRICAL EYE DIAGRAM AFTER 6in OF FR4
AND 72in OF CABLE WITH NO DEEMPHASIS (11.3Gbps K28.5,
0XXDeemphasis block is disabled0
100Deemphasis block is enabled Level 10.3
101Deemphasis block is enabled Level 21.1
110Deemphasis block is enabled Level 32.1
111Deemphasis block is enabled Level 44.3
输出幅度范围(典型值
RXCTRL1[1]RXCTRL2[1]RXCTRL1[7:6]
RATE_SELRXDE_ENRXDE1RXDE0
0XXXLow data-rate path400 to 1192
10XXHigh data-rate path400 to 1147
1100High data-rate path with deemphasis400 to 1041
1101High data-rate path with deemphasis 400 to 987
1110High data-rate path with deemphasis400 to 908
1111High data-rate path with deemphasis400 to 828
)
MODE
DEEMPHASIS
(dB)
OUTPUT
AMPLITUDE
(mV
P-P
)
表
7. CML
RXCTRL1[1]RXCTRL2[1]RXCTRL1[7:6]
RATE_SELRXDE_ENRXDE1RXDE0
输出
0XXXLow data-rate path4.5
10XXHigh data-rate path4.5
1100High data-rate path with deemphasis4.1
1101High data-rate path with deemphasis 3.9
1110High data-rate path with deemphasis3.6
1111High data-rate path with deemphasis3.3
00LOS circuitry is disabled and powered down
X1LOS circuitry is enabled and Rx input amplitude is detected
10LOS circuitry is enabled and RPMIN input amplitude is detected
CSEL leading time before the first SCL edge
SCL pulse-width high
SCL pulse-width low
SCL rise to SDA propagation time
SDA setup time
SDA hold time
CSEL trailing time after last SCL edge
t
t
t
CH
t
CL
t
DS
DH
t
L
D
t
T
SFP+
t
D
双通道限幅放大器
t
T
t
T
MAX3945
接收器控制寄存器
Bit #
NameRXDE1RXDE0X*SOFTRESBW1BW0RATE_SELX*
Default Value00101111
Bit #
NameLOS2_ENLOS1_ENLOS_POLRX_POLSQ_ENRX_ENRXDE_ENAZ_EN
Default Value01110101
第7位:
基于
MAX3945
LOS2_ENLOS1_ENRX_ENRx INPUT-BASED LOSRSSI MONITOR-BASED LOS
第
6位:LOS1_EN
0=
1=
第5位:
0=
1=
第4位:
0=
1=
第
3位:SQ_EN
0=
1=
第2位:
0=
1=
第1位:
0=
1=
第0位:
0=
1=
双通道限幅放大器
接收器控制寄存器
76543210ADDRESS
LOS2_EN
监测器的
RSSI
00XDisabled and powered downDisabled and powered down
011EnabledDisabled and powered down
X10Disabled and powered downDisabled and powered down
111EnabledDisabled and powered down
100Disabled and powered downEnabled
101Disabled and powered downEnabled