MAXIM MAX3892 User Manual

General Description

The MAX3892 serializer is ideal for converting 4-bitwide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4

4-bit FIFO allows for any static delay between the parallel output clock and parallel input clock. Delay variation up to a unit interval (UI) is allowed after reset. A fully integrated phase-locked loop (PLL) synthesizes an internal

2.5GHz serial clock from a 622MHz, 155.5MHz,

77.8MHz, or 38.9MHz reference clock. A selectable dual VCO allows excellent jitter performance at both SONET and forward-error correction (FEC) data rates.

Operating from a single 3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers current-mode logic (CML) serial data and clock outputs. A loopback data output is provided to facilitate system diagnostic testing. The MAX3892 is available in the extended temperature range (-40°C to +85°C) in 44-pin QFN and TQFN packages.

Applications

SONET/SDH OC-48 Transmission Systems

WDM Transponders

Add/Drop Multiplexers

Dense Digital Cross-Connects

Backplane Interconnects

Features

♦ Single +3.3V Supply

♦ 455mW Power Consumption

♦ 1.4ps

RMS

Maximum Jitter Generation

♦ 4 ✕ 4-Bit FIFO Input Buffer

♦ 622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps

Serial Conversion

♦ 622MHz/667MHz or 311MHz/333MHz Clock Input

♦ On-Chip Clock Synthesizer

♦ Multiple Clock Reference Frequencies:

(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or (666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)

♦ LVDS Parallel Clock and Data Inputs

♦ CML Serial Data and Clock Outputs

♦ Additional CML Output for System Loopback

Testing

MAX3892

+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1

Serializer with Clock Synthesis

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Maxim Integrated Products

Ordering Information

19-2215; Rev 6; 10/07

EVALUATION KIT

AVAILABLE

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Typical Application Circuit

Denotes a lead-free package.

PART

MAX389 2EGH

MAX389 2ETH+

TEMP

RANGE

-40°C to +85° C

PINPACKAGE

PKG CODE

44 QFN G4477-3

44 TQFN T4477-3

MAX3273

LASER

DRIVER

MAX3882

1:4 DESERIALIZER

WITH CDR

RCLK+

RESET

= 50Ω.

FIL

VCCVCO

MAX3892

MODE

RATESET

SCLKO+ SCLKO-

SLBEN

SLBPD

SLBO+

SLBO-

CLKSET

FIFOERROR LOL

SDO+

SDO-

CML

TTL

CML

OPTIONAL

FOR

SYSTEM

LOOPBACK

TEST

LVPECL

LVDS

SONET/SDH

FRAMER

LVDS

THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z

100Ω

RCLK-

PDI0+

PDI0-

PDI3+ PDI3-

PCLKI+

PCLKI-

PCLKO+

PCLKO-

MAX3892

+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS load = 100Ω ±1%, TA= +25°C, unless otherwise noted.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage VCC, VCCO, VCCVCO .....................-0.5V to +5V

All Inputs and FIL .......................................-0.5V to (V

+ 0.5V)

LVDS Output Voltage (PCLKO±)................-0.5V to (V

+ 0.5V)

CML Output Current (SDO±, SCLKO±, SLBO±) ................22mA

Continuous Power Dissipation (T

= +85°C)

44-Pin QFN (derate 25mW/°C above +85°C) ............1625mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Supply Current I

LVDS INPUT SPECIFICATIONS (PDI[3..0]±, PCLKI±)

Input Voltage Range V

Differential Input Voltage |VID| 100 mV

Input Common-Mode Current LVDS input VOS = 1.2V 61 µA

Threshold Hysteresis 45 mV

Differential Input Resistance R

LVPECL INPUT SPECIFICATIONS (RCLK±)

Input High Voltage V

Input Low Voltage V

Input Bias Voltage VCC - 1.3 V

Single-Ended Input Resistance >1.0 kΩ

Differential Input Voltage Swing 300 1900 mV

LVDS OUTPUT SPECIFICATIONS (PCLKO±)

Output High Voltage V

Output Low Voltage V

Differential Output Voltage |VOD| 250 400 mV

Change in Magnitude of Differential Output Voltage for Complementary States

Offset Output Voltage 1.125 1.275 V

Change in Magnitude of Output Offset Voltage for Complementary States

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Δ|V

(Note 2) 138 190 mA

| 25 mV

0 2400 mV

83 100 117 Ω

VCC -

1.16

VCC -

1.81

0.925 V

VCC -

0.88

VCC -

1.48

1.475 V

P-P

MAX3892

+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1

Serializer with Clock Synthesis

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS loads = 100Ω ±1%, CML loads = 50Ω ±1%, T

= +25°C, unless otherwise noted.) (Note 3)

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS load = 100Ω ±1%, TA= +25°C, unless otherwise noted.) (Note 1)

Differential Output Resistance 80 140 Ω

Output Current Shorted together 12 mA

Output Current Shorted to ground 40 mA

CML OUTPUT SPECIFICATIONS (SDO±, SCLKO±, SLBO±)

Differential Output RL = 100Ω differential 640 800 1000 mV

Differential Output Resistance 83 100 117 Ω

Output Common-Mode Voltage RL = 50Ω to V LVTTL SPECIFICATIONS (RESET, RATESET, SLBEN, SLBPD FIFOERROR, LOL)

Input High Voltage V

Input Low Voltage V

Input High Current I

Input Low Current I

Output High Voltage V

Output Low Voltage V

PROGRAMMING INPUTS (CLKSET, MODE)

Input Current Input = 0 or V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

P-P

IOH = 20µA 2.4 V

IOL = 1mA 0.4 V

VCC - 0.2 V

2.0 V

0.8 V

-30 +10 µA

-50 +10 µA

-500 +500 µA

PARALLEL INPUT SPECIFICATIONS (PDI±, PCLKI±)

Parallel Input Data Rate

Parallel Input Clock Rate

Parallel Input Setup Time t

Parallel Input Hold Time t

PARALLEL CLOCK OUTPUT SPECIFICATIONS (PCLKO±)

Parallel Clock Output Rise/Fall Time

Parallel Clock Output Duty Cycle 46 54 %

SERIAL OUTPUT SPECIFICATIONS (SDO±, SCLKO±)

Serial Output Data Rate

Serial Data Output Rise/Fall Time tr, t

Serial Output Clock to Data Delay t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

, t

CLK-Q

RATESET = GND 622

RATESET = V

MODE = OPEN or V

MODE = SHORT or 30kΩ to GND 311

(Note 4) -94 ps

(Note 4) 300 ps

20% to 80% 100 200 ps

RATESET = GND 2.488

RATESET = V

20% to 80% 80 ps

(Note 5) -25 25 ps

666

622

2.666

Mbps

MHz

Gbps

MAX3892

+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis

4 _______________________________________________________________________________________

Note 1: Specifications at -40°C are guaranteed by design and characterization. Note 2: Measured with SLBO/CLK622 and SCLK outputs disabled and CML outputs open. Note 3: AC characteristics are guaranteed by design and characterization. Note 4: In 622MHz clock mode, the parallel data is clocked in by the rising edge of the 622MHz/666MHz parallel clock input. In the

311MHz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. The parallel input setup and hold time increases by 60ps if the duty cycle is between 48% to 52% in 311MHz mode (Figure 1).

Note 5: Relative to the falling edge of the SCLKO. Note 6: Measurement bandwidth is BW = 12kHz to 20MHz. Note 7: Measured with 00001111 pattern, RCLK to PCLKI/PDI[3:0] phase approximately 40ps. See the

Jitter Generation vs. RCLK to

PCLK/PDI[3:0] Phase

plot in the

Typical Operating Characteristics

section.

Note 8: Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured using a 2

- 1 PRBS pattern with

96 consecutive identical digits.

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C. Typical values are at VCC= +3.3V, differential LVDS loads = 100Ω ±1%, CML loads = 50Ω ±1%, T

= +25°C, unless otherwise noted.) (Note 3)

Serial Clock Output Jitter Generation

Serial Data Output Random Jitter RJ (Note 7) 1.4 ps

Serial Data Output Deterministic Jitter

REFERENCE CLOCK INPUT SPECIFICATIONS (RCLK)

Reference Clock Frequency Tolerance

Reference Clock Input Duty Cycle 30 70 %

RESET INPUTS (RESET)

Minimum Pulse Width of FIFO Reset

Tolerated Drift Between PCLKI and PCLKO After Reset

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

JG (Notes 6 and 7) 1.0 1.4 ps

DJ (Note 8) 19 ps

±100 ppm

UI is PCLKO period 4 UI

UI is PCLKO period ±1UI

RMS

P-P

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