MAXIM MAX3882A User Manual

MAX3882A

2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier

________________________________________________________________

Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX3882A is a deserializer combined with clock
and data recovery and limiting amplifier ideal for con­verting 2.488Gbps serial data to 4-bit-wide, 622Mbps
parallel data for SDH/SONET applications. The device
accepts serial NRZ input data as low as 10mV

P-P

of

2.488Gbps and generates four parallel LVDS data out­puts at 622Mbps. Included is an additional high-speed
serial data input for system loopback diagnostic test­ing. For data acquisition, the MAX3882A does not
require an external reference clock. However, if need­ed, the loopback input can be connected to an external
reference clock of 155MHz or 622MHz to maintain a
valid clock output in the absence of input data transi­tions. Additionally, a TTL-compatible loss-of-lock output
is provided. The device provides a vertical threshold
adjustment to compensate for optical noise generated
by EDFAs in WDM transmission systems. The
MAX3882A operates from a single +3.3V supply and
consumes 610mW.

The MAX3882A’s jitter performance exceeds all SDH/
SONET specifications. The device is available in a 6mm

✕ 6mm, 36-pin TQFN package.

Applications

SDH/SONET Receivers and Regenerators

Add/Drop Multiplexers

Digital Cross-Connects

SDH/SONET Test Equipment

DWDM Transmission Systems

Features

♦ No Reference Clock Required for Data Acquisition
♦ Serial Input Rate: 2.488Gbps
♦ Fully Integrated Clock and Data Recovery with

Limiting Amplifier and 1:4 Demultiplexer

♦ Parallel Output Rate: 622Mbps
♦ Differential Input Range: 10mV

P-P

to 1.6V

P-P

without Threshold Adjust

♦ Differential Input Range: 50mV

P-P

to 600mV

P-P

with Threshold Adjust

♦ 0.65UI High-Frequency Jitter Tolerance
♦ Loss-of-Lock (LOL) Indicator
♦ Wide Input Threshold Adjust Range: ±170mV
♦ Maintain Valid Clock Output in Absence of Data

Transitions

♦ System Loopback Input Available for System

Diagnostic Testing

♦ Operating Temperature Range -40°C to +85°C
♦ Low Power Dissipation: 610mW at +3.3V

19-2718; Rev 2; 4/09

Pin Configuration

+

Denotes a lead(Pb)-free/RoHS-compliant package.

*

EP = Exposed pad.

Ordering Information

Typical Application Circuits appear at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX3882AETX+ -40°C to +85°C 36 TQFN-EP*

TOP VIEW

GND

PD2-

PD2+

PD3-

PD3+

27 26 25 24 23 22 21 20 19

PD1+

PD1-

PD0+

PD0-

18 PCLK+

17

PCLK-

16

GND

15

_OUT

V

CC

14

V

_VCO

CC

13

FIL

V

12

_VCO

CC

GND

11

*EP

10 LREF

SIS

LOL

VCC_OUT

GND

FREFSET

V

CC

V

CC

CAZ+

CAZ-

V

REF

V

CTRL

*EXPOSED PAD.

28

29

30

31

32

33

34

35

36

+

123456789

GND

CC

V

MAX3882A

SDI-

SDI+

TQFN

CC

V

SLBI+

SLBI-

MAX3882A

2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage, VCC................................................-0.5 to +5.0V

Input Voltage Levels

(SDI+, SDI-, SLBI+, SLBI-) ...........(V

CC

- 1.0V) to (V

CC

+ 0.5V)

Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±20mA

LVDS Output Voltage Levels

(PCLK±, PD_±).......................................-0.5V to (V

CC

+ 0.5V)
Voltage at LOL, SIS, LREF, V

REF

, FIL, CAZ+,

CAZ-, V

CTRL

, FREFSET ..........................-0.5V to (V

CC

+ 0.5V)

Continuous Power Dissipation (T

A

= +70°C)

36-Pin TQFN (derate 35.7mW/°C above +70°C) ......2856mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 1)

Supply Current ICC 185 230 mA

Single-Ended Input Voltage
Range

Input Common-Mode Voltage
Range

Input Termination to VCC R

Differential Input Voltage Range
with Threshold Adjust Enabled
SDI+, SDI-

Threshold Adju stment Range VTH Figure 2 -170 +170 mV

Threshold-Control Voltage V

Threshold-Control Linearity ±5 %

Threshold Setting Accuracy Figure 2 -18 +18 mV

Threshold Setting Stability

V

REF

LVDS Output High Voltage VOH 1.475 V

LVDS Output Low Voltage V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

CTRL

Voltage Output RL = 50k 2.14 2.2 2.24 V

OL

Figure 1

IS

Figure 1

42.5 50 57.5 

IN

Figure 2 100 600 mV

(Note 2) 0.302 2.097 V

15mV  |VTH|  80mV -6 +6

80mV < |V

0.925 V

TH

|  170mV -12 +12

V

0.8

V

0.4

CC

CC

-

-

V

CC

0.4

V

CC

+

V

V

P-P

mV

LVDS Differentia l Output Voltage |VOD| 250 400 mV

LVDS Change in Magnitude of
Differential Output Voltage for
Complementary States

LVDS Offset Output Voltage 1.125 1.275 V

LVDS Change in Magnitude of
Output Offset Voltage for
Complementary States

|V

| 25 mV

OD

|V

| 25 mV

OS

MAX3882A

2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 1)

Note 1: At -40°C, DC characteristics are guaranteed by design and characterization.
Note 2: Voltage applied to V

CTRL

pin is from 0.302V to 2.097V when input threshold is adjusted from +170mV to -170mV.

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 3)

LVDS Differentia l Output
Impedance

LVDS Output Current Short together or short to GND 12 mA

LVTTL Input High Voltage VIH 2.0 V

LVTTL Input Low Voltage VIL 0.8 V

LVTTL Input Current -10 +10 μA

LVTTL Output High Voltage VOH IOH = +20μA 2.4 V

LVTTL Output Low Voltage VOL IOL = -1mA 0.4 V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

80 120 

Serial Input Data Rate 2.488 Gbps

Differential Input Voltage
Threshold Adjust Disabled
SDI+, SDI-

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

(Note 4) Figure 1 10 1600 mV

ID

P-P

Differential Input Voltage SLBI+,
SLBI-

Jitter Peaking JP f  2MHz 0.1 dB

Jitter Transfer Bandwidth JBW 1.7 2.0 MHz

Sinusoidal Jitter Tolerance

Sinusoidal Jitter To lerance with
Threshold Adjust Enabled
(Note 5)

Jitter Generation J

Differential Input Return Loss 20 log|S11|

Tolerated Consecutive Identical
Digits

Acquisition Time (Note 7)
Figure 4

LOL As sert Time Figure 4 2.3 100.0 μs

Low-Frequency Cutoff for
DC Offset Cancellation Loop

50 800 mV

f = 100kHz 3.1 4.1

f = 1MHz 0.62 1.0

f = 10MH z 0.44 0.6

f = 100kHz 4.1

f = 1MHz 0.75

f = 10MH z 0.41

(Note 6) 2.7 ps

GEN

100kHz to 2.5GHz 17

2.5GHz to 4.0GHz 15

BER = 10

0011 pattern 0.6

PRBS 2

CAZ = 0.1μF 4 kHz

-10

2000 Bits

23

- 1 pattern 0.62 1.5

UI

UI

P-P

P-P

P-P

RMS

dB

ms

MAX3882A

2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0 to +3.6V, TA= -40°C to +85°C. Typical values are at +3.3V and at TA= +25°C, unless otherwise noted.) (Note 3)

Note 3: AC characteristics are guaranteed by design and characterization.
Note 4: Jitter tolerance is guaranteed (BER ≤ 10

-10

) within this input voltage range. Input threshold adjust is disabled when V

CTRL

is

connected to V

CC

.

Note 5: Measured with the input amplitude set at 100mV

P-P

differential swing with a 20mV offset and an input edge speed of 145ps

(4th-order Bessel filter with f

3dB

= 1.8GHz).

Note 6: Measured with 10mV

P-P

OC-48 differential input with PRBS 223- 1 and BW = 12kHz to 20MHz.

Note 7: Measured at OC-48 data rate using a 0.068µF loop-filter capacitor.
Note 8: Under LOL condition, the CDR clock output is set by the external reference clock.
Note 9: Relative to the falling edge of PCLK+. See Figure 3.

Reference Cloc k Frequenc y

Reference Clock Accuracy ±100 ppm

VCO Frequency Drift (Note 8) 400 ppm

Data Output Rate 622 Mbps

Cloc k Output Frequenc y 622 MHz

Output Cloc k-to-Data Dela y t

Cloc k Output Duty Cycle 45 50 55 %

Clock and Data Output Rise/Fall
Time

LVDS Differentia l Skew t

LVDS Channel-to-Channel Skew t

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FREFSET = VCC 155

FREFSET = GND 622

(Note 9) -80 +80 ps

CK-Q

, t

t

R

SKEW1

SKEW2

20% to 80% 100 250 ps

F

Any differential pair 50 ps

PD_± 100 ps

MHz