MAXIM MAX3880 User Manual

General Description

The MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low­voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.

The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.

The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.

Applications

2.488Gbps SDH/SONET Transmission Systems

Add/Drop Multiplexers

Digital Cross-Connects

Features

♦ Single +3.3V Supply

♦ 910mW Operating Power

♦ Fully Integrated Clock Recovery and Data

Retiming

♦ Exceeds ANSI, ITU, and Bellcore Specifications

♦ Additional High-Speed Input Facilitates System

Loopback Diagnostic Testing

♦ 2.488Gbps Serial to 155Mbps Parallel Conversion

♦ LVDS Data Outputs and Synchronization Inputs

♦ Tolerates >2000 Consecutive Identical Digits

♦ Loss-of-Lock Indicator

MAX3880

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

________________________________________________________________ Maxim Integrated Products 1

MAX3866

MAX3880

PRE/POSTAMPLIFIER

OVERHEAD

TERMINATION

100Ω*

*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z

0

= 50Ω.

V

CC

+3.3V

PHADJ-

V

CC

LOL

GNDFIL-

FIL+

SIS

TTL TTL

SDI+

OUT+

V

CC

IN+

FIL

OUT-

LOP

TTL

SDI-

SLBI-

SLBI+

SYSTEM
LOOPBACK

SYNC+

SYNC-

PD15+

PD15-

100Ω*

PD0+

PD0-

100Ω*

PCLK+

PCLK-

PHADJ+

0.01µF

+3.3V

C

F

1µF

Typical Application Circuit

19-1467; Rev 2; 12/05

PART

MAX3880ECB -40°C to +85°C

TEMP. RANGE PIN-PACKAGE

64 TQFP-EP*

Ordering Information

*Exposed pad
+Denotes lead-free package.

Pin Configuration appears at end of data sheet.

For free samples and the latest literature, visit www.maxim-ic.com or phone [phone].
For small orders, phone [phone].

MAX3880ECB+ -40°C to +85°C 64 TQFP-EP*

MAX3880

+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, differential loads = 100Ω ±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V

CC

= +3.3V, TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Positive Supply Voltage (VCC)...............................-0.5V to +7.0V

Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-,

SYNC+, SYNC-)........................... (V

CC

- 0.5V) to (VCC+ 0.5V)

Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA

Voltage at LOL, SIS, PHADJ+, PHADJ-,

FIL+, FIL- .................................................-0.5V to (V

CC

+ 0.5V)

Output Current LVDS Outputs ............................................10mA

Continuous Power Dissipation (T

A

= +85°C)

TQFP (derate 33.3mW/°C above +85°C).......................1.44W

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Figure 1

Common-mode voltage = 50mV

Figure 2

Differential input voltage = 100mV

CONDITIONS

%±2.5 ±10

∆R

O

Change in Magnitude of Single­Ended Output Resistance for
Complementary Outputs

Ω40 95 140R

O

Single-Ended Output
Resistance

mV±25

∆V

OS

Change in Magnitude of Output
Offset Voltage for
Complementary States

V1.125 1.275V

OS

Output Offset Voltage

mV±25

∆|VOD|

Change in Magnitude of
Differential Output Voltage for
Complementary States

mV250 400

|

V

OD

|

Differential Output Voltage

V0.925V

OL

Output Low Voltage

mVp-p50 800V

ID

Differential Input Voltage

mA275 380I

CC

Supply Current

V1.475V

OH

Output High Voltage

Ω85 100 115R

IN

Differential Input Resistance

mV78V

HYST

Threshold Hysteresis

mV-100 100V

IDTH

Differential Input Threshold

VVCC- 0.4 VCC+ 0.2V

IS

Single-Ended Input Voltage

Ω50R

IN

Input Termination to Vcc

V0 2.4V

I

Input Voltage Range

UNITSMIN TYP MAXSYMBOLPARAMETER

V0.8V

IL

Input Low Voltage

V2.0V

IH

Input High Voltage

V2.4 V

CC

V

OH

Output High Voltage

µA-10 +10Input Current

V0.4V

OL

Output Low Voltage

SERIAL DATA INPUTS (SDI±, SLBI±)

LVDS INPUTS AND OUTPUTS (SYNC±, PCLK±, PD_±)

TTL INPUTS AND OUTPUTS (SIS, LOL)

MAX3880

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, differential loads = 100Ω ±1%, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
V

CC

= +3.3V, TA= +25°C.) (Note 1)

Note 1: AC characteristics are guaranteed by design and characterization.
Note 2: At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency

jitter tolerance outperforms the instrument’s measurement capability.

Figure 5

100kHz to 2.5GHz

f = 10MHz

f = 70kHz (Note 2)

f = 100kHz

f = 1MHz

2.5GHz to 4.0GHz

CONDITIONS

dB

-11

Input Return Loss (SDI±, SLBI±)

ps200 450 900t

CLK-Q

Parallel Clock-to-Data Output
Delay

Mbps155.52

Gbps2.488SDISerial Data Rate

Parallel Output Data Rate

-18

Bits>2,000

Tolerated Consecutive Identical
Digits

UIp-p

0.28 0.46

Jitter Tolerance

2.31 3.3

1.74 2.41

0.38 0.57

UNITSMIN TYP MAXSYMBOLPARAMETER

Figure 1. Input Amplitude

Figure 2. Driver Output Levels

SDI+

SDI-

25mV MIN
400mV MAX

(SDI+) - (SDI-)

V

PD-

SINGLE-ENDED OUTPUT

V

PD+

- V

V

PD+

PD-

DIFFERENTIAL OUTPUT

50mVp-p MIN

V

ID

800mVp-p MAX

PD+

V

= 100Ω

R

D

PD-

0V (DIFF)

L

V

|

OD|

V

OD

V

OH

V

OS

V

OL

+V

OD

0V

V

= V

PD+

- V

PD-

OD, p-p

-V

OD

MAX3880

+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery

4 _______________________________________________________________________________________

0

10 1,000100

JITTER TOLERANCE vs. INPUT VOLTAGE

0.3

0.1

0.6

0.4

0.8

0.2

0.7

0.5

MAX3880-04

INPUT VOLTAGE (mVp-p)

JITTER TOLERANCE (UIp-p)

JITTER FREQUENCY = 1MHz

JITTER FREQUENCY
= 5MHz

SONET SPEC

10

-10

10

-8

10

-9

10

-6

10

-7

10

-4

10

-5

10

-3

6.0 7.06.5 7.5 8.0 8.5 9.0 9.5 10.0

BIT ERROR RATE vs. INPUT VOLTAGE

MAX3880-05

INPUT VOLTAGE (mVp-p)

BIT ERROR RATE

200

300

400

600

500

700

-50 0-25 25 50 75 100

PARALLEL CLOCK TO DATA OUTPUT

PROPAGATION DELAY vs. TEMPERATURE

MAX3880-06

TEMPERATURE (°C)

PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)

Typical Operating Characteristics

(VCC= +3.3V, TA = +25°C, unless otherwise noted.)

1.64ns/div

DATA

CLOCK

RECOVERED DATA AND CLOCK

(DIFFERENTIAL OUTPUT)

MAX3880-01

2

23

- 1 PATTERN

240

250

260

270

280

290

300

-50 -25 0 25 50 75 100

SUPPLY CURRENT vs. TEMPERATURE

MAX3880-02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

VCC = 3.6V

VCC = 3.0V

10

0.1
10 1,000 10,000

JITTER TOLERANCE

1

MAX3880-03

JITTER FREQUENCY (kHz)

INPUT JITTER (UIPp-p)

100