General Description
The MAX3876 is a compact, low-power clock recovery
and data retiming IC for 2.488Gbps SDH/SONET applications. The fully integrated phase-locked loop (PLL)
recovers a synchronous clock signal from the serial
NRZ data input. The data is retimed by the recovered
clock. Differential CML outputs are provided for both
clock and data signals, and an additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3876 is designed for both section-regenerator
and terminal-receiver applications in OC-48/STM-16
transmission systems. Its jitter performance exceeds all
of the SONET/SDH specifications.
This device operates from a +3.3V or +5.0V single supply over a -40°C to +85°C temperature range. Power
consumption is typically only 445mW with a +3.3V supply. The MAX3876 is available in a 32-pin TQFP package as well as in die form.
Applications
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
2.488Gbps ATM Receiver
Digital Video Transmission
SDH/SONET Test Equipment
Intrarack/Subrack Interconnects
Features
♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH
Regenerator Specifications
♦ 440mW Power Dissipation (at +3.3V)
♦ Clock Jitter Generation: 3.7mUI
RMS
♦ +3.3V or +5V Single Power Supply
♦ Fully Integrated Clock Recovery and Data Retiming
♦ Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
♦ Tolerates >2500 Consecutive Identical Digits
♦ Loss-of-Lock Indicator
♦ Differential CML Data and Clock Outputs
For free samples and the latest literature: www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
________________________________________________________________ Maxim Integrated Products 1
Typical Application Circuit
19-1631; Rev 0; 1/00
PART
MAX3876EHJ -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
32 TQFP
Ordering Information
Pin Configuration appears at end of data sheet.
MAX3876E/D -40°C to +85°C Dice*
*Dice are designed to operate over this range, but are tested
and guaranteed at TA= +25°C only. Contact factory for
availability.
+3.3V
+3.3V
TTL
0.01µF
0.01µF
FILT
PHOTODIODE
IN
V
CC
MAX3866
PREAMPLIFIER
OUT+
OUT-
SYSTEM
LOOPBACK
CC
SDI+
SDI-
SLBI+
SLBI-
MAX3876
SIS FIL+ FIL-
TTL
1µF
LOLV
SDO+
SDO-
SCLKO+
SCLKO-
+3.3V
MAX3831
4:1/1:4
TRANSCEIVER
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage, VCC..............................................-0.5V to +7.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-) ...........(V
CC
- 0.5V) to (VCC+ 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±11mA
CML Output Current Levels
(SDO+, SDO-, SCLKO+, SCLKO-) ................................±22mA
Voltage at LOL, SIS, FIL+, FIL-...................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
32-Pin TQFP (derate 16.1mW/°C above +85°C).............1.0W
Operating Temperature Range
MAX3876EHJ..................................................-40°C to +85°C
Operating Junction Temperature Range (die) ..-55°C to +150°C
Storage Temperature Range .............................-60°C to +160°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Figure 1, DC-coupled
Excluding CML output termination
CONDITIONS
VVCC- 0.4 VCC+ 0.4V
IS
Single-Ended Input Voltage
(SDI±, SLBI±)
mVp-p
50 1000
V
ID
mA135 167I
CC
Supply Current
Differential Input Voltage
(SDI±, SLBI±)
V2.4 V
CC
V
OH
TTL Output High Voltage (LOL)
µA-10 +10TTL Input Current (SIS)
V0.8V
IL
TTL Input Low Voltage (SIS)
Ω48R
IN
Input Termination to V
CC
(SDI±, SLBI±)
mVp-p
CML Differential Output Voltage
Swing
ΩDifferential Output Impedance
V2.0V
IH
TTL Input High Voltage (SIS)
UNITSMIN TYP MAXSYMBOLPARAMETER
TTL Output Low Voltage (LOL)
V
OL
0.4 V
640 800 1000
85 100 115
RL= 50Ω to V
CC
Figure 1. Input Amplitude Figure 2. Output Clock-to-Q Delay
VCC- 0.2RL= 50Ω to V
CC
V
CML Output Common-Mode
Voltage
580 800 1000
TA= 0°C to +85°C
TA= -40°C
DC-coupled VVCC- 0.25 V
CM
Input Common-Mode Voltage
Figure 1, AC-coupled 50 1600
+ 0.4V
V
CC
V
CC
800mV
25mV
t
CK
VCC - 0.4V
V
VCC - 0.25V
V
- 0.5V
CC
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
CC
500mV
(b) DC-COUPLED SINGLE-ENDED CML INPUT
25mV
SCLKO+
SDO
t
CK-Q
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA= +25°C.) (Note 2)
Clock Output Edge Speed 20% to 80%
f ≤ 2MHz
75 ps
Figure 2
1.76 3.32
0.32 0.51
f = 100kHz
f = 10MHz
f = 70kHz (Note 3)
f = 1MHz
CONDITIONS
dB0.03 0.1J
P
Jitter Peaking
ps110 290
GHz2.488Serial Output Clock Rate
Clock-to-Q Delay
mUIp-p19.2 61.0
mUI
RMS
3.7 6.2
J
GEN
Jitter Generation
MHz1.4 2.0J
BW
Jitter Transfer Bandwidth
UIp-p
2.1 4.4
Jitter Tolerance
0.41 0.74
UNITSMIN TYP MAXSYMBOLPARAMETER
Data Output Edge Speed 20% to 80% 95 ps
Tolerated Consecutive
Identical Digits
2500
Bits
100kHz to 2.5GHz 17
2.5GHz to 4.0GHz 15
Jitter BW = 12kHz to 20MHz
Note 1: Dice are tested at TA= +25°C only.
Note 2: AC characteristics are guaranteed by design and characterization.
Note 3: At jitter frequencies < 70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications.
Input Return Loss
(SDI±, SLBI±)
dB
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
10ps/div
RECOVERED CLOCK JITTER
MAX3876 toc2
50mV/div
PRBS = 223-1
V
IN
= 50mVp-p
WIDEBAND JITTER
= 3.94ps
RMS
10
10k 1M
10M
100k
JITTER TOLERANCE
0.1
MAX3876 toc03
JITTER FREQUENCY (kHz)
INPUT JITTER (UIp-p)
1
PRBS = 223 - 1
50mVp-p INPUT
BELLCORE
MASK
100ps/div
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
MAX3876 toc1
DATA
CLOCK
223-1 PATTERN
V
IN
= 50mVp-p
TA = +25°C
200mV/div
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
4 _______________________________________________________________________________________
NAME FUNCTION
1, 2, 8, 9,
10, 16, 26,
29, 32
GND Supply Ground
3, 6, 11,
14, 15, 17,
20, 21, 24,
27, 28
V
CC
Positive Supply Voltage
PIN
4 SDI+ Positive Data Input. 2.488Gbps serial-data stream.
5 SDI- Negative Data Input. 2.488Gbps serial-data stream.
13 SLBI- Negative System Loopback Input. 2.488Gbps serial-data stream.
12 SLBI+ Positive System Loopback Input. 2.488Gbps serial-data stream.
7 SIS Signal Input Selection, TTL. Low for normal data input. High for system loopback input.
Pin Description
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
10 100 1000
JITTER TOLERANCE vs.
INPUT AMPLITUDE
MAX3876 toc04
INPUT SIGNAL AMPLITUDE (mVp-p)
JITTER TOLERANCE (UIp-p)
0.1
JITTER FREQUENCY = 1MHz
JITTER FREQUENCY = 5MHz
TA = +85°C
PRBS = 2
23
- 1
0.9
10
-10
10
-8
10
-9
10
-6
10
-7
10
-5
8.8 9.0 9.1 9.2 9.3 9.4 9.5 9.8
BIT ERROR RATE vs.
INPUT AMPLITUDE
MAX3876 toc06
INPUT SIGNAL AMPLITUDE (mVp-p)
BIT ERROR RATE
PRBS = 223 - 1
8.9 9.6 9.7
-3.0
-2.0
-2.5
-1.0
-1.5
0
-0.5
0.5
1k 10k 1M 10M
JITTER TRANSFER
MAX3876 toc05
JITTER FREQUENCY (Hz)
JITTER TRANSFER (dB)
100k
PRBS = 223 - 1
BELLCORE
MASK
Typical Operating Characteristics (continued)
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
18
SCLKO- Negative Serial Clock Output, CML, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-.
10
0.1
0 0.15 0.20 0.250.05 0.10
JITTER TOLERANCE
vs. PULSE-WIDTH DISTORTION
1.0
MAX3876 toc07
PULSE-WIDTH DISTORTION (UI)
JITTER TOLERANCE (UI)
PRBS = 223 - 1
100mVp-p INPUT
100kHz
1MHz
10MHz
SUPPLY CURRENT
160
155
150
145
140
135
SUPPLY CURRENT (mA)
130
125
120
-50 0-25 25 50 75 100
vs. TEMPERATURE
VCC = 5.0V
AMBIENT TEMPERATURE (°C)
MAX3876 toc08
VCC = 3.0V
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
_______________________________________________________________________________________ 5
Figure 3. Functional Diagram
NAME FUNCTIONPIN
25
LOL
Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor)
23 SDO+ Positive Data Output, CML, 2.488Gbps
22 SDO- Negative Data Output, CML, 2.488Gbps
19 SCLKO+ Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
30 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
31 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Pin Description (continued)
Detailed Description
The MAX3876 consists of a fully integrated phaselocked loop (PLL), input amplifier, data retiming block,
and CML output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept
DC-coupled differential input amplitudes from 50mVp-p
up to 1000mVp-p. With AC-coupling, differential input
signal amplitudes can be increased to a maximum of
1600mVp-p. The bit error rate is better than 1 · 10
-10
for
input signals as small as 10mVp-p, though the jitter tolerance performance will be degraded. For interfacing
with PECL signal levels, see Applications Information.
Phase Detector
The phase detector incorporated in the MAX3876 produces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
SDI+
SDI-
SLBI+
SLBI-
AMP
AMP
SISSIS
MUX
MAX3876
PHASE AND
FREQUENCY
DETECTOR
FIL+ FIL-
LOOP
FILTER
DQ
CK
I
VCO
Q
CML
CML
TTL
SDO+
SDO-
SCLKO+
SCLKO-
LOL
Frequency Detector
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadrature VCO outputs on the rising edge of the data input
signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition
is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequency detector.
Loop Filter and VCO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, CF,
is required to set the PLL damping ratio. See Design
Procedure for guidelines on selecting this capacitor.
The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low-phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.5ps
RMS
within a jitter band-
width of 12kHz to 20MHz.
Loss-of-Lock Monitor
A loss-of-lock (LOL) monitor is incorporated in the
MAX3876 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency locked, LOL switches to TTL high in approximately 800ns.
Note: The LOL monitor is valid only when a data stream
is present on the inputs to the MAX3876. As a result,
LOL does not detect a loss-of-power condition due to
loss of the incoming signal.
Design Procedure
Setting the Loop Filter
The MAX3876 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 1.5MHz. The external capacitor, CF,
can be adjusted to set the loop damping. Figures 4 and
5 show the open-loop and closed-loop transfer functions.
The PLL zero frequency, fZ, is a function of external
capacitor CF, and can be approximated according to:
For an overdamped system (f
Z/fL
) < 0.25, the jitter peaking (MP) of a second-order system can be approximated by:
For example, using CF= 0.1µF results in a jitter peaking
of 0.2dB. Reducing CFbelow 0.01µF may result in PLL
instability. The recommended value for CFis 1.0µF to
guarantee a maximum jitter peaking of less than 0.1dB.
CFmust be a low TC, high-quality capacitor of type
X7R or better.
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
6 _______________________________________________________________________________________
Figure 4. Open-Loop Transfer Function
Figure 5. Closed-Loop Transfer Function
(j2πf) (dB)
H
O
CF = 1.0µF
= 2.6kHz
f
OPEN-LOOP GAIN
H(j2πf) (dB)
Z
0
-3
101
CF = 1.0µF
= 0.1µF
C
F
= 26kHz
f
Z
100
CF = 0.1µF
f (kHz)
1000
f
z
=
2π
1
60 C
()
F
CLOSED-LOOP GAIN
1
M
P
100
10
20log 1+
=
1000
f
Z
f
L
f (kHz)
Input and Output Terminations
The MAX3876’s digital outputs (SDO+, SDO-, SCLKO+,
SCLKO-) are internally terminated with 50Ω to V
CC
(Figure 6). See the DC Electrical Characteristics for sig-
nal swing and common-mode voltage levels. To ensure
best performance, the differential outputs must have
balanced loads. The input termination can be driven
differentially or can be driven single-ended by externally biasing SDI- or SLBI- to the center of the voltage
swing.
Jitter Tolerance and Input
Sensitivity Trade-Offs
When the received data amplitude is higher than
50mVp-p, the MAX3876 provides a typical jitter tolerance of 0.51UI at jitter frequencies greater than 10MHz.
The SDH/SONET jitter tolerance specification is 0.15UI,
leaving a jitter allowance of 0.36UI for receiver preamplifier and postamplifier design.
The BER is better than 1 · 10
-10
for input signals greater
than 10mVp-p. At this input level, jitter tolerance will be
degraded but will still be above the SDH/SONET
requirement. The user can make a trade-off between jitter tolerance and input sensitivity according to the
specific application. See the Typical Operating
Characteristics for Jitter Tolerance and BER vs. Input
Amplitude graphs.
Jitter Tolerance vs.
Pulse-Width Distortion
The MAX3876 can typically tolerate up to 0.20UI of
pulse-width distortion (PWD) and still exceed ITU and
Bellcore specifications for sinusoidal jitter tolerance.
Refer to the Typical Operating Characteristics for Jitter
Tolerance and PWD vs. Jitter Frequency graphs.
Applications Information
Consecutive Identical Digits (CIDs)
The MAX3876 has a low phase and frequency drift in
the absence of data transitions. As a result, long runs of
consecutive zeros and ones can be tolerated while
maintaining a BER of 1 · 10
-10
. The CID tolerance is
tested using a 2
13
- 1 PRBS, substituting a long run of
zeros to simulate the worst case. A CID tolerance of
2500 bits is typical.
System Loopback
The MAX3876 is designed to allow system loopback
testing. The user can connect a serializer output in a
transceiver directly to the SLBI+ and SLBI- inputs of the
MAX3876 for system diagnostics. To select the SLBI±
inputs, apply a TTL logic high to the SIS pin.
PECL Input Levels
When interfacing with differential PECL input levels, it is
important to attenuate the signal while still maintaining
50Ω termination (Figure 7). AC-coupling is also
required to maintain the input common-mode level.
Layout
The MAX3876’s performance can be significantly
affected by circuit board layout and design. Use good
high-frequency design techniques, including minimizing ground inductance and using fixed-impedance
transmission lines on the data and clock signals.
Power-supply decoupling should be placed as close to
V
CC
as possible. Take care to isolate the input from the
output signals to reduce feedthrough.
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
_______________________________________________________________________________________ 7
Figure 6. CML Outputs
V
CC
50Ω
50Ω
SDO+
SDO-
MAX3876
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
8 _______________________________________________________________________________________
Figure 7. PECL-to-CML Interface
Figure 8. Direct Coupling of a PECL Output into the MAX3876
V
CC
VCC = 3.3V
3.3V
0.1µF
25Ω
PECL
LEVELS
*
R
T
0.1µF
RT*
SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL
*SELECT R
T
IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA).
25Ω
100Ω
SDI+
SDI-
ZIN = 50Ω
= 50Ω
Z
IN
MAX3876
PECL
OUTPUT
226Ω
243Ω
82Ω
226Ω
82Ω
3.3V
243Ω
SDI+
SDI-
V
= 3.3V
CC
ZIN = 50Ω
= 50Ω
Z
IN
MAX3876
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
_______________________________________________________________________________________ 9
Pin Configuration
MAX3876
TQFP
TOP VIEW
32 28
293031
25
26
27
FIL+
FIL-
GND
V
CC
GND
VCCGND
LOL
10
13
15
14
1611 12
9
GND
V
CC
GND
SLBI-
SLBI+
V
CC
V
CC
GND
17
18
19
20
21
22
23
SDO+
24 V
CC
SDO-
V
CC
V
CC
SCLKO+
SCLKO-
V
CC
2
3
4
5
6
7
8GND
SIS
V
CC
SDI-
SDI+
V
CC
GND
1GND
TRANSISTOR COUNT: 1334
SUBSTRATE CONNECTED TO GROUND
Chip Topography
V
CC
LOL
GND
GND
FIL+
FIL-
GND
V
CC
GND
GND
V
CC
SDI+
SDI-
V
CC
SIS
GND
GND
V
SLBI+
CC
SLBI-
V
CC
CC
N.C.
N.C.
V
0.071"
(1.803mm)
V
CC
SDO+
SDO-
V
CC
V
CC
(1.828mm)
SCLKO+
SCLKO-
V
CC
GND
0.072"
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
10 ______________________________________________________________________________________
Package Information
32L,TQFP.EPS
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
______________________________________________________________________________________ 11
Package Information (continued)
MAX3876
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
NOTES
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