Maxim MAX3832UCB, MAX3831UCB Datasheet

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General Description

The MAX3831/MAX3832 are 4:1 multiplexers (muxes)
and 1:4 demultiplexers (demuxes) with automatic chan­nel assignment. Operating from a single +3.3V supply,
the mux receives four parallel, 622Mbps SDH/SONET
channels. These channels are bit interleaved to gener­ate a serial data stream of 2.488Gbps for interfacing to
an optical or an electrical driver. A 10-bit-wide elastic
buffer tolerates up to ±7.5ns skew between any parallel
data input and the reference clock. An external
155MHz reference clock is required for the on-chip PLL
to synthesize a high-frequency 2.488GHz clock for tim­ing the outgoing data streams.

The MAX3831/MAX3832’s demux receives 2.488Gbps
serial data and the 2.488GHz clock from an external
clock/data recovery device (MAX3876), converting it to
four 622Mbps LVDS outputs. The MAX3831 provides a
622MHz LVDS clock output, and the MAX3832 pro­vides a 155MHz LVDS clock output. An internal frame
detector looks for a 622Mbps SDH/SONET framing pat­tern and rolls the demux to maintain proper channel
assignment at the outputs.

These devices also include an embedded pattern gen­erator that enables a full-speed, built-in self-test (BIST).
Two different loopback modes provide system test flexi­bility. A TTL loss-of-frame monitor is included. The
MAX3831/MAX3832 are available in 64-pin TQFP-EP
(exposed paddle) packages and are specified over the
upper commercial (0°C to +85°C) temperature range.

Features

♦ +3.3V Single Supply
♦ 1.45W Power Dissipation (MAX3831)
♦ 4-Channel Mux/Demux with Fully Integrated

2.488GHz Clock Generator

♦ Frame Detection Maintains Channel Assignment
♦ ±7.5ns Elastic Store Range
♦ 2.5ps RMS Serial-Data Output Random Jitter
♦ 8ps Serial-Data Output Deterministic Jitter
♦ 622Mbps LVDS Parallel Input/Output
♦ 2.488Gbps Serial CML Input/Output
♦ On-Chip Pattern Generator Provides

High-Speed BIST

♦ System Test Flexibility: System Loopback,

Line Loopback

♦ Loss-of-Frame Indicator

Applications

SDH/SONET Backplanes ATM Switching Networks

High-Speed Parallel Links Line Extenders

Intrarack/Subrack Dense Digital Cross­Interconnects Connects

MAX3831/MAX3832

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

________________________________________________________________ Maxim Integrated Products 1

19-1534; Rev 1; 10/99

Typical Application Circuit

Ordering Information

PART

MAX3831UCB

MAX3832UCB

0°C to +85°C

0°C to +85°C

TEMP. RANGE PIN-PACKAGE

64 TQFP-EP

64 TQFP-EP

Pin Configuration appears at end of data sheet.

PLBEN

+3.3V

V

SCLKI-

SCLKI+

SDI-

SDI+

SDO+

SDO-

LBEN

RSETFR

0.1µF

CC

CML

CML

MAX3876

2.5Gbps
CDR

TTL

TTL

2.5Gbps

OPTICAL

TRANSCEIVER

TTL

RSETES

155MHz REF

CLOCK INPUT

CMOS

OVERHEAD

LVDS

4

LVDS

4

LVDS

LVDS

RCLKI+

RCLKI­PDI1+ TO PDI4+

PDI1- TO PDI4-

4

PDO1+ TO PDO4+

4

PDO1- TO PDO4-

PCLKO+

PCLKO-

0.33µF

FIL+ FIL-

TRIEN

MAX3831
MAX3832

TTL

TTL TTL TTL

TEST

LOF

GND

MAX3831/MAX3832

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at T

A

= +25°C and VCC= +3.3V.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Positive Supply Voltage (VCC)...............................-0.5V to +5.0V

Input Voltage (LVDS, TTL)..........................-0.5V to (V

CC

+ 0.5V)

CML Input Voltage ..........................(V

CC

- 0.8V) to (VCC+ 0.5V)

FIL+, FIL- Voltage.......................................-0.5V to (V

CC

+ 0.5V)

TTL Output Voltage ....................................-0.5V to (V

CC

+ 0.5V)

LVDS Output Voltage ..................................-0.5V to (V

CC

+0.5V)

CML Output Currents..........................................................22mA

Continuous Power Dissipation (T

A

= +85°C) (Note 1)

64-Pin TQFP-EP (derate 40.0mW/°C above +85°C) .........2.6W

Operating Temperature Range...............................0°C to +85°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

Short outputs together (Note 3)

TRIEN = V

CC

TRIEN = GND

Figure 1

LVDS input, VOS= 1.2V

CONDITIONS

V

VCC- VCC+

0.6 0.4

V

IS

Single-Ended Input Voltage Range

VVCC- 0.2Output Common-Mode Voltage

Ω85 100 115Differential Output Impedance

mVp-p640 800 1000V

ODp-p

Differential Output Voltage

mA12Output Current

Ω80 120

Differential Output Impedance

MΩ>1

mV±25

∆VOS

Change in Magnitude of Output
Offset Voltage for Complementary
States

V1.125 1.275V

OS

Output Offset Voltage

mV±25

∆VOD

Change in Magnitude of
Differential Output Voltage for
Complementary States

mA

440 580

I

CC

Supply Current

mV250 400

VOD

Differential Output Voltage

V0.925V

OL

Output Voltage Low

V1.475V

OH

Output Voltage High

µA270I

OS

Input Common-Mode Current

mV0 2400V

IN

Input Voltage Range

mV-100 +100V

IDTH

Differential Input Threshold

mV90V

HYST

Threshold Hysteresis

Ω85 100 115R

IN

Input Impedance

UNITSMIN TYP MAXSYMBOLPARAMETER

Figure 2

Ω85 100 115Differential Input Impedance

mVp-p400 1200Differential Input Voltage Swing

LVDS INPUTS AND OUTPUTS

CML INPUTS AND OUTPUTS

Note 1: Based on empirical data from the MAX3831/MAX3832 evaluation kit.

CML inputs and outputs open,
LVDS input VOS= 1.2V (Note 2)

MAX3831

MAX3832 480 614

MAX3831/MAX3832

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at T

A

= +25°C and VCC= +3.3V.)

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, LVDS differential load = 100Ω ±1%, CML load = 50Ω ±1% to VCC, all TTL inputs are open, TA= 0°C to
+85°C, unless otherwise noted. Typical values are at T

A

= +25°C and VCC= +3.3V.) (Note 4)

TRIEN = GND

IOL= 2mA

IOH= 20µA

VIH= 2.0V

VIL= 0

CONDITIONS

kΩ6Output Impedance

V0.4V

OL

Output Voltage Low

V2.4V

OH

Output Voltage High

V2.0V

IH

Input Voltage High

V0.8V

IL

Input Voltage Low

µA-250 -50I

IH

Input Current High

µA-550 -100I

IL

Input Current Low

UNITSMIN TYP MAXSYMBOLPARAMETER

Note 2: When TEST = GND, the pattern generator will consume an additional 30mA.
Note 3: Guaranteed by design and characterization.

(Note 7)

(Note 5)

20% to 80%

CONDITIONS

ps

p-p

818SDJ

Serial-Data Output Deterministic
Jitter

ps

RMS

3.5

Mbps622.08Parallel Input Data Rate

ns±7.5t

es

Maximum Parallel Input Skew

Gbps2.48832Serial-Data Output Rate

ps120tr, t

f

Serial-Data Output Rise/Fall Time

UNITSMIN TYP MAXSYMBOLPARAMETER

Figure 3

Figure 3

Mbps622.08PDO±Parallel-Data Output Rate

Gbps2.48832Serial-Data Input Rate

ps100t

SU

Serial-Data Setup Time

ps100t

H

Serial-Data Hold Time

(Note 6)

ps

p-p

40

SRJSerial-Data Output Random Jitter

TTL INPUTS AND OUTPUTS

MAX3831

PCLKO±Parallel-Clock Output Frequency MHz

622.08

MAX3831, Figure 3t

CLK-Q

PCLKO to PDO_ Delay ps-100 90 300

Any differential pairt

SKEW1

LVDS Differential Skew ps65

PDO1± to PDO4±t

SKEW2

LVDS Channel-to-Channel Skew ps<100

LVDS Three-State Enable Time ns30

Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Relative to the positive edge of the 155MHz reference clock. PDI1 to PDI4 aligned to RCLKI at reset.
Note 6: Measured with a reference clock jitter of <1ps

RMS

.

Note 7: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse-width distortion.

MAX3832 155.52

20% to 80%LVDS Output Rise/Fall Time ps350

4:1 MULTIPLEXER WITH CLOCK GENERATOR

1:4 DEMULTIPLEXER

MAX3831/MAX3832

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel
Interconnect Mux/Demux ICs with Clock Generator

4 _______________________________________________________________________________________

Figure 1. Definition of the LVDS Output

Figure 2. Definition of the CML Input

Figure 3. Timing Parameters

PDO+

V

D

PDO-

V

PDO-

SINGLE-ENDED OUTPUT

V

PDO+

DIFFERENTIAL OUTPUT

0V (DIFF)

R

= 100Ω

L

V

|

OD|

V

OD

V

OH

V

OS

V

OL

+V

OD

0V

V

= V

PDO+

- V

PDO-

ODp-p

-V

OD

SCLKI

SDI

PCLKO

PDO1–PDO4

SDI+

SDI-

(SDI+) - (SDI-)

t

SCLK

= 1 / f

SCLK

V

ID

t

SU

t

CLK-Q

200mV MIN
600mV MAX

400mVp-p MIN
1200mVp-p MAX

t

H

NOTE: SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLKI = (SCLKI+) - (SCLKI-).

MAX3831/MAX3832

+3.3V, 2.5Gbps, SDH/SONET, 4-Channel

Interconnect Mux/Demux ICs with Clock Generator

_______________________________________________________________________________________ 5

Typical Operating Characteristics

(VCC= +3.3V, TA = +25°C, unless otherwise noted.)

SERIAL-DATA OUTPUT EYE DIAGRAM

MAX3831/2 toc01

223-1 PRBS PATTERN

50ps/div

ELASTIC STORE RANGE

10

8

6

4

2

0

-2

-4

-6

-8

VARIATION OF DATA DELAY AFTER RESET (ns)

-10
0 0.4 0.60.2 0.8 1.0 1.2 1.4 1.6

ERROR-FREE OPERATION

CHANNEL ALIGNED TO RCLKI

DATA TO RCLKI DELAY AT RESET (ns)

SERIAL-DATA OUTPUT JITTER

WIDEBAND RMS

JITTER = 2.48ps

5ps/div

100

MAX3831/2 toc04

80

60

40

HOLD TIME (ps)

20

0

-20

-50 0 25-25 50 75 100

SUPPLY CURRENT vs. TEMPERATURE

600

MAX3831/2 toc02

500

400

300

200

SUPPLY CURRENT (mA)

100

0

-50 0 25-25 50 75 100

SERIAL-DATA HOLD TIME

TEMPERATURE (°C)

MAX3832

MAX3831/2 toc03

MAX3831

TEMPERATURE (°C)

MAX3831/2 toc05

PARALLEL CLOCK-TO-DATA OUTPUT

MAX3831

SERIAL-DATA SETUP TIME

100

80

60

40

SETUP TIME (ps)

20

0

-50 0 25-25 50 75 100
TEMPERATURE (°C)

MAX3831/2 toc06

PROPAGATION DELAY vs. TEMPERATURE

300

250

200

150

100

50

PCLKO TO PDO_ PROPAGATION DELAY (ps)

0

-50 0 25-25 50 75 100
TEMPERATURE (°C)

MAX3831/2 toc07