MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
________________________________________________________________
Maxim Integrated Products
1
19-4109; Rev 0; 7/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
General Description
The MAX3816A DDC*/I2C extender automatically compensates for excess load capacitance of long DVI™, HDMI™,
and VGA cables. A single MAX3816A placed at the display side of the link restores signal integrity bidirectionally
for both DDC clock and data over 0 to 60 meters of cable.
The MAX3816A features compensation for cable
capacitance with a guaranteed range up to 3000pF,
typically beyond 5000pF. The MAX3816A detects statechange assertion by the logical “AND” of the source
side and display side. It asserts the new state with a
rail-to-rail slew-rate-limited driver capable of meeting
I2C rise- and fall-time requirements under the full load
of the cable. After assertion of the new state, a holdoff
period of 2.5µs prevents a subsequent state change
while the cable channel settles.
Under full load at 100kbps, the MAX3816A consumes
25mW, excluding pullup resistors. It is available in a
16-pin TSSOP package and operates from 0°C to +70°C.
Applications
Front-Projector DVI/HDMI Inputs
High-Definition Televisions, Displays, and
Computer Monitors
DVI/HDMI Cable-Extender Modules and Active
Cable Assemblies
Features
♦ DDC or I2C Cable Extension Up to 60 Meters at
100kbps for Both Clock and Data Channels
♦ Single-Sided Solution Requires Only One
MAX3816A at the Display Side
♦ Compensates for Cable Capacitance, 0 to 3000pF
Guaranteed (8x I2C Specification), or Beyond
5000pF Typical
♦ Parallel and Serial Operating Modes
♦ Prevents Ringing Due to Reflections by
Terminating Transmission Line Impedance After
Transitions
♦ Use with MAX3815 TMDS®Equalizer to Form a
Complete Digital Video Extension Solution
♦ 3.0V to 5.5V Power Supply
♦ Optional Voltage Translation Between 5V Cable
DDC and 3.3V Display DDC Levels
Typical Application Circuit (Parallel Mode)
Ordering Information
+
Denotes a lead-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
*DDC (Display Data Channel) is part of the VESA Standard.
TMDS is a registered trademark of Silicon Image, Inc.
DVI is a trademark of Digital Display Working Group.
HDMI is a trademark of HDMI Licensing, LLC.
LONG CABLE FROM VIDEO SOURCE:
DVI, HDMI, OR CAT-5 CABLE UP TO 60m
SHIELD GNDS
DDC +5V
DDC SCL
DDC SDA
DDC GND
(200ft)
47kΩ47kΩ
V
CC
10μF
10μF
MAX3816ACUE+ 0°C to +70°C 16 TSSOP
5V*
V
CC
MAX3816A
CLOCK_C
DATA_C
GND_REF
CABLE HEAD OR EXTENDER BOX
V
CLOCK_D
DATA_D
MODE
DRVR_EN
V
DD
PART TEMP RANGE PIN-PACKAGE
CONNECTOR TO DISPLAY
DVI, HDMI, OR M1 CONNECTOR, < 3m
DDC +5V
DDC SCL
DDC SDA
V
DD
VDD OR VSS (SEE DESCRIPTION)
SS
DDC GND
SHIELD GNDS
*TO MEET DVI/HDMI SPECIFICATIONS FOR THE DDC +5V LINK, THE VDD SIDE OF THE MAX3816A MUST BE EXTERNALLY POWERED. IF NOT APPLICABLE, CONNECT TO DDC +5V.
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +5.5V, VDD= +3.0V to +5.5V, TA= 0°C to +70°C. Typical values are at TA= +25°C, VCC= +5.0V, VDD= +3.3V,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range (relative to VSS) at VDD, VCC,
CLOCK_D, DATA_D, CLOCK_C, DATA_C,
DRVR_EN, MODE ..................................................-0.5V to +6.0V
Continuous Power Dissipation (T
A
= +70°C)
(derate 11.1mW/°C above +70°C)..............................889mW
Voltage Range (relative to V
SS
) at GND_REF .......-0.5V to +0.5V
Operating Junction Temperature (T
J
) Range ....-55°C to +150°C
Storage Ambient Temperature (T
S
) Range .......-40°C to +150°C
Electrostatic Discharge (ESD)
Human Body Model......................................................> ±3kV
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUP PLY
Supply Voltage VCC or V
I
CC
Supply Current
I
DD
Supply Noise Tolerance
CLOCK_C, DATA_C, CLOCK_D, DATA_D (Notes 2, 3)
Output-High Voltage V
Output-Low Voltage
High-to-Low Threshold V
Low-to-High Threshold V
Output-High-State Current Lim it Output in ramp-up mode for DATA_C 5.0 16.5 mA
OH
V
OL
V
HOLD
TRI GIH
TRI GIL
See the Applications Information section
DD
(Note 1)
VCC = 5.5V, VDD = 5.5V, 100kbp s,
60pF load on cable, 10pF load on displa y,
current into V
VCC = 5.5V, VDD = 5.5V, 100kbp s,
60pF load on cable, 10pF load on displa y,
current into V
DC to 500kHz 100
DC to 60Hz (series mode) 700
Cable side (CLOCK_C, DATA_C) VCC - 0.1 V
Display side (CLOCK_D, DATA_D) VDD - 0.1 V
VOL achieved within 1μ s of negative
transition (see Figure 1a, State 2)
After VOL is achieved, V
the most positive leve l allowed
if logic level is 0 and no other
driver is asserting low on the
same node (series mode)
Threshold u sed to detect high-to-low
transition relative to supply (V
side, V
DD
Threshold u sed to detect low-tohigh transition relative to supply
(V
for cable side, VDD for
CC
display side)
pin
CC
pin
DD
HOLD
for display side)
is
for cable
CC
Cable
side
Display
side
Cable
side
Display
side
3.0 5.5 V
1.3 3.0
4.3 7.0
CC
DD
0.2 0.4 V
15
20
75
12.5
17.5
mA
mV
P-P
V
% of
Supply
% of
Supply
% of
Supply
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
_______________________________________________________________________________________ 3
Note 1: While the MAX3816A is operable over the continuous range of 3.0V to 5.5V, the DDC application requires VCCconnection to
DDC +5V.
Note 2: All levels in the cable side clock and data I/O are referenced to GND_REF, unless otherwise noted.
Note 3: All levels in the display side clock and data I/O are referenced to V
SS
, unless otherwise noted.
Note 4: Rise time measured 30% to 70%; fall time measured 70% to 30%. Load range is 60pF to 3000pF on source side, and 10pF
to 400pF on display side. Pullup resistors are chosen to supply I
2
C maximum of 3mA when asserting low state.
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +5.5V, VDD= +3.0V to +5.5V, TA= 0°C to +70°C. Typical values are at TA= +25°C, VCC= +5.0V, VDD= +3.3V,
unless otherwise noted.)
ICC vs. V
CC
MAX3816A toc01
VCC (V)
I
CC
(mA)
5.255.004.75
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
4.50 5.50
100kbps DATA, 100kHz CLOCK,
INCLUDES 3.3kΩ PULLUP RESISTORS
CABLE C
LOAD
= 3000pF
CABLE C
LOAD
= 60pF
IDD vs. V
DD
MAX3816A toc02
VDD (V)
I
DD
(mA)
5.04.54.03.5
1
2
3
4
5
6
7
8
9
10
0
3.0 5.5
100kbps DATA, 100kHz CLOCK, INCLUDES
3.3kΩ PULLUP RESISTORS FOR 5V SUPPLY
RANGE AND 2.2kΩ PULLUP RESISTORS FOR
3.3V SUPPLY RANGE
DISPLAY C
LOAD
= 330pF
DISPLAY C
LOAD
= 10pF
MAX3816A toc03
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 30m CABLE LOAD
(2350pF)
WITH
MAX3816A
WITHOUT
MAX3816A
Typical Operating Characteristics
(VCC= +5.0V, V
DD
= +3.3V, TA= +25°C, unless otherwise noted.)
Rise T ime (Note 4) t
Fal l Time (Note 4) t
Driver On-Time Driver asserting high or low 1750 ns
Driver Acti ve Termination Driver asserting high or low 60
TRANSITION SENSING
Level-Sense Filter Delay Time to transition decision and assert 300 ns
Holdoff Time t
LVTTL/LVCMOS CONTROL INPUTS (DRVR_EN, MODE)
Input-High Voltage VIH 2.0 V
Input-Low Voltage VIL 0.8 V
Input-High Current IIH V
Input-Low Current IIL VIN < V
PARAMETER S YMBOL CONDITIONS MIN TYP MAX UNITS
3.0V to 3.6V supply 700 1000
R
4.5V to 5.5V supply 700
3.0V to 3.6V supply 200 300
F
4.5V to 5.5V supply 300
HOLDOFF
Data/clock sensing off during this period 2.5 μs
< VIN -1 +1 μA
IH(MIN)
-1 +1 μA
IL(MAX)
ns
ns
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
4 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC= +5.0V, V
DD
= +3.3V, TA= +25°C, unless otherwise noted.)
MAX3816A toc04
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 30m CABLE LOAD
(3100pF)
WITH
MAX3816A
WITHOUT
MAX3816A
MAX3816A toc05
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 60m CABLE LOAD
(4700pF)
WITH
MAX3816A
WITHOUT
MAX3816A
MAX3816A toc06
1V/div
2μs/div
3.3kΩ PULLUP RESISTOR AT EACH END OF CABLE.
PULLDOWN SOURCE: 25Ω CMOS SWITCH SIGNAL
INITIATED AND MEASURED AT REMOTE SOURCE.
DATA_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 60m CABLE LOAD
(4700pF)
WITH
MAX3816A
WITHOUT
MAX3816A
MAX3816A toc07
1V/div
2μs/div
PULLUP RESISTORS: TWO 3.3kΩ IN PARALLEL.
PULLDOWN SOURCE: 25Ω CMOS SWITCH.
CLOCK_C TRANSIENT RESPONSE
WITH AND WITHOUT MAX3816A, 62pF CABLE LOAD
WITH
MAX3816A
WITHOUT
MAX3816A
CABLE SIDE TRANSITION TIME
vs. CABLE CAPACITANCE
MAX3816A toc08
CAPACITANCE (pF)
30% TO 70% RISE OR FALL (ns)
50004000300020001000
200
400
600
800
1000
1200
0
0 6000
VCC = 5V, 3.3kΩ PULLUP RESISTOR AT EACH
END OF CABLE
RISE TIME
FALL TIME
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VCC= +5.0V, V
DD
= +3.3V, TA= +25°C, unless otherwise noted.)
SERIES MODE TRANSIENT RESPONSE
(3000pF CABLE CAPACITANCE)
REFLECTION ABSORBED BY MAX3816A
VIDEO SOURCE
CLOCK
5V/div
VIDEO SOURCE
DATA
5V/div
DISPLAY CLOCK
5V/div
DISPLAY DATA
5V/div
(% OF SUPPLY VOLTAGE)
HOLD
V
2μs/div
50m CABLE ON SOURCE SIDE, 330pF CAPACITANCE
ON DISPLAY SIDE, V
DATA INITIATED AT VIDEO SOURCE AND MEASURED
AT MAX3816A
V
40
35
30
25
20
15
10
5
0
HOLD
DISPLAY SIDE (REFERENCED
TO V
CABLE SIDE (REFERENCED
TO V
DD
-0.6 0.6
= 5V, VDD = 5V CLOCK AND
CC
vs. (VSS - GND_REF)
RELATIVE TO VSS)
DD
RELATIVE TO GND_REF)
VSS - GND_REF (V)
0.40.2-0.4 -0.2 0
MAX3816A toc09
MAX3816A toc11
CLOCK_C AT
MAX3816A
2V/div
CLOCK_C AT
REMOTE CLIENT
2V/div
(% OF SUPPLY VOLTAGE)
TRIGIL
V
REFLECTION
ABERRATION AT
CLOCK_C PIN
NOT SEEN AT SOURCE
ACTUAL SIGNAL
AT VIDEO SOURCE
1μs/div
60m CABLE, SIGNAL INITIATED AT DISPLAY SIDE
V
vs. (VSS - GND_REF)
30
25
20
15
10
5
0
TRIGIL
DISPLAY SIDE
(REFERENCED TO V
(REFERENCED TO V
-0.6 0.6
VSS - GND_REF (V)
)
DD
CABLE SIDE
)
CC
0.40.20-0.2-0.4
MAX3816A toc10
MAX3816A toc12
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
6 _______________________________________________________________________________________
Pin Description
Theory of Operation
The MAX3816A has parallel and series modes. The
parallel mode is preferred for applications where high
tolerance to noncompliant source and sink devices is
desired (noncompliant VOLfrom displays and noncompliant VIHfrom sources are common). Further, the parallel mode can be operated with other speed-up
devices on the same bus, either active (DRVR_EN = HI)
or in bypass (DRVR_EN = LO).
Series mode is preferred for applications where high
tolerance to ground offset or noise between and source
and sink is needed. Series mode also isolates display
circuits from transmission line reflections in very long
cables, providing full isolation between cable and display buses. For in-display applications, series mode
can provide level shifting between the 5V cable DDC
and 3.3V display internal DDC.
A single MAX3816A is applied at the display side of the
video link to compensate for excessive cable capacitance. The overall operation of the MAX3816A, for
either the DATA or CLOCK signal, can be summarized
as follows (Figures 1a and 1b).
1) High state. Drivers off. Level sensing on.
If no client device is controlling the “wired-AND” bus
from either the source or display side, all device drivers are off and the bus (including the MAX3816A)
is waiting in the high state. The pullup resistors on
each side are holding the bus up to V
CC
on the
source side and VDDon the display side.
2) High-to-low transition. Drivers assert low. Level
sensing off (Holdoff).
A change of state is initiated by any device driver
pulling low. Once the signal transitions below 75%
of the power supply, the MAX3816A drives both the
source and display sides toward ground with a lowimpedance driver, level sensing is turned off, and
the holdoff timer is started. The source side is
pulled down to the level of the VSS. This is accomplished using a low-impedance n-channel buffer
that is designed to drive a 1 meter (60pF) to 60
PIN NAME FUNCTION
1 DRVR_EN
2 V
3 CLOCK_C I2C Cable-Side Cloc k w ith Cable Dri ver, CMOS Input/Output. Connect a 47k pullup resistor to VCC.
4 GND_REF
5 DATA _C I2C Cable-Side Data with Cable Driver, CMOS Input/Output. Connect a 47k pullup resistor to VCC.
6 GND_REF Cable-Side Ground Return (Alternate). Connected internal ly to pin 4 above.
7 VCC Power Supply for Cable Side (Alternate). Connected internally to pin 2 above.
8, 9, 10 DNC Do Not Connect
11 VDD Power Supply for Display Side and Core Circuitry. Connect bypass capacitor as shown in Figure 6.
12 DATA _D
13 VSS Ground for Display Side and Core Circuitr y. Connect bypass capacitor s as s hown in Figure 6.
14 CLOCK_D
15 V
16 MODE
CC
SS_T
Driver Enable Input, LVTTL/LVCMOS. Set h igh to enable all data and clock drivers for normal
operation. Set low to disable drivers, permitting isolation of cable bus from disp lay bus.
Power Supply for Cable Side. In the DDC application, connect to DDC +5V. Connect 10μF or larger
bypass capacitor as shown in Figure 6.
Cable-Side Ground Return. Connect directly to cable DDC ground wire. The MAX3816A circuitry use s
the video source DDC GND as a threshold reference. Also connect 10μF or larger bypass capacitors
as shown in Figure 6.
2
I
C Display-Side Data, CMOS Input/Output. Connect a 2.2k pullup res istor to VDD for VDD = 3.3V,
or a 3.3 k pullup resistor to V
2
I
C Display-Side Clock, CMOS Input/Output. Connect a 2.2k pullup resistor to VDD for VDD = 3.3V,
or a 3.3 k pullup resistor to V
Must Be Connected to VSS for Normal Operation
Mode Setting Input, LVTTL/LVCMOS. Force high for parallel mode (normal operation) and force low for
serial operation.
for VDD = 5V.
DD
for VDD = 5V.
DD
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
_______________________________________________________________________________________ 7
meter (> 3000pF) cable with a controlled slew-rate.
Similarly, the display side is pulled down to VSSwith
a controlled slew rate, open-drain n-channel MOS
device. These buffers stay on for 1.75µs.
3) Low state. Level sensing off (Holdoff).
Level sensing remains off until the completion of the
holdoff period, which is 2.5µs on both the clock and
data channels.
In series mode, drivers maintain low level (at or
below V
HOLD
). Either the client pulldowns sustain
the level below VOL, or the MAX3816A sustains the
level at V
HOLD
if no other driver on the same node
is pulling down. This action is in support of the
“wired-AND” function across source and display
sides.
4) Low state, drivers off. Level sensing on.
After the MAX3816A holdoff time completes, level
sensing resumes.
In series mode, the MAX3816A supports a “wiredAND” connection between source and display
sides; returning to the high state is supported only
when all client sources turn off. If either the source
or display side releases the bus, but not both, a
MAX3816A level-sensing buffer senses the transition at V
TRIGIL
, supporting the existing low state by
clamping the voltage to V
HOLD
and waiting for the
remaining side to release the bus.
5) Low-to-high transition. Drivers on. Level sensing
off (Holdoff).
A change of state is initiated when no device is
holding the bus low on both source and display
sides. When both sides exceed their respective
V
TRIGIL
levels, the source side turns on a slew-rate
controlled open-drain p-channel device, pulling up
to VCCfor 1.75µs. Simultaneously, the display side
is released and the pullup resistors pull the displayside bus up to VDD, as per normal I2C operation.
6) High state. Drivers off. Level sensing off
(Holdoff).
During holdoff, no transitions are sensed. The high
state is maintained by external pullup resistors. Upon
the end of holdoff, when the cable and display levels
are above 85%, the state machine transitions to state
(1); otherwise, it waits until levels raise above 85% to
transition to state (1). Data, but not clock, has another exit from state (6) to (1) upon data source or data
display levels dropping below 60%.
I2C continuous clock applications are not recommended for the MAX3816A. The MAX3816A is optimized for
DDC applications with a noncontinuous clock.
Detailed Description
The MAX3816A DDC/I2C 2-wire extender consists of
two controllers with level-shifters, cable drivers, display
drivers, and level-sensing circuitry (Figure 2).
Controllers and Level Shifters
The MAX3816A functionality is governed by two controllers, one for CLOCK and one for DATA. Bidirectional
signaling is fully supported on both CLOCK and DATA.
The primary function of the controllers is to receive the
state-change information from the source- and displayside level-sense circuitry and support the “wired-AND”
function between the two. When the state changes, a
holdoff period is timed during which the source and
display drivers assert the next state, high or low, and all
input sensing is ignored while I/O transients settle
(Figure 3). The holdoff period is approximately 2.5µs.
The cable transmission-line termination feature is active
only during the first 1.75µs of holdoff, sufficiently long
enough to absorb roundtrip reflections from a 60m
cable.
In series mode, the CLOCK and DATA controllers isolate the source electronics from the display electronics.
The cable side of the MAX3816A is referenced to V
CC
and GND_REF, and the display side is referenced to
VDDand VSS. This power scheme provides tolerance to
offset and noise between the source and display
devices.
Cable Drivers
The low-impedance cable drivers (Figure 10) can
charge and discharge at least 3000pF of capacitive
cable load within the I2C rise and fall time limits. The
drivers each incorporate a slew-rate limiter to control
the amount of high-frequency energy transmitted. The
cable drivers also provide a back termination impedance of approximately 60Ω to absorb transmission-line
reflections returning to the driver. The cable drivers
each include a high-state current-limiting feature to
clamp the output current to less than 16mA.
After 1.75µs of driver assertion, following a decision to
transition, the low-impedance drivers are turned off.
Subsequently, when another device asserts a new
state, it does not have to work against the low impedance of the MAX3816A.
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
8 _______________________________________________________________________________________
Figure 1a. Clock State Machine Diagram
Locally, connect a 47kΩ pullup resistor from CLOCK_C
and DATA_C to VCC. This assumes that a 1.65kΩ
pullup resistor resides at the opposite end of each
channel.
Display Drivers
The display drivers (Figure 11) are typical open-drain
pulldown devices capable of discharging up to 400pF
of capacitive load within the I2C fall-time limits.
Locally, connect a 2.2kΩ pullup resistor from CLOCK_D
and DATA_D to VDDfor VDD= 3.3V, or a 3.3kΩ pullup
resistor to VDDfor VDD= 5V.
Level Sense
The MAX3816A’s level-sensing circuitry monitors the
incoming data for state transitions. When the CLOCK or
DATA signal is high and drops below V
TRIGIH
, the controller ramps the outputs low. When the DATA and
CLOCK are low and both rise above V
TRIGI
L
, referenced to GND_REF on the source side or VSSon the
display side, the output drives the level high.
HIGH
STAT E
CLOCK_C “OR” CLOCK_D < 75%
1
SENSE ON
DRIVERS OFF
HOLDOFF TIMER ≥ 2.5
“AND”
CLOCK_C “AND” CLOCK_D > 85%
s
μ
LOW
STAT E
HOLDOFF TIMER = START
2
SENSE OFF
DRIVERS ON
RAMP
DOWN
HOLDOFF TIMER = 1.75
s
μ
6
SENSE OFF
DRIVERS OFF
HOLDOFF TIMER = 1.75 s
RAMP
UP
HOLDOFF TIMER = START
NOTES:
1) STATE CHANGE CONDITIONS ARE IN ITALICS. TRANSITION ACTIONS ARE UNDERLINED.
2) THE DATA CHANNEL STATE MACHINE IS IDENTICAL AND SYMMETRIC, EXCEPT THAT HOLDOFF TIME IS 2.0μs INSTEAD OF 2.5μs.
ALSO, IN ADDITION TO THE 85% CONDITION TO EXIT STATE 6, DATA HAS AN ADDITIONAL EXIT: DATA_C “OR” DATA_D < 60%.
3) DEPENDENT ON MODE PIN 16: MODE = LOW FOR SERIAL OPERATION (DRIVERS HOLD); MODE = HIGH FOR PARALLEL OPERATION (DRIVERS OFF).
μ
5
SENSE OFF
DRIVERS ON
3
SENSE OFF
(NOTE 3)
HOLDOFF TIMER = 2.5 s
4
SENSE ON
(NOTE 3)
CLOCK_D > 17.5% AND CLOCK_C > 12.5%
μ
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
_______________________________________________________________________________________ 9
CABLE/
Figure 1b. Signal Waveform Example Showing States
SOURCE
SIDE
(NOTE 1)
STAT E
NUMBER
V
DDC VIH = 70% V
DDC VIL = 30% V
DDC VOL(max) = 0.4V
GND
V
XX
V
= 75% V
XX
XX
XX
TRIGIH
XX
3
1 124
= 12.5% VCC CLOCK_C,
V
TRIGIH
17.5% VDD CLOCK_D
5
6
DDC VIH = 70% V
DISPLAY
SIDE
(NOTE 1)
DDC VIL = 30% V
DDC VOL(max) = 0.4V
NOTES:
1) THIS EXAMPLE APPLIES TO TRANSMISSION IN EITHER DIRECTION. SOURCE TO DISPLAY IS SHOWN.
IS USED GENERICALLY FOR THE VOLTAGE AT THE VCC OR VDD PINS.
2) V
XX
XX
XX
GND
0μsHOLDOFF TIMER
= 15% VCC CLOCK_C,
V
HOLD
20% VDD CLOCK_D
0μs 1.75μs 2.5μs1.75μs 2.5μs
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
10 ______________________________________________________________________________________
Figure 2. Functional Diagram
DRVR_EN
V
DD
CMOS
V
DRIVER ENABLE
CABLE DRIVER
SS
V
CC
V
CC
V
DD
MAX3816A
DRIVER_ENABLE (INTERNAL)
DISPLAY
DRIVER
CLOCK_C
DATA_C
LPF
CABLE DRIVER
CABLE
TERMINATION
RESISTORS
V
SS
LEVEL SENSE
V
TRIGIH
V
TRIGIL
DRIVER_ENABLE (INTERNAL)
V
CC
CABLE
TERMINATION
RESISTORS
V
SS
GND_REF
GND_REF
CONTROLLER AND
LEVEL SHIFTER
V
CC
CONTROLLER AND
LEVEL SHIFTER
CLOCK_D
V
SS
V
SS
LEVEL SENSE
V
DD
CMOS
V
DD
V
SS
V
SS
V
TRIGIH
V
TRIGIL
DRIVER_ENABLE (INTERNAL)
V
SS
DISPLAY
DRIVER
LPF
MODE
DATA_D
LEVEL SENSE
V
V
TRIGIH
TRIGIL
LPF
LEVEL SENSE
V
V
TRIGIH
LPF
TRIGIL
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
______________________________________________________________________________________ 11
Figure 4. Holdoff with Decision Points Shown
Figure 3. Holdoff Operation
CLOCK_C
OR
DATA_C
DATA
CLOCK
t
HOLDOFF_D
WITH
MAX3816A
V
TRIGIL
t
HOLDOFF
WITHOUT
MAX3816A
O = DECISION POINT
V
TRIGIH
t
HOLDOFF
t
HOLDOFF_C
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
12 ______________________________________________________________________________________
Figure 5. Typical In-Display Application Circuit
Applications Information
Use Single MAX3816A at Display Side
A single MAX3816A is designed to achieve full
100kbps operation over 60m (200ft) of cable.
In-Display Application, Series Mode
When inserted at the front-end of a display, the source
side of the MAX3816A should be powered by the
source VCC(typically 5V) and ground (GND_REF). The
display-side VDDshould be powered by the local display supply (typically 3.3V) to level-shift and diminish
the effects of supply noise and offset between source
and display (Figure 5). Supply decoupling capacitors of
at least 10µF should be connected close to the
MAX3816A between GND_REF and VSS, as well as
between GND_REF and VCC.
MAX3816A In-Display, Series Mode Advantages
(See Figure 5)
• Long cable reach.
• The MAX3816A acts as a buffer between source and
display. Hence, source reflections are isolated to the
source side of the MAX3816A, protecting display circuits from reflections (stair-step waveforms).
• The MAX3816A can be turned off (DRVR_EN asserted low) to isolate source and display buses. The display bus can then operate independently of
source-cable loading or malfunctions.
• Multiple MAX3816As can be used in parallel as an
input mux to display, with only one “on” at a time.
Consideration
When using the level-shifter feature, as shown, and assuming the display 3.3V supply is off when the display is off,
the Display EDID Prom will not be able to communicate to
source DDC. If required, the solution is to either place a 5V
EDID Prom on the source side of the MAX3816A or derive
the 3.3V VDDfrom the DDC +5V supply.
LONG CABLE FROM VIDEO SOURCE:
DVI, HDMI, OR M1 CONNECTOR
CABLE UP TO 60m (200ft)
DDC +5V
DDC SCL
DDC SDA
DDC GND
SHIELD GNDS
V
CC
47kΩ 47kΩ 2.2kΩ 2.2kΩ
MAX3816A
CLOCK_C
DATA_C
V
CC
GND_REF
10μF
10μF
GROUND PLANE
DISPLAY CIRCUIT BOARD
V
DD
CLOCK_D
DATA_D
MODE
DRVR_EN
V
V
SS
VDD OR VSS (SEE DESCRIPTION)
SS
V
DD
1μF
2
C BUS
DISPLAY I
REFERENCE TO 3.3V
DISPLAY 3.3V
I2C SCL
2
I
C SDA
DISPLAY GND
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
______________________________________________________________________________________ 13
External Box or Cable Assembly
Applications
Three implementations external to the display such as
external box products or cable assemblies are shown
in Figures 6, 7, and 8.
MAX3816A External to Display, In Series
Advantages (See Figure 6)
• Long cable reach.
• The MAX3816A acts as a buffer between the source
and display. Hence, source reflections are isolated
to the source side of the MAX3816A, protecting display circuits from possible double clocking due to
stair-step waveforms caused by very long cables
with reflections.
• The MAX3816A can be turned off (DRVR_EN asserted low) to isolate source and display buses. The display bus can then operate independently of
source-cable loading or malfunctions. Also, multiple
MAX3816As can be used in parallel as an input mux
to display, with only one “on” at a time.
Consideration
Only one series-connected MAX3816A is allowed on a
bus. Two or more series-connected MAX3816A ICs will
not function. If multiple MAX3816A ICs are expected,
use the parallel applications in Figures 7 and 8.
Figure 6. External to Display, In Series
LONG CABLE FROM VIDEO SOURCE:
DVI, HDMI, OR CAT-5 CABLE UP TO 60m
(200ft)
CONNECTOR TO DISPLAY
DVI, HDMI, OR M1 CONNECTOR, < 3m
5V*
DDC +5V
V
47kΩ 47kΩ 3.3kΩ 3.3kΩ
DDC SCL
DDC SDA
V
CC
10μF
DDC GND DDC GND
10μF
SHIELD GNDS
*TO MEET DVI/HDMI SPECIFICATIONS FOR THE DDC +5V LINK, THE V
IF NOT APPLICABLE, CONNECT TO DDC +5V.
CC
MAX3816A
CLOCK_C
DATA_C
RETURN
GROUND PLANE
CABLE HEAD OR EXTENDER BOX
SIDE OF THE MAX3816A MUST BE EXTERNALLY POWERED.
DD
V
CLOCK_D
DATA_D
MODE
DRVR_EN
V
DD
V
SS
VDD OR VSS (SEE DESCRIPTION)
SS
DDC +5V
DDC SCL
DDC SDA
SHIELD GNDS
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
14 ______________________________________________________________________________________
MAX3816A External to Display, Switchable Series
and Parallel Mode Advantages (See Figure 7)
• Long cable reach.
• In parallel mode, the MAX3816A is very tolerant of
noncompliant DDC sources and sinks.
• The MAX3816A can be turned off and bypassed if
another MAX3816A or speed-up device is being
used on the same DDC.
• In parallel mode, the MAX3816A can be used simultaneously with other I2C speed-up devices.
• The MAX3816A acts as a buffer between source and
display. Hence, source reflections are isolated to the
source side of the MAX3816A, protecting display
circuits from possible double clocking due to stairstep waveforms caused by very long cables with
reflections.
• In series mode, the MAX3816A can be turned off
(DRVR_EN asserted low) to isolate between source
and display buses. The display bus can then operate independently of source-cable loading or malfunctions.
Consideration
Use a good quality CMOS switch with low resistance
(< 20Ω) and over/undervoltage tolerance.
Figure 7. External to Display, Switchable Series and Parallel Mode
LONG CABLE
FROM SOURCE
47kΩ47kΩ
+5V
SER
PAR
ENA
BYP
+5V
DRVR_EN
CLK_C
DATA_C
MAX3816A
SERIES MODE: DRVR_EN = HI (ENA), MODE = LO (SER)
PARALLEL MODE: DRVR_EN = HI (ENA), MODE = HI (PAR)
BYPASS MODE: DRVR_EN = LO (BYP), MODE = HI (PAR)
ISOLATE MODE: DRVR_EN = LO (BYP), MODE = LO (SER)
MODE
CLK_D
DATA_D
+5V
3.3kΩ
10
MAX4719
+5V
3.3kΩ
10
CONNECTOR
TO DISPLAY
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
______________________________________________________________________________________ 15
MAX3816A External to Display, In Parallel
Advantages (See Figure 8)
• Medium-long cable reach.
• In parallel mode, the MAX3816A is very tolerant of
noncompliant DDC sources and sinks.
• The MAX3816A can be turned off if another
MAX3816A or speed-up device is being used on the
same DDC.
• The MAX3816A can be turned off without isolating
the display from the source side, letting DDC operate straight through unassisted or assisted.
Consideration
Long cable reflections can reach display circuits since
the MAX3816A is not used as a buffer between source
and display. Hence, very long cables could cause double-clocking at display circuits due to stair-step rise/fall
waveforms due to reflections.
Figure 8. External to Display, In Parallel
LONG CABLE FROM VIDEO SOURCE:
DVI, HDMI, OR CAT-5 CABLE UP TO 60m
DDC +5V
DDC SCL
DDC SDA
DDC GND
SHIELD GNDS
*TO MEET DVI/HDMI SPECIFICATIONS FOR THE DDC +5V LINK, THE VDD SIDE OF THE MAX3816A MUST BE EXTERNALLY POWERED. IF NOT APPLICABLE, CONNECT TO DDC +5V.
(200ft)
47kΩ47kΩ
V
CC
MAX3816A
CLOCK_C
DATA_C
V
CC
10μF
GND_REF
10μF
CABLE HEAD OR EXTENDER BOX
5V*
V
DD
CLOCK_D
DATA_D
MODE
DRVR_EN
V
V
DD
VDD OR VSS (SEE DESCRIPTION)
SS
CONNECTOR TO DISPLAY
DVI, HDMI, OR M1 CONNECTOR, < 3m
DDC +5V
DDC SCL
DDC SDA
DDC GND
SHIELD GNDS
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
16 ______________________________________________________________________________________
Figure 9. CLOCK_C/DATA_C Equivalent Interface Structure
Figure 10. CLOCK_D/DATA_D Equivalent Interface Structure
Figure 11. DRVR_EN Equivalent Interface Structure
Interface Schematics
V
CC
V
DD
MAX3816A
SENSE
V
SS
V
CC
CLOCK_C
OR DATA_C
BACK
TERMINATION
DRIVERS
RETURN
RETURN
MAX3816A
SENSE
V
CLOCK_D
OR DATA_D
SS
DRIVER
V
SS
V
DD
MAX3816A
DRVR_EN
V
SS
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
______________________________________________________________________________________ 17
Typical In-Display Operating Circuits
RGB/HV
ADC/SYNC
TMDS
DESERIALIZER
SELECT
IMAGE
SCALER AND
PROCESSOR
PANEL
INTERFACE
TIMING AND
DRIVERS
LCD,
DLP,
OR
LCOS
VGA INPUT
HDMI/DVI-D
INPUT
HDMI/DVI-D CABLE
UP TO 60m OR 200ft
LAPTOP
VIDEO PROJECTOR
TMDS EQUALIZER
MAX3815
MAX3816A
DDC EXTENDER
DRVR_EN
V
CC
CLOCK_C
DATA_C
GND_REF
CLOCK_D
V
SS
DATA_D
V
DD
DDC SCL
DDC SDA
DDC +5V
DDC +5V
FROM
SOURCE
DDC SCL
DDC SDA
DISPLAYGND
DRIVERS
INDISPLAY
DDC EXTENDER
ONE MAX3816A USED AT DISPLAY SIDE OF CABLE
IN CABLE HEAD, OR EXTENDER BOX, OR DISPLAY
DISPLAY CLIENT
CONNECTOR (OR SHORT CABLE < 3m)
TO PROJECTOR, LCD, PLASMA
47kΩ 47kΩ
3.3kΩ
3.3kΩ
10μF
10μF
GROUND PLANE
LONG CABLE
UP TO 60 METERS (200ft)
DVI OR HDMI CABLE, OR CAT-5
SOURCE CLIENT
DDC MASTER IN VIDEO SOURCE:
PC, DVD, STB
V
CC
SHIELDGNDS
DDC SCL
DDC SDA
DDC+5V
DDC GND
DDC SCL
DDC SDA
DDC+5V
SHIELDGNDS SHIELDGNDS
DDC GND DDC GND
VDD OR V
SS
MAX3816A
DDC +5V
DDC SCL
DDC SDA
SOURCEGND
DRIVERS
INSOURCE
R
PULLUPRPULLUP
R
PULLUPRPULLUP
MODE
V
SS
MAX3816A
I2C 2-Wire Extender for DDC in DVI,
HDMI, and VGA Interfaces
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Chip Information
TRANSISTOR COUNT: 5759
PROCESS: CMOS
MAX3815
TMDS EQUALIZER
MAX3816A
DDC EXTENDER
PC MONITOR
UP TO 60m
DVI-D CABLE
UP TO 3m
DVI-D CABLE
DIGITAL CABLE
DIGITAL SATELLITE
DVD PC
DVI-D EXTENDER BOX
VIDEO SOURCE
Typical In-Display Operating Circuits (continued)
Pin Configuration
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 TSSOP U16+2
21-0066
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
TOP VIEW
+
DRVR_EN
CLOCK_C
GND_REF
GND_REF
1
2
V
CC
3
4
5
DATA_C
6
7
CC
16
MODE
15
V
SS_T
CLOCK_D
14
V
MAX3816A
13
SS
12
DATA_D
11
V
DD
DNCV
10
98 DNCDNC
TSSOP
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