MAXIM MAX3815A Technical data

19-4822; Rev 0; 7/09

Typical Operating Circuits

EVALUATION KIT

AVAILABLE

TMDS Digital Video Equalizer for

General Description

The MAX3815A cable equalizer automatically provides
compensation for DVI™ and HDMI™ v1.3 cables. It
extends the usable cable distance up to 40 meters
(1.65Gbps) and 35 meters (2.25Gbps). The MAX3815A
is designed to equalize signals encoded in the transition­minimized differential signaling (TMDS®) format.

The MAX3815A features four CML-differential inputs and
outputs (three data and one clock). It provides a loss-of­signal (LOS) output that indicates loss-of-clock signal.
The outputs include a disable function. Upon LOS, the
chip is powered down. For direct chip-to-chip communi­cation, the output drivers can be switched to one-half the
DVI output specification to conserve power and reduce
EMI. The output drive current can also be increased to
allow the use of back termination resistors for improved
signal integrity. Equalization can be automatic or set to
manual control for specific in-cable applications.

The MAX3815A is available in a 7mm x 7mm, 48-pin
TQFP-EP package and operates over a 0°C to +70°C
temperature range.

HDMI/DVI Cables

Features

Guaranteed Performance to 2.25Gbps (HDMI 1.3),

S

Improved Jitter Performance at Low Source
Amplitude, and Enhanced Output Driver

Extends 2.25Gbps TMDS Interface Length

S

0 to 35 Meters Over HDMI Cable, 24 AWG
0 to 22 Meters Over HDMI Cable, 28 AWG

Extends 1.65Gbps TMDS Interface Length

S

0 to 40 Meters Over HDMI Cable, 24 AWG
0 to 28 Meters Over HDMI Cable, 28 AWG

Compatible with HDTV Resolutions 720p, 1080i,

S

1080p, and 1080p with 36-Bit Color

Compatible with Computer Resolutions VGA,

S

SVGA, XGA, SXGA, UXGA, and WUXGA

Fully Automatic Equalization, No System Control

S

Required

3.3V Power Supply

S

Power Dissipation of 0.6W (typ)

S

7mm x 7mm, 48-Pin TQFP Lead-Free Package

S

MAX3815A

Applications

Front-Projector HDMI/DVI Inputs

High-Definition Televisions and Displays

HDMI/DVI-D Cable-Extender Modules and Active
Cable Assemblies

LCD Computer Monitors

HDMI 1.3 Deep Color Systems

HDMI OR DVI EXTENDER BOX

UP TO 35m OF HDMI

OR

DVI CABLE

VIDEO SOURCE

Typical Operating Circuits continued at end of data sheet.

DVI is a trademark of Digital Display Working Group.
HDMI is a trademark of HDMI Licensing, LLC.
TMDS is a registered trademark of Silicon Image, Inc.

MAX3815A

EQUALIZER

MAX3816A

DDC EXTENDER

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX3815ACCM+

+Denotes a lead(Pb)-free/RoHS compliant package.
*EP = Exposed pad.

Pin Configuration appears at end of data sheet.

STANDARD LENGTH

DVI-D OR HDMI CABLE

0NC to +70NC

48 TQFP-EP*

HDTV

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

TMDS Digital Video Equalizer for
HDMI/DVI Cables

ABSOLUTE MAXIMUM RATINGS

Supply Voltage Range, VCC ................................-0.5V to +4.0V

Voltage Range at Output CML Pins .....................-0.5V to +4.0V

Voltage Range at Input CML Pins, RES, VCC_T,

and GND_T ............................................ -0.5V to (VCC + 0.7V)

Voltage Between Input CML Complementary Pair ........... ±3.3V

Voltage Between Output CML Complementary Pair ........ ±1.4V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

MAX3815A

ELECTRICAL CHARACTERISTICS

(VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in
automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power-Supply Current I

Supply-Noise Tolerance DC to 500kHz 200 mV

EQUALIZER PERFORMANCE

Residual Output Jitter (Cables
Only) 0.25Gbps to 1.65Gbps
(Notes 1, 2, and 3)

CC

Clock present (CLKLOS = HIGH)
Clock and data absent (CLKLOS = LOW)

1dB skin-effect loss at 825MHz 0.05

24dB skin-effect loss at 825MHz 0.13 0.21

Continuous Power Dissipation (TA = +70°C)

48-Pin TQFP (derate 36.2mW/°C above +70°C) ........2896mW

Operating Junction Temperature Range ......... -55°C to +150°C

Storage Temperature Range ............................ -55°C to +150°C

Die Attach Temperature ..................................................+400°C

210 270

12

mA

P-P

UI

Residual Output Jitter (Cables
Only) 1.65Gbps to 2.25Gbps
(Notes 1, 2, and 3)

CID Tolerance 20 Bits

CONTROL AND STATUS

CLKLOS Assert Level

CML INPUTS (CABLE SIDE)

Differential Input-Voltage Swing V

Common-Mode Input Voltage V

Input Resistance R

CML OUTPUTS (ASIC SIDE)

Differential Output-Voltage Swing V

Output-Voltage High Single-ended, OUTLEVEL = HIGH V

Output-Voltage Low Single-ended, OUTLEVEL = HIGH

Output Voltage During Clock
Absence (CLKLOS = LOW)

CM

OD

1dB skin-effect loss at 825MHz 0.1

24dB skin-effect loss at 825MHz 0.14 0.28

Differential peak-to-peak at EQ input
with max 225MHz clock (see the Typical
Operating Characteristics for more
information)

At cable input 800 1000 1200 mV

ID

V

CC

0.4

Single-ended 45 50 55

IN

50W load, each side
to V

CC

With back termination as shown in Figure 4,
OUTLEVEL = OPEN

Single-ended

OUTLEVEL = HIGH 800 1000 1200
OUTLEVEL = LOW 500

V

CC

600

V

CC

10

50 mV

-

910

CC

-

-

V

V

V

CC

0.1

CC

400

CC

10

UI

+

V

W

mV

mV

­mV

+

mV

P-P

P-P

P-P

2 ______________________________________________________________________________________

TMDS Digital Video Equalizer for

HDMI/DVI Cables

ELECTRICAL CHARACTERISTICS (continued)

(VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in
automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

-

Common-Mode Output Voltage

50W load, each side to VCC,
OUTLEVEL = HIGH

Rise/Fall Time (Note 1) 20% to 80% 80 160 ps

LVTTL CONTROL AND STATUS INTERFACE

LVTTL Input High Voltage V
LVTTL Input Low Voltage V
LVTTL Input High Current V

IH

IL

< VIN < V

IH(MIN)

LVTTL Input Low Current GND < VIN < V

Open-Collector Output High
Voltage

Open-Collector Output Low
Voltage

R

LOAD

R

LOAD

≥ 10kW to V

≥ 2kW to V

CC

IL(MAX)

CC

CC

2.0 V

2.4 V

Open-Collector Output Sink
Current

OUTLEVEL Input Open-State
Current Tolerance

CC

0.25

0.8 V

±50 µA

-100 µA

0.4 V

5 mA

±5 µA

V

MAX3815A

Note 1: AC specifications are guaranteed by design and characterization.
Note 2: Cable input swing is 800mV to 1200mV differential peak-to-peak. Residual output jitter is defined as peak-to-peak jitter,

both deterministic plus random, as measured using an oscilloscope histogram with 5000 hits. Source jitter subtracted.

Note 3: Test pattern is a 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros.

Typical Operating Characteristics

(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer
in automatic mode, cable launch amplitude 1V

SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

250

OUTLEVEL = OPEN, EQCONTROL = VCC,

240

CLOCK SIGNAL ACTIVE

230

220

210

200

TMDS SOURCE DC-COUPLED TO MAX3815A

190

180

SUPPLY CURRENT (mA)

170

160

150

INPUT (NOMINAL AMPLITUDE)

TMDS SOURCE AC-COUPLED TO MAX3815A

0 70

AMBIENT TEMPERATURE (°C)

differential, unless otherwise noted.)

P-P

0

MAX3815A toc02

605030 402010

-5

-10

-15

-20

GAIN (dB)

-25

-30

-35

-40

INPUT RETURN LOSS vs. FREQUENCY

0 3000

FREQUENCY (MHz)

25002000500 1000 1500

MAX3815A toc02

_______________________________________________________________________________________ 3

TMDS Digital Video Equalizer for
HDMI/DVI Cables

Typical Operating Characteristics (continued)

(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer
in automatic mode, cable launch amplitude 1V

EQUALIZER INPUT AFTER 100ft OF 26 AWG

CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)

DATA RATE = 2.25Gbps
30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz

differential, unless otherwise noted.)

P-P

MAX3815A toc03

EQUALIZER INPUT EYE AFTER 100ft OF 26 AWG

CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)

DATA RATE = 2.25Gbps
30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz

MAX3815A toc04

MAX3815A

20mV/div

500mV/div

EQUALIZER INPUT EYE AFTER 150ft OF 26 AWG

CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)

DATA RATE = 742.5Mbps
24dB CABLE SKIN-EFFECT LOSS AT 370MHz

350mV/div

SHR is a trademark of DVIGear, Inc.

5ns/div

300ps/div

MAX3815A toc05

TOTAL JITTER vs. POWER-SUPPLY NOISE

FREQUENCY (DATA RATE = 2.25Gbps)

180

NOISE AMPLITUDE: 200mV
DATA THROUGH 50m DVIGear SHR

170

HDMI CABLE, 22 AWG

160

)

P-P

150

140

130

TOTAL JITTER (ps

120

110

100

1 10,000

FREQUENCY (kHz)

P-P

350mV/div

100010010

100ps/div

TOTAL JITTER vs. DATA RATE

(50m HDMI CABLE)

200

DVIGear SHR™ HDMI CABLE (22 AWG)

180

160

)

140

P-P

120

100

80

TOTAL JITTER (ps

60

40

20

0

250 2250

MAX3815A toc07

PEAK-TO-PEAK JITTER

IN PICOSECONDS

PEAK-TO-PEAK JITTER

IN UNIT INTERVALS

17501250750

DATA RATE (Mbps)

MAX3815A toc06

0.5

0.4

0.3

0.2

0.1

0

)

P-P

TOTAL JITTER (UI

4 ______________________________________________________________________________________

TMDS Digital Video Equalizer for

HDMI/DVI Cables

Typical Operating Characteristics (continued)

(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer
in automatic mode, cable launch amplitude 1V

differential, unless otherwise noted.)

P-P

MAX3815A

TOTAL JITTER vs. CABLE LENGTH (CARLISLE

INTERCONNECT TECHNOLOGIES TWIN-AX 28 AWG)

0.6

0.5

)

P-P

0.4

0.3

0.2

NO EQ

DETERMINISTIC JITTER (UI

0.1

0

0 40

2.25Gbps

1.485Mbps

742.5Mbps

WITH MAX3815A EQ

302010

CABLE LENGTH (m)

EQCONTROL VOLTAGE (RELATIVE TO VCC)

vs. CABLE LENGTH (MANUAL EQ CONTROL)

0

CABLE IS CARLISLE INTERCONNECT
TECHNOLOGIES TWIN-AX 28 AWG WITH

-0.1

APPROXIMATELY 1.35dB OF LOSS

-0.2

PER METER AT 1.11GHz

-0.3

-0.4

-0.5

EQCONTROL VOLTAGE (V)

-0.6

-0.7

-0.8

EQCONTROL VOLTAGE

RESIDUAL JITTER

0 30

CABLE LENGTH (m)

MAX3815A toc10

AT 2.25Gbps

2010

MAX3815A toc08

200

180

160

)

P-P

140

120

100

80

60

RESIDUAL JITTER (ps

40

20

0

TOTAL JITTER vs. SIGNAL AMPLITUDE INPUT

TO CABLE (DATA RATE 2.25Gbps)

130

50m OF DVIGear SHR HDMI CABLE
WITH 35dB LOSS AT 1.11GHz

120

110

)

P-P

100

90

80

TOTAL JITTER (ps

70

60

50

0.4 1.6
DIFFERENTIAL AMPLITUDE (V

1.41.20.6 0.8 1.0

P-P

LOSS-OF-CLOCK ASSERT THRESHOLD

vs. CABLE LENGTH

350

)

CLOCK AMPLITUDE IS AT INPUT OF CABLE

P-P

CABLE IS CARLISLE INTERCONNECT

300

TECHNOLOGIES TWIN-AX, 28 AWG

250

200

150

100

50

DIFFERENTIAL CLOCK AMPLITUDE (mV

0

0 36

225MHz CLOCK

FREQUENCY

25MHz CLOCK

FREQUENCY

302418126

CABLE LENGTH (m)

MAX3815A toc09

)

MAX3815A toc11

EQUALIZER OUTPUT EYE AFTER 50m OF 22 AWG

HDMI CABLE (DATA RATE = 2.25Gbps)

DVIGear SHR HDMI CABLE

200mV/div

100ps/div

MAX3815A toc12

_______________________________________________________________________________________ 5

TMDS Digital Video Equalizer for
HDMI/DVI Cables

Pin Description

PIN NAME FUNCTION

1, 4, 5, 8, 9,

12, 13, 16, 38

2 RX0_IN- Negative Data Input, CML
3 RX0_IN+ Positive Data Input, CML
6 RX1_IN- Negative Data Input, CML

MAX3815A

7 RX1_IN+ Positive Data Input, CML
10 RX2_IN- Negative Data Input, CML
11 RX2_IN+ Positive Data Input, CML
14 RXC_IN+ Positive Clock Input, CML
15 RXC_IN- Negative Clock Input, CML

17 EQCONTROL

18

19 N.C. Not Connected. This pin is not internally connected.

20, 23, 24, 25,
28, 29, 32, 33,

36, 37

21 RXC_OUT- Negative Clock Output, CML
22 RXC_OUT+ Positive Clock Output, CML
26 RX2_OUT+ Positive Data Output, CML
27 RX2_OUT- Negative Data Output, CML
30 RX1_OUT+ Positive Data Output, CML
31 RX1_OUT- Negative Data Output, CML
34 RX0_OUT+ Positive Data Output, CML
35 RX0_OUT- Negative Data Output, CML

39 OUTLEVEL

40

41, 43, 44 VCC_T Reserved. Must be connected to VCC for normal operation.

42 GND_T Reserved. Must be connected to GND for normal operation.

45–48 RES Reserved. Must be left open for normal operation.

— EP

V

CC

CLKLOS

GND Ground

OUTON

Supply Voltage. All pins must be connected to VCC.

Equalizer Control. This pin allows the user to control the equalization level of the MAX3815A.
Connect the pin to GND for automatic operation. Set the voltage to VCC - 1V for minimum
equalization, or set the voltage between VCC - 1V and VCC for manual equalization. See the
Applications Information section for more information.

Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input
TMDS clock from the cable. Connect pin to VCC through a 4.7kω resistor.

Output-Level Control Input

• HIGH: Standard swing (1000mV

• OPEN: Standard swing (900mV

(see Figure 4)

• LOW: One-half standard swing (500mV

Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and
sets a differential logic zero when forced high.

Exposed Pad. The exposed pad must be soldered to the circuit-board ground for proper
thermal and electrical operation.

differential)

P-P

differential) with external 267ω back termination resistor

P-P

differential)

P-P

6 ______________________________________________________________________________________

RX0_IN+/-

RX1_IN+/-

RX2_IN+/-

RXC_IN+/-

TERMINATED

3.3V CML

TERMINATED

3.3V CML

TERMINATED

3.3V CML

TERMINATED

3.3V CML

TMDS Digital Video Equalizer for

HDMI/DVI Cables

INPUT

BUFFER

INPUT

BUFFER

INPUT

BUFFER

INPUT

BUFFER

ADAPTIVE

EQ

ADAPTIVE

EQ

ADAPTIVE

EQ

LIMITING

AMPLIFIER

LIMITING

AMPLIFIER

LIMITING

AMPLIFIER

LIMITING

AMPLIFIER

DRIVER

DRIVER

DRIVER

DRIVER

RX0_OUT+/-

RX1_OUT+/-

RX2_OUT+/-

EQCONTROL

RXC_OUT+/-

MAX3815A

CLKLOS

CLOCK LOS

DETECTOR

MAX3815A

Figure 1. Functional Diagram

Detailed Description

The MAX3815A TMDS equalizer accepts differential
CML input data at rates of 250Mbps up to 2.25Gbps
(individual channel data rate). It automatically adjusts
to skin-effect losses in copper cable. It consists of four
CML input buffers, a loss-of-clock signal detector, three
independent adaptive equalizers, four limiting amplifiers,
and four output buffers (Figure 1).

CML Input Buffers and Output Drivers

The input buffers and the output drivers are implemented
using current-mode logic (CML) (see Figures 4 and 5). The
output drivers are open-collector and can be turned off
with the OUTON pin. The OUTLEVEL pin sets the output
drive current to one of three levels; see the Applications
Information and Pin Description sections for more infor­mation. For details on interfacing with CML, refer to

Application Note 291: HFAN-01.0: Introduction to LVDS,
PECL, and CML.

OUTON

OUTLEVEL

Loss-of-Clock Signal Detector

The loss-of-clock signal detector indicates a loss-of­clock signal at the CLKLOS pin. This is an open-collector
output that must be connected to VCC through a 4.7kω
external pullup. This resistor is required whether or not
the LOS output is used.

Adaptive Equalizer

The three data channels each contain an independent
adaptive equalizer. Each channel analyzes the incom­ing signal and determines the amount of equalization to
apply.

Limiting Amplifier

The limiting amplifier amplifies the signal from the adap­tive equalizer and truncates the top and bottom of the
waveform to provide a clean high- and low-level signal
to the output drivers.

_______________________________________________________________________________________ 7

TMDS Digital Video Equalizer for
HDMI/DVI Cables

D0

D1

D2

CLK

MAX3815A

D3

D4

D5

Figure 2. Connection Scheme for MAX3815A in Dual Link
Application

CONTROL CIRCUITRY

MAX3815A

MAX3815A

TO CHIP POWER-

V

CC

MAX3815A

CLKLOS

V

CC

4.7k

D0

D1
D2

CLK

D3

D4

D5

Ω

Typical shielded twisted pair (STP), unshielded twisted
pair (UTP), and twin-ax cables exhibit skin-effect losses,
which attenuate the high-frequency spectrum of a TMDS
signal, eventually causing data errors or even closing
the signal eye altogether given a long enough cable. The
MAX3815A recovers the data and opens the signal eye
through compensating equalization.

The basic TMDS interface is composed of four differential

serial links: three links carry serial data up to 2.25Gbps

each, and the fourth is a one-tenth-rate (0.1x) clock that
operates up to 225MHz. TMDS, as with analog nVGA
links, must handle a variety of resolutions and screen
update rates. The actual range of digital serial rates is
roughly 250Mbps to 2.25Gbps. For applications requir­ing ultra-high resolutions (e.g., QXGA), a “dual-link” DVI
interface is used and is composed of six data links plus
the clock, requiring two MAX3815A ICs with the clock
going to both ICs. See Figure 2.

The MAX3815A can be used to extend any TMDS inter-

face as used under the following trademarked names:

DVI (digital visual interface), DFP™ (digital flat-panel),
PanelLink, ADC™ (Apple display connector), and HDMI
(high-definition multimedia interface).

Applications Information

Figure 3. Simplified CLKLOS Output Circuit Schematic

A loss-of-clock signal is indicated by the CLKLOS out­put. A low level on CLKLOS indicates that the signal
power on the RXC_IN pins has dropped below a thresh­old. When there is sufficient input voltage to the channel
(typically greater than 100mV
high. The CLKLOS output is suitable for indicating prob­lems with the transmission link caused by, for example,

MAX3815A

RX_OUT+

+3.3V

50Ω

50Ω

a broken cable, a defective driver, or a lost connection

267Ω

to the equalizer. Note that the loss-of-clock circuitry is
sensitive to a DC or AC voltage between the RXC_IN

RX_OUT-

12.5mA

Figure 4. Back Termination Circuit

DFP is a trademark of Video Electronics Standards Association (VESA).
ADC is a trademark of Apple Computer, Inc.

HDM/DVI

RECEIVER

pins. A DC or AC voltage greater than Q30mV (typical) is
sensed as an active clock signal.

Loss-of-Clock Signal (CLKLOS) Output

differential), CLKLOS is

P-P

8 ______________________________________________________________________________________

TMDS Digital Video Equalizer for

The loss-of-clock circuitry powers down the part when­ever there is an absence of a clock signal. This mutes
the output and reduces power consumption to 83mW
whenever the input signal is removed. During power­down, the MAX3815A’s TMDS output pins go to a high­impedance state.

The CLKLOS is an open-collector output that requires a
resistive pullup to V
range is 1kω to 10kω (see Figure 3).

Output Level Control (OUTLEVEL) Input

The OUTLEVEL pin is a three-state input that allows the
user to select between three output settings. Forcing this
pin high results in the standard output signal level with
no back terminations; leaving the pin open results in a
standard output swing with 267ω differential back termi­nation resistors. Forcing this pin low results in one-half
standard output signal level.

Using back termination resistance improves signal integ­rity through absorption of reflections. It also shifts the sin­gle-ended output voltage high (VH) and low (VL). Table 1
shows the output voltages when using the MAX3815A in
each of its three output configurations.

Equalizer Control (EQCONTROL) Input

The EQCONTROL pin allows the user to control the

equalization in one of two ways: forcing the pin to ground

sets the equalizer in automatic equalization mode,
and forcing a voltage between VCC - 1V to VCC allows
manual control of the equalization level. Set to VCC for
maximum boost (long cable). Set to VCC - 1V for mini­mum boost (short cable).

for operation. The pullup resistor

CC

Using Back Termination

HDMI/DVI Cables

Interface Models

MAX3815A

V

CC

Ω

50

RX_IN+/-

Figure 5. Simplified Input Circuit Schematic

MAX3815A

TRANSIENT

SUPRESSOR

CLAMP

0 1

PWRDWN

10mA OUTLEVEL = HIGH

12.5mA OUTLEVEL = OPEN
5mA OUTLEVEL = LOW

MAX3815A

RX_OUT+

RX_OUT-

Table 1. Output Settings and Swings

OUTLEVEL BACK TERMINATION

High Open 1000 V

Open

Low Open 500 V

_______________________________________________________________________________________ 9

267I

Figure 6. Simplified Output Circuit Schematic

DIFFERENTIAL
SWING (mV

P-P

910 VCC - 85mV VCC - 540mV

SINGLE-ENDED HIGH

)

SINGLE-ENDED LOW

(VH)

CC

CC

(VL)

VCC - 500mV

VCC - 250mV

TMDS Digital Video Equalizer for
HDMI/DVI Cables

• The data and clock inputs should be wired directly

between the cable connector and IC without stubs.

TYPICAL MAX3815A CABLE REACH

(DATA RATE = 2.25Gbps)

60

50

TYPICAL LIMIT OF CABLE

WITH EQ AT 2.25Gbps

40

MAX3815A

Figure 7. Cable Reach

30

CABLE LENGTH (m)

20

10

0

TYPICAL LIMIT OF CABLE
WITHOUT EQ AT 2.25Gbps

28 22

WIRE GAUGE (AWG)

2426

Output On (OUTON) Input

The OUTON pin is an LVTTL input. Force the pin low to
enable the outputs. Force the pin high to set a differen­tial zero on the outputs, irrespective of the signal at the
inputs.

Cable Selection

TMDS performance is heavily dependent on cable quality.
Deterministic jitter (DJ) can be caused by differential-to­common-mode conversion (or vice versa) within a twisted
pair (STP or UTP), usually a result of cable twist or dielectric

imbalance. Refer to Application Note 3353: HFAN-04.5.4:
‘Jitter Happens’ when a Twisted Pair is Unbalanced and
Application Note 4218: Unbalanced Twisted Pairs Can
Give You the Jitters! for more information.

Layout Considerations

The data and clock inputs are the most critical paths for
the MAX3815A and great care should be taken to mini­mize discontinuities on these transmission lines between
the connector and the IC. Here are some suggestions for

maximizing the performance of the MAX3815A:

• Place supply filter capacitors close to the MAX3815A

inputs to provide a low inductance path for supply
return currents.

• Input and output data channel designations are only

a guide. Polarity assignments can be swapped and
channel paths can be interchanged.

• An uninterrupted ground plane should be positioned

beneath the high-speed I/Os.

• Ground-path vias should be placed close to the input/

output connectors to allow a low inductance return
current path.

• Maintain 100Ω differential transmission line impedance

into and out of the MAX3815A.

• Use good high-frequency layout techniques and

multilayer boards with an uninterrupted ground plane
to minimize EMI and crosstalk. Refer to Application

Note 3854: MAX3815: Interfacing to the MAX3815
DVI/HDMI Cable Equalizer and the EV kit data sheet,

MAX3815AEVKIT-HDMI.

The exposed pad on the 48-pin TQFP-EP provides a very
low thermal resistance path for heat removal from the
IC. The pad is also electrical ground on the MAX3815A
and must be soldered to the circuit board ground
for proper thermal and electrical performance. Refer

to Maxim Application Note 862: HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages for additional information.

Chip Information

PROCESS: SiGe BiPOLAR

Package Information

For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

48 TQFP-EP C48E+8

Exposed-Pad Package

21-0065

10 _____________________________________________________________________________________

TMDS Digital Video Equalizer for

Typical Operating Circuits (continued)

HDMI/DVI Cables

VIDEO PROJECTOR

MAX3815A

RGB/HV

ADC/SYNC

TMDS

DESERIALIZER

SELECT

IMAGE
SCALER AND
PROCESSOR

PANEL

INTERFACE

TIMING AND

DRIVERS

LCD,
DLP,

OR

LCOS

LAPTOP

VGA INPUT

DVI-D INPUT

DVI-D CABLE UP
TO 35m OR 120ft

(24 AWG STP)

MAX3815A

EQUALIZER

Pin Configuration

TOP VIEW

GND_T

VCC_T

OUTON

OUTLEVEL

VCCGND

*EP

36

35

34

33

32

31

30

29

28

27

26

25

GND

RX0_OUT-

RX0_OUT+

GND

GND

RX1_OUT-

RX1_OUT+

GND

GND

RX2_OUT-

RX2_OUT+

GND

V

RX0_IN-

RX0_IN+

V

V

RX1_IN-

RX1_IN+

V

V

RX2_IN-

RX2_IN+

V

RES

RES

RES

RES

VCC_T

VCC_T

48 47 46 45 44 43 42 41 40 39 38 37

+

1

CC

2

3

4

CC

5

CC

6

7

8

CC

9

CC

10

11

12

CC

MAX3815A

13 14 15 16 17 18 19 20 21 22 23 24

CC

V

*EXPOSED PAD.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.

RXC_IN-

RXC_IN+

CC

V

CLKLOS

EQCONTROL

TQFP

N.C.

GND

RXC_OUT-

RXC_OUT+

GND

GND

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2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.