MAXIM MAX3804 User Manual

General Description

The MAX3804 driver with integrated analog equalizer
compensates up to 20dB of loss at 5GHz. It is designed
to ensure PC board signal integrity up to 12.5Gbps,
where frequency-dependent skin effect and dielectric
losses typically produce unacceptable amounts of inter­symbol interference. The MAX3804 can extend the practi­cal chip-to-chip transmission distance for 10Gbps NRZ
serial data up to 30in (0.75m) on FR-4, and it significantly
decreases deterministic jitter. Residual jitter after equal­ization for 10.7Gbps signals is typically 24ps

P-P

on the

maximum path length.

The MAX3804 is ideal for 10Gbps chip-to-chip serial
interconnections on inexpensive FR-4 material. Its
3mm ✕ 3mm package affords optimal placement and
routing flexibility. It has separate VCCconnections for
internal logic and current-mode logic (CML) I/O. This
allows the CML input and output to be referenced to iso­lated supplies, providing independent DC-coupled inter­facing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of
input equalization can be selected through a digital con­trol input, enabling the equalizer to be matched to a
range of transmission line path loss. When correctly set to
match the path loss, the MAX3804 provides optimal per­formance over a wide range of data rates and formats.

Applications

OC-192 and 10Gb Ethernet Switches and Routers

OC-192 and 10Gb Ethernet Serial Modules

High-Speed Signal Distribution

Features

♦ Compensates Up to 30in (0.75m) of 6-mil FR-4

Transmission Line Loss

♦ 115mW Operating Power

♦ Up to 12.5Gbps Data Rate

♦ Compatible with 8B10B, 64B66B, and PRBS Data

♦ Less than 30ps

P-P

Residual Jitter After

Equalization

♦ 3-Bit Equalization Level Select Input

♦ 3mm x 3mm Thin QFN Package

♦ DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O

♦ -40°C to +85°C Operation

♦ +3.3V Core Supply Voltage

MAX3804

12.5Gbps Settable Receive Equalizer

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

SDI-

SDI+

SDI-

SDI+

SDO-

SDO+

SDO-IN

SDO+

MAX3804

V

CC

V

CC2

V

CC1VCC

V

CC

10Gbps

SERDES

10Gbps

SERIAL OPTICAL

MODULE

30in OF FR-4 STRIPLINE OR

MICROSTRIP TRANSMISSION LINE

+3.3V

+3.3V

GNDEQ3EQ2EQ1

+2.5V

+1.8V

Typical Operating Circuit

19-2713; Rev 1; 11/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

PART TEMP RANGE

MAX3804ETE -40°C to +85°C

PIN-

PACKAGE

16 Thin QFN

(3mm x 3mm)

PACKAGE
CODE

T1633F-3

MAX3804

12.5Gbps Settable Receive Equalizer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, V

CC1

= V

CC2

= +1.65V to +3.6V, TA= -40°C to +85°C. Typical values are at V

CC

= V

CC1

= V

CC2

= +3.3V,

and T

A

= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage (VCC) ............................................-0.5V to +4.0V

CML Supply Voltage (V

CC1

, V

CC2

) ............-0.5V to (VCC+ 0.5V)

Current at Serial Output (SDO+, SDO-) ............................±25mA

Input Voltage (SDI+, SDI-, EQ1,

EQ2, EQ3) ..............................................-0.5V to (V

CC

+ 0.5V)

Continuous Power Dissipation (T

A

= +85°C)

16-Lead Thin QFN-EP (derate 17.5mW/°C

above +85°C) ........................................................1398mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Note 1: Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z0= 100Ω, 6-mil

microstrip in FR-4, ε

r

= 4.5, and tan δ = 0.02, VIN= (SDI+ - SDI-).

Note 2: Measured with 0000011111 pattern at 12.5Gbps.
Note 3: Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmis-

sion line) and equalizer output. Total residual jitter is DJ

P-P

+ 14.2 x RJ

RMS

.

Note 4: Measured at 10.7Gbps using a pattern of 100 ones, 2

7

PRBS, 100 zeros, 27PRBS, and at 12.5Gbps using a K28.5 pattern.

Deterministic jitter at the input is from frequency-dependent, media-induced loss only.

Note 5: V

IN

= 400mV

P-P

to 1200mV

P-P

, input path is 0 to 30in, 6-mil microstrip in FR-4, εr= 4.5, and tan δ = 0.02.

Note 6: Guaranteed by design and characterization.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Current I

CML Input Differential V

CML Input Common Mode DC-coupled

CML Input Termination Single ended 42.5 50 57.5 Ω

CML Input Return Loss Up to 5GHz 10 dB

CML Output Differential V

CML Output Impedance Single ended 42.5 50 57.5 Ω

CML Output Transition Time tR, t

Residual Jitter Output
(Total RJ, PWD, and PDJ)

LVTTL Input Current IIH, I

LVTTL Input Low V

LVTTL Input High V

CC

AC-coupled or DC-coupled (Note 1) 400 1200 mV

IN

OUT

20% to 80% (Notes 2, 6) 35 ps

F

At 10.7Gbps (Notes 3, 4, 5, 6) 24 30

At 12.5Gbps (Notes 3, 4, 5, 6) 17 30

IL

IL

IH

35 50 mA

V

CC1

- 0.4

V

CC1

+ 0.1

400 500 600 mV

-30 +30 µA

0.8 V

2.0 V

P-P

V

P-P

ps

P-P

MAX3804

12.5Gbps Settable Receive Equalizer

_______________________________________________________________________________________ 3

4

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. TEMPERATURE

85

70

55

40

SUPPLY CURRENT (mA)

25

10

-40 85

VCC = V

CC1

TEMPERATURE (°C)

= V

CC2

603510-15

RESIDUAL JITTER

vs. EQUALIZATION SETTING

35

31

)

P-P

27

23

RESIDUAL JITTER (ps

19

15

000 111

18in

6in

12in

3in

EQUALIZATION SETTING (EQ3, EQ2, EQ1)

24in

RESIDUAL JITTER

+ 14.2RJ

DJ

P-P

30in

400mV

, FR-4,

P-P

7

PRBS WITH 100

2
CIDs AT 10.7Gbps

110101100011010001

= 3.3V

RMS

MAX3804 toc01

)

P-P

RESIDUAL JITTER (ps

MAX3804 toc04

60mV/

RESIDUAL JITTER

35

30

25

20

15

10

5

0

400 1200

EQUALIZER OUTPUT EYE AFTER 18in OF FR-4

div

vs. INPUT AMPLITUDE

30in OF FR-4
TRANSMISSION LINE

7

2

PRBS WITH 100

CIDs AT 9.953Gbps

K28.5 AT 12.5Gbps

RESIDUAL JITTER

+ 14.2RJ

= DJ

P-P

1000800600

INPUT AMPLITUDE (mV

7

PRBS WITH 100 CIDs AT 10.7Gbps)

(2

16ps/div

)

P-P

RMS

MAX3804 toc02

)

P-P

RESIDUAL JITTER (ps

MAX3804 toc05

60mV/

RESIDUAL JITTER

35

30

25

20

15

10

5

0

EQUALIZER OUTPUT EYE AFTER 18in OF FR-

div

vs. FR-4 PATH LENGTH

400mV

P-P

27PRBS WITH 100

CIDs AT 9.953Gbps

K28.5 AT 12.5Gbps

327

FR-4 PATH LENGTH (in)

INPUT AMPLITUDE

RESIDUAL JITTER

+ 14.2RJ

= DJ

P-P

21159

MAX3804 toc03

RMS

(K28.5 AT 12.5Gbps)

MAX3804 toc06

16ps/div

MAX3804

12.5Gbps Settable Receive Equalizer

4 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

EQUALIZER OUTPUT EYE AFTER 30in OF FR-4

(K28.5 AT 12.5Gbps)

MAX3804 toc09

16ps/div

60mV/

div

EQUALIZER OUTPUT EYE AFTER 24ft

OF RG-188/U COAXIAL CABLE, SINGLE ENDED

(2

7

PRBS WITH 100 CIDs, 9.953Gbps)

MAX3804 toc10

20ps/div

60mV/

div

EQUALIZER OUTPUT EYE AFTER 30in OF FR-4

(2

7

PRBS WITH 100 CIDs AT 3.2Gbps)

MAX3804 toc11

60ps/div

60mV/

div

EQUALIZER INPUT EYE AFTER 30in OF FR-4

(2

7

PRBS WITH 100 CIDs AT 10.7Gbps)

MAX3804 toc07

16ps/div

60mV/

div

EQUALIZER OUTPUT EYE AFTER 30in OF FR-4

(2

7

PRBS WITH 100 CIDs AT 10.7Gbps)

MAX3804 toc08

16ps/div

60mV/

div

MAX3804

12.5Gbps Settable Receive Equalizer

_______________________________________________________________________________________ 5

Pin Description

Detailed Description

General Theory of Operation

The MAX3804’s low-noise linear input stage includes
two amplifiers, one with flat-frequency response, and
one with response that compensates for the loss
characteristic of an FR-4 PC board transmission line.
A current-steering network allows the designer to
control the amount of equalization to match the path
loss for specific applications. This network consists of a
pair of variable attenuators feeding into a summing
node. Equalization is set by a 3-bit LVTTL-compatible
input (EQ3, EQ2, and EQ1). By employing fixed control
of the equalization level, the MAX3804 provides optimal
performance for a specific path loss. A high-speed
limiting amplifier follows the equalizer circuitry to shape
the output signal (see Figure 1).

CML Input and Output Buffers

The MAX3804 input and output CML buffers are termi­nated with 50Ω to V

CC1

and V

CC2

, respectively. The
equivalent circuit for the output is shown in Figure 2.
Separate supply voltage connections are provided for
the core (VCC), input (V

CC1

), and output (V

CC2

) circuit­ry to control noise coupling, and to allow DC-coupling
to +1.8V, +2.5V, or +3.3V CML ICs. The CML inputs
and outputs can also be AC-coupled.

Use AC-coupling for single-ended cable applications.
The unused CML input must be connected through an
AC-coupling capacitor to a 50Ω termination.

The low-frequency cutoff of the input-stage offset-can­cellation circuit is nominally 21kHz.

PIN NAME FUNCTION

1, 4 V

2 SDI+ Positive Serial Data Input, CML

3 SDI- Negative Serial Data Input, CML

5 EQ1 Equalizer Boost Control Logic Input LSB, LVTTL. See Table 1.

6 EQ2 Equalizer Boost Control Logic Input, LVTTL. See Table 1.

7 EQ3 Equalizer Boost Control Logic Input MSB, LVTTL. See Table 1.

8, 16 GND Supply Ground

9, 12 V

10 SDO- Negative Serial Data Output, CML

11 SDO+ Positive Serial Data Output, CML

13, 14 N.C. No Connection. Leave unconnected.

15 V

EP Exposed Pad

CC1

CC2

CC

CML Input Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Input can also be
AC-coupled.

CML Output Supply Voltage. Connect to +1.8V to +3.3V for DC-coupled CML. Output can also be
AC-coupled.

+3.3V Core Supply Voltage

Ground. Must be soldered to the circuit board ground for proper thermal and electrical performance
(see the Package and Layout Considerations section).

Applications Information

Equalizer Boost Level Control

The MAX3804 equalizer is intended for use at the
receive end of an FR-4 PC board transmission line,
typically up to 30in of differential 6-mil stripline or
microstrip. It is specifically designed to mitigate
intersymbol interference caused by the frequency­dependent path loss of FR-4 transmission lines. It can
also be used with a variety of other transmission-line
materials and geometries, including coaxial cable,
or PC board paths that include well-engineered
connectors. Table 1 shows the relationship between
nominal 6-mil FR-4 transmission line length and
equalization setting.

Supply Voltage Connections

The CML input and output supplies (V

CC1

, V

CC2

) can

be connected to +1.8V to +3.3V. V

CC1

and V

CC2

need
not be connected to the same supply voltage; however,
the core supply (VCC) must be connected to +3.3V.

Package and Layout Considerations

The MAX3804 is packaged in a 3mm x 3mm plastic­encapsulated 16-lead thin QFN package. The package
has an exposed pad that provides thermal and
electrical connectivity to the IC and must be soldered
to a high-frequency ground. Use good layout tech­niques for the SDI± and SDO± PC board transmission
lines, and configure the trace geometry near the IC

package to minimize impedance discontinuities.
Power-supply decoupling capacitors should be as
close as possible to the IC.

MAX3804

12.5Gbps Settable Receive Equalizer

6 _______________________________________________________________________________________

Figure 1. Functional Diagram

Figure 2. Simplified Output Structure

V

CC1

FLAT­RESPONSE
AMPLIFIER

50Ω50Ω

SDI+

SDI-

EQ1
EQ2
EQ3

CML

BOOST­RESPONSE
AMPLIFIER

DIGITAL-

TO-ANALOG

CONVERTER

VARIABLE

ATTENUATOR

VARIABLE

ATTENUATOR

V

CC2

50Ω50Ω

∑

MAX3804

LIMITING
AMP

50Ω

MAX3804

V

CC2

50Ω

ESD

DIODES

CML

V

CC

SDO+

SDO-

SDO+

SDO-

MAX3804

12.5Gbps Settable Receive Equalizer

_______________________________________________________________________________________ 7

Table 1. Nominal 6-mil FR-4 Transmission
Line Length and Equalization Settings

Pin Configuration

Chip Information

TRANSISTOR COUNT: 1007

PROCESS: SiGe bipolar

EQ3 EQ2 EQ1

000 2

001 6

010 10

011 14

100 18

101 22

110 26

111 30

NOMINAL 6-mil FR-4

MICROSTRIP LENGTH (in)

GND

161514

1

V

CC1

2

SDI+

MAX3804

3

SDI-

4

V

CC1

5

EQ1

Thin QFN*

(3mm x 3mm)

*THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT
BOARD GROUND FOR PROPER THERMAL AND
ELECTRICAL PERFORMANCE.

VCCN.C.

N.C.

13

12

V

CC2

11

SDO+

SDO-

10

V

9

CC2

6

7

8

EQ2

EQ3

GND

MAX3804

12.5Gbps Settable Receive Equalizer

8 _______________________________________________________________________________________

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

D2

b

D

D/2

D2/2

0.10 M C A B

E/2

- A -

C

L

- B -

C

L

0.10

C

0.08

C

A

A2

A1

E

(NE - 1) X e

e

C

L

L

e

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm

E2/2

k

(ND - 1) X e

C

L

e

21-0136

E2

L

L

REV.DOCUMENT CONTROL NO.APPROVAL

C

12x16L QFN THIN.EPS

1

2

MAX3804

12.5Gbps Settable Receive Equalizer

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.

EXPOSED PAD VARIATIONS

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE
12 & 16L, QFN THIN, 3x3x0.8 mm

APPROVAL

DOCUMENT CONTROL NO.

21-0136

REV.

2

C

2