MAXIM MAX3804 User Manual

General Description

The MAX3804 driver with integrated analog equalizer
compensates up to 20dB of loss at 5GHz. It is designed
to ensure PC board signal integrity up to 12.5Gbps,
where frequency-dependent skin effect and dielectric
losses typically produce unacceptable amounts of inter­symbol interference. The MAX3804 can extend the practi­cal chip-to-chip transmission distance for 10Gbps NRZ
serial data up to 30in (0.75m) on FR-4, and it significantly
decreases deterministic jitter. Residual jitter after equal­ization for 10.7Gbps signals is typically 24ps

P-P

on the

maximum path length.

The MAX3804 is ideal for 10Gbps chip-to-chip serial
interconnections on inexpensive FR-4 material. Its
3mm ✕ 3mm package affords optimal placement and
routing flexibility. It has separate VCCconnections for
internal logic and current-mode logic (CML) I/O. This
allows the CML input and output to be referenced to iso­lated supplies, providing independent DC-coupled inter­facing to 1.8V, 2.5V, or 3.3V ICs. Eight discrete levels of
input equalization can be selected through a digital con­trol input, enabling the equalizer to be matched to a
range of transmission line path loss. When correctly set to
match the path loss, the MAX3804 provides optimal per­formance over a wide range of data rates and formats.

Applications

OC-192 and 10Gb Ethernet Switches and Routers

OC-192 and 10Gb Ethernet Serial Modules

High-Speed Signal Distribution

Features

♦ Compensates Up to 30in (0.75m) of 6-mil FR-4

Transmission Line Loss

♦ 115mW Operating Power

♦ Up to 12.5Gbps Data Rate

♦ Compatible with 8B10B, 64B66B, and PRBS Data

♦ Less than 30ps

P-P

Residual Jitter After

Equalization

♦ 3-Bit Equalization Level Select Input

♦ 3mm x 3mm Thin QFN Package

♦ DC-Coupling to 1.8V, 2.5V, or 3.3V CML I/O

♦ -40°C to +85°C Operation

♦ +3.3V Core Supply Voltage

MAX3804

12.5Gbps Settable Receive Equalizer

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

SDI-

SDI+

SDI-

SDI+

SDO-

SDO+

SDO-IN

SDO+

MAX3804

V

CC

V

CC2

V

CC1VCC

V

CC

10Gbps

SERDES

10Gbps

SERIAL OPTICAL

MODULE

30in OF FR-4 STRIPLINE OR

MICROSTRIP TRANSMISSION LINE

+3.3V

+3.3V

GNDEQ3EQ2EQ1

+2.5V

+1.8V

Typical Operating Circuit

19-2713; Rev 1; 11/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

PART TEMP RANGE

MAX3804ETE -40°C to +85°C

PIN-

PACKAGE

16 Thin QFN

(3mm x 3mm)

PACKAGE
CODE

T1633F-3

MAX3804

12.5Gbps Settable Receive Equalizer

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, V

CC1

= V

CC2

= +1.65V to +3.6V, TA= -40°C to +85°C. Typical values are at V

CC

= V

CC1

= V

CC2

= +3.3V,

and T

A

= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage (VCC) ............................................-0.5V to +4.0V

CML Supply Voltage (V

CC1

, V

CC2

) ............-0.5V to (VCC+ 0.5V)

Current at Serial Output (SDO+, SDO-) ............................±25mA

Input Voltage (SDI+, SDI-, EQ1,

EQ2, EQ3) ..............................................-0.5V to (V

CC

+ 0.5V)

Continuous Power Dissipation (T

A

= +85°C)

16-Lead Thin QFN-EP (derate 17.5mW/°C

above +85°C) ........................................................1398mW

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Note 1: Differential Input Sensitivity is defined at the input to a transmission line. The transmission line is differential Z0= 100Ω, 6-mil

microstrip in FR-4, ε

r

= 4.5, and tan δ = 0.02, VIN= (SDI+ - SDI-).

Note 2: Measured with 0000011111 pattern at 12.5Gbps.
Note 3: Residual jitter is the difference in total jitter (RJ, PWD, and PDJ) between the transmitted signal (at the input to the transmis-

sion line) and equalizer output. Total residual jitter is DJ

P-P

+ 14.2 x RJ

RMS

.

Note 4: Measured at 10.7Gbps using a pattern of 100 ones, 2

7

PRBS, 100 zeros, 27PRBS, and at 12.5Gbps using a K28.5 pattern.

Deterministic jitter at the input is from frequency-dependent, media-induced loss only.

Note 5: V

IN

= 400mV

P-P

to 1200mV

P-P

, input path is 0 to 30in, 6-mil microstrip in FR-4, εr= 4.5, and tan δ = 0.02.

Note 6: Guaranteed by design and characterization.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Current I

CML Input Differential V

CML Input Common Mode DC-coupled

CML Input Termination Single ended 42.5 50 57.5 Ω

CML Input Return Loss Up to 5GHz 10 dB

CML Output Differential V

CML Output Impedance Single ended 42.5 50 57.5 Ω

CML Output Transition Time tR, t

Residual Jitter Output
(Total RJ, PWD, and PDJ)

LVTTL Input Current IIH, I

LVTTL Input Low V

LVTTL Input High V

CC

AC-coupled or DC-coupled (Note 1) 400 1200 mV

IN

OUT

20% to 80% (Notes 2, 6) 35 ps

F

At 10.7Gbps (Notes 3, 4, 5, 6) 24 30

At 12.5Gbps (Notes 3, 4, 5, 6) 17 30

IL

IL

IH

35 50 mA

V

CC1

- 0.4

V

CC1

+ 0.1

400 500 600 mV

-30 +30 µA

0.8 V

2.0 V

P-P

V

P-P

ps

P-P

MAX3804

12.5Gbps Settable Receive Equalizer

_______________________________________________________________________________________ 3

4

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. TEMPERATURE

85

70

55

40

SUPPLY CURRENT (mA)

25

10

-40 85

VCC = V

CC1

TEMPERATURE (°C)

= V

CC2

603510-15

RESIDUAL JITTER

vs. EQUALIZATION SETTING

35

31

)

P-P

27

23

RESIDUAL JITTER (ps

19

15

000 111

18in

6in

12in

3in

EQUALIZATION SETTING (EQ3, EQ2, EQ1)

24in

RESIDUAL JITTER

+ 14.2RJ

DJ

P-P

30in

400mV

, FR-4,

P-P

7

PRBS WITH 100

2
CIDs AT 10.7Gbps

110101100011010001

= 3.3V

RMS

MAX3804 toc01

)

P-P

RESIDUAL JITTER (ps

MAX3804 toc04

60mV/

RESIDUAL JITTER

35

30

25

20

15

10

5

0

400 1200

EQUALIZER OUTPUT EYE AFTER 18in OF FR-4

div

vs. INPUT AMPLITUDE

30in OF FR-4
TRANSMISSION LINE

7

2

PRBS WITH 100

CIDs AT 9.953Gbps

K28.5 AT 12.5Gbps

RESIDUAL JITTER

+ 14.2RJ

= DJ

P-P

1000800600

INPUT AMPLITUDE (mV

7

PRBS WITH 100 CIDs AT 10.7Gbps)

(2

16ps/div

)

P-P

RMS

MAX3804 toc02

)

P-P

RESIDUAL JITTER (ps

MAX3804 toc05

60mV/

RESIDUAL JITTER

35

30

25

20

15

10

5

0

EQUALIZER OUTPUT EYE AFTER 18in OF FR-

div

vs. FR-4 PATH LENGTH

400mV

P-P

27PRBS WITH 100

CIDs AT 9.953Gbps

K28.5 AT 12.5Gbps

327

FR-4 PATH LENGTH (in)

INPUT AMPLITUDE

RESIDUAL JITTER

+ 14.2RJ

= DJ

P-P

21159

MAX3804 toc03

RMS

(K28.5 AT 12.5Gbps)

MAX3804 toc06

16ps/div