Maxim MAX3693ECJ Datasheet

General Description
The MAX3693 serializer is ideal for converting 4-bit­wide, 155Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and deliv­ers a 3.3V PECL serial-data output. A fully integrated PLL synthesizes an internal 622Mbps serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref­erence clock.
Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
Features
Single +3.3V Supply155Mbps (4-bit-wide) Parallel to
622Mbps Serial Conversion
Clock Synthesis for 622Mbps215mW Power Multiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
LVDS Parallel Clock and Data InputsDifferential 3.3V PECL Serial-Data Output
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
________________________________________________________________
Maxim Integrated Products
1
Typical Operating Circuit
19-4775; Rev 1; 4/99
PART
MAX3693ECJ -40°C to +85°C
TEMP. RANGE PIN-PACKAGE
32 TQFP
Ordering Information
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLE
(155MHz LVDS CRYSTAL REFERENCE)
OVERHEAD
GENERATION
= +3.3V
V
CC
PCLKI- PCLKI+ RCLK- V
PD0+
PD0-
PD1+ PD1-
PD2+ PD2­PD3+
PD3-
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z
RCLK+
MAX3693
= 50)
0
CKSET
CC
FIL+
FIL-
SD-GNDPCLKO- PCLKO+
SD+
V
= +3.3V
CC
130 130
1µF
1µF
82
= +3.3V
V
CC
MAX3668
82
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3V to +3.6V, differential LVDS loads = 100±1%, PECL loads = 50±1% to (V
CC
- 2V), TA= -40°C to +85°C, unless other-
wise noted. Typical values are at V
CC
= +3.3V, TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltage (with respect to GND)
V
CC
.......................................................................-0.5V to +5V
All Inputs, FIL+, FIL-,
PCLKO+, PCLKO- ..............................-0.5V to (V
CC
+ 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (T
A
= +85°C)
TQFP (derate 10.20mW/°C above +85°C)...................663mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
T
A
= 0°C to +85°C
PECL outputs unterminated
TA= 0°C to +85°C
Differential input voltage = 100mV
Common-mode voltage = 50mV
CONDITIONS
V
VCC- 1.025 VCC- 0.88
V
OH
Output High Voltage
mA38 65 100I
CC
Supply Current
V0.925V
OL
Output Low Voltage
V1.475V
OH
Output High Voltage
85 100 115R
IN
Differential Input Resistance
mV60V
HYST
Threshold Hysteresis
V
VCC- 1.81 VCC- 1.62
V
OL
Output Low Voltage
V0 2.4V
I
Input Voltage Range
mV-100 100V
IDTH
Differential Input Threshold
UNITSMIN TYP MAXSYMBOLPARAMETER
%±2.5 ±10
R
O
Change in Magnitude of Single-Ended Output Resistance for Complementary Outputs
40 95 140R
O
Single-Ended Output Resistance
mV±25
V
OS
Change in Magnitude of Output Offset Voltage for Complementary States
mV250 400
|VOD|
Differential Output Voltage
mV±25
∆|VOD|
Change in Magnitude of Differential Output Voltage for Complementary States
V1.125 1.275V
OS
Output Offset Voltage
TA= -40°C V
CC
- 1.085 VCC- 0.88
TA= -40°C VCC-1.83 VCC- 1.555
CKSET = 0 or V
CC
µA±500I
CKSET
CKSET Input Current
PECL OUTPUTS (SD±)
LVDS INPUTS AND OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±)
PROGRAMMING INPUT (CKSET)
MAX3693
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________________________________________________________________________________ 3
Note 1: AC characteristics guaranteed by design and characterization.
TA= +25°C
CONDITIONS
ps600t
H
Parallel Data-Hold Time
ps200t
SU
MHz622.08f
SCLK
Serial Clock Rate
Parallel Data-Setup Time
ns0 +4.0t
SKEW
PCLKO to PCLKI Skew
ps
RMS
11
Φ
0
Output Random Jitter
ps200t
R, tF
PECL Differential Output Rise/Fall Time
UNITSMIN TYP MAXSYMBOLPARAMETER
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3V to +3.6V, differential LVDS load = 100±1%, PECL loads = 50±1% to (V
CC
- 2V), TA= -40°C to +85°C, unless other-
wise noted. Typical values are at V
CC
= +3.3V, TA= +25°C.) (Note 1)
100
0
-50 -25 25 100
SUPPLY CURRENT
vs. TEMPERATURE
20
60
80
MAX3693-01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
050
40
75
PECL OUTPUTS UNTERMINATED
200
-50
-50 -25 25 100
PARALLEL DATA-SETUP TIME
vs. TEMPERATURE
0
100
150
MAX3693-02
TEMPERATURE (°C)
PARALLEL DATA-SETUP TIME (ps)
050
50
75
250
0
-50 -25 25 100
PARALLEL DATA-HOLD TIME
vs. TEMPERATURE
50
150
200
MAX3693-03
TEMPERATURE (°C)
PARALLEL DATA-HOLD TIME (ps)
050
100
75
Typical Operating Characteristics
(V
CC
= +3.3V, differential LVDS loads = 100±1%, PECL loads = 50±1% to (V
CC
- 2V), TA= +25°C, unless otherwise noted.)
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