Datasheet MAX3675EHJ, MAX3675ECJ, MAX3675E-D Datasheet (Maxim)

___________________________________________________ Typical Operating Circuit

_____________________ General Description

The MAX3675 is a complete clock-recovery and data­retiming IC incorporating a limiting amplifier. It is
intended for 622Mbps SDH/SONET applications and
operates from a single +3.3V supply.

The MAX3675 has two differential input amplifiers: one
accepts PECL levels, while the other accepts small-sig­nal analog levels. The analog inputs access the limiting
amplifier stage, which provides both a received-signal­strength indicator (RSSI) and a programmable-threshold
loss-of-power (LOP) monitor. Selecting the PECL amplifier
disables the limiting amplifier, conserving power. A loss­of-lock (LOL) monitor is also incorporated as part of the
fully integrated PLL.

________________________Applications

SDH/SONET Transmission Systems
SDH/SONET Access Nodes
Add/Drop Multiplexers
ATM Switches
Digital Cross-Connects

____________________________Features

♦ Single +3.3V or +5.0V Power Supply
♦ Complies with ANSI, ITU, and Bellcore

SDH/SONET Specifications

♦ Low Power: 215mW at +3.3V
♦ Selectable Data Inputs, Differential PECL or

Analog

♦ Received-Signal-Strength Indicator (RSSI)
♦ Loss-of-Power and Loss-of-Lock Monitors
♦ Differential PECL Clock and Data Outputs
♦ No External Reference Clock Required

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

________________________________________________________________

Maxim Integrated Products

1

V

CC

ZO = 50Ω

100Ω

100k

INREF

FILT

OUT+

C

IN

0.01µF

C

IN

0.01µF

C

OLC

33nF

C

F

47nF

+3.3V

220pF

100pF

PHOTO-

DIODE

ADI+

DDI-

DDI+

SDO+

SDO-

0.1µF

C

LOL

0.01µF

0.01µF

ADI-

CFILT OLC+ OLC-

R1

R2

GND

RSSI INV VTH LOP

LOL

INSEL

PHADJ+ PHADJ- FIL+

52.3Ω
1%

2.2µF

FIL-

OUT-

GND

COMP

IN

ZO = 50Ω

+3.3V

V

CC

SCLKO+

SCLKO-

ZO = 50Ω

ZO = 50Ω

+3.3V

+3.3V

82Ω

82Ω

130Ω 130Ω

ZO = 50Ω

ZO = 50Ω

+3.3V

82Ω

82Ω

130Ω 130Ω

MAX3675

MAX3664

19-1258; Rev 2; 11/98

PART

MAX3675ECJ -40°C to +85°C

TEMP. RANGE PIN-PACKAGE

32 TQFP

_________________Ordering Information

Pin Configuration appears at end of data sheet.

*Contact factory for availability. Dice are designed to operate

from -40°C to +85°C, but are tested and guaranteed only at
Tj= +45°C.

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone].
For small orders, phone [phone].

EVALUATION KIT MANUAL

AVAILABLE

MAX3675EHJ -40°C to +85°C 5mm 32 TQFP
MAX3675E/D -40°C to +85°C Dice*

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Notes 1, 2)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage, VCC..............................................-0.5V to +6.5V

Input Voltage Levels,

DDI+, DDI-, ADI+, ADI-...........................-0.5V to (V

CC

+ 0.5V)

Input Differential Voltage (ADI+) - (ADI-)...............................±3V

PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO-...100mA

LOL, LOP, INSEL, PHADJ+, PHADJ-.........-0.5V to (VCC+ 0.5V)

FIL+, FIL-, OLC+, OLC-, RSSI, VTH...........-0.5V to (V

CC

+ 0.5V)

(OLC+) - (OLC-).....................................................................±3V

(FIL+) - (FIL-) ..................................................................±700mV

CFILT...............................................(V

CC

- 2.5V) to (VCC+ 0.5V)

INV.........................................................................-0.5V to +2.0V

Continuous Power Dissipation (T

A

= +85°C)

TQFP (derate 11.1mW/°C above +85°C).....................721mW

Operating Junction Temperature Range...........-40°C to +150°C

Storage Temperature Range.............................-65°C to +160°C

Processing Temperature (die).........................................+400°C

Lead Temperature (soldering, 10sec).............................+300°C

1MΩ between INV and VTH

MAX3675ECJ,
PECL outputs
unterminated

1MΩ between INV and VTH

C

LOL

= 0.01µF

(ADI+) - (ADI-) = 20mVp-p

ADI+, ADI- open

CONDITIONS

V1.10 1.18 1.30INV Input Bias Voltage

nA-100 +100Op-Amp Input Bias Current

VRSSI Output Voltage 2.00 2.12 2.30

1.22

VVCC- 0.7 VCC- 0.6 VCC- 0.5ADI+, ADI- Input Bias Voltage

VVCC- 1.16 VCC- 0.88V

IH

PECL Input High Voltage

47 65

65 90

V0.44V

OL

LOL Low Voltage

V0.1 0.4V

OL

LOP Low Voltage

V2.4V

OH

LOP, LOL High Voltage

VVCC- 1.81 VCC- 1.620V

OL

PECL Output Low Voltage

VVCC- 1.81 VCC- 1.48V

IL

PECL Input Low Voltage

µA-10 10I

IH

PECL Input High Current

µA-10 10I

IL

PECL Input Low Current

VVCC- 1.03 VCC- 0.88V

OH

PECL Output High Voltage

UNITSMIN TYP MAXSYMBOLPARAMETER

INSEL = V

CC

INSEL = GND

Note 1: Dice are tested at Tj= +45°C, VCC= +4.25V
Note 2: At T

A

= -40°C, DC characteristics are guaranteed by design and characterization.

mAI

CC

Supply Current

(ADI+) - (ADI-) = 80mVp-p 2.38 2.51 2.70

CF= 0.022µF

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V and TA= +25°C.)
(Notes 3, 4)

Note 3: AC parameters are guaranteed by design and characterization.
Note 4: The MAX3675 is characterized with a PRBS of 2

23

- 1 maintaining a BER of ≤ 10

-10

having a confidence level of 99.9%.

Note 5: A lower minimum input voltage of 2mVp-p is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVp-p.
Note 6: Hysteresis = 20log(V

RELEASE

/ V

ASSERT

)

Note 7: Small-signal bandwidth cannot be measured directly.
Note 8: RSSI slope = [V

RSSI2

- V

RSSI1

] / [20log (V

ID2

/ V

ID1

)]

Note 9: 1UI = 1 unit interval = (622.08MHz)

-1

= 1.608ns

PARAMETER SYMBOL MIN TYP MAX UNITS

RSSI Output Voltage

1.36

Limiting Amplifier Small-Signal Bandwidth BW 800 MHz

Power-Detect Hysteresis 23 5 dB

Input Referred Noise V

N

100 µV

Threshold Voltage V

TH

1.40 V

13

mUI

Differential Input Voltage Range V

ID

0.003 1.2000 Vp-p

Jitter Generation (Note 9)

6

CONDITIONS

(ADI+) - (ADI-) = 2mVp-p

(Note 7)

V

RELEASE

= 3.6mVp-p (Note 6)

ADI inputs

V

RELEASE

= 3.6mVp-p

CF= 2.2µF, RF= 52.3Ω

BER < 10

-10

, ADI inputs (Note 5)

1.93

V

(ADI+) - (ADI-) = 20mVp-p

Jitter-Transfer Peaking 0.08 dB

Maximum Consecutive Input
Run Length (1 or 0)

1000 Bits

Serial Clock-to-Q Delay t

CLK-Q

195 275 370 ps

Serial Clock Frequency f

SCLK

622.08 MHz

RF= 52.3Ω, CF= 2.2µF

8

RF= 52.3Ω,
CF= 2.2µF

1.50 3.35

Jitter Tolerance (Note 9)

0.25 0.60

0.20 0.50

3.5 MHz

CF= 2.2µF, RF= 52.3Ω

Loop Bandwidth

350 kHz

29

RSSI Linearity ±0.7 %(ADI+) - (ADI-) = 2mVp-p to 50mVp-p
RSSI Slope mV/dB

(ADI+) - (ADI-) = 2mVp-p to
50mVp-p (Note 8)

UI

f=10kHz
f=25kHz
f = 250kHz
f=1MHz

CF= 0.022µF, RF= 523Ω

CF= 0.022µF, RF= 523Ω

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

4 _______________________________________________________________________________________

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

380ps/div

CLOCK

DATA

RECOVERED DATA AND
CLOCK (SINGLE ENDED)

MAX3675 TOC01

JITTER FREQUENCY (Hz)

2

23

-1 PATTERN

V

CC

= +3.3V

RF = 520Ω
C

F

= 0.022µF

20ps/div

RECOVERED CLOCK JITTER

MAX3675 TOC02

JITTER FREQUENCY (Hz)

2

23

-1 PATTERN

V

CC

= +3.3V

R

F

= 520Ω

C

F

= 0.022µF

RMS∆ = 12.8ps

10

-2

10

-3

10

-4

10

-5

10

-6

10

-7

10

-8

10

-9

10

-10

600µ 800µ700µ 900µ 1m 1.1m 1.2m 1.3m

BIT ERROR RATE

vs. INPUT VOLTAGE

MAX3675 TOC03

INPUT VOLTAGE (Vp-p)

BIT ERROR RATE

2

23

-1 PATTERN

V

CC

= +3.3V

10

0.1
10k 100k 1M

JITTER TOLERANCE

MAX3675 TOC04

JITTER FREQUENCY (Hz)

INPUT JITTER (UIp-p)

1

2

23

-1 PATTERN

V

CC

= +3.3V

R

F

= 52.3Ω

C

F

= 2.2µF

BELLCORE
MASK

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

-1.6

-1.8

-2.0

-2.2

-2.4

-2.6

-2.8

-3.0
2k 10k 100k 700k

JITTER TRANSFER

MAX3675 TOC05

JITTER FREQUENCY (Hz)

JITTER TRANSFER (dB)

2

23

-1 PATTERN

V

CC

= +3.3V
RF = 52.3Ω
CF = 2.2µF

BELLCORE
MASK

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

_______________________________________________________________________________________ 5

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

2.0

2.6

2.4

2.2

2.8

3.0

3.2

3.4

3.6

3.8

4.0

-40 0-20 20 40 60 80

LOSS-OF-POWER

HYSTERESIS vs. TEMPERATURE

MAS3675 TOC06

AMBIENT TEMPERATURE (°C)

HYSTERESIS (dB)

2

23

-1 PATTERN

V

CC

= +3.3V OR +5.0V

2.8

1.2
100µ 10m 100m1m 1

RECEIVED-SIGNAL-STRENTH INDICATOR

vs. INPUT VOLTAGE

1.4

1.6

MAX3675 TOC07

INPUT VOLTAGE (Vp-p)

RSSI (V)

1.8

2.0

2.2

2.4

2.6

V

CC

= +3.3V

2

23

-1 PATTERN

1010 PATTERN

100m

1m

1.3 2.52.42.32.22.12.01.91.81.71.61.51.4

LOSS-OF-POWER

ASSERT AND RELEASE LEVEL

vs. THRESHOLD VOLTAGE

MAX4108/9-08

DETECTOR THRESHOLD VOLTAGE, VTH (V)

ANALOG INPUT VOLTAGE (Vp-p)

10m

LOP RELEASE

LOP ASSERT

2

23

-1 PATTERN

V

CC

= +3.3V

2.8

1.2

100µ 10m 100m1m 1

RECEIVED-SIGNAL-STRENGTH INDICATOR

vs. INPUT VOLTAGE

1.4

1.6

MAX3675 TOC09

INPUT VOLTAGE (Vp-p)

RSSI (V)

1.8

2.0

2.2

2.4

2.6

V

CC

= 5.0V

V

CC

= 3.3V

2

23

-1 PATTERN

30

50

40

70

60

80

90

-40 0 20-20 40 60 80

SUPPLY CURRENT
vs. TEMPERATURE

MAX3675 TOC10

AMBIENT TEMPERATURE (°C)

SUPPLY CURRENT (mA)

V

CC

= 3.3V

V

CC

= 5.0V

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

6 _______________________________________________________________________________________

______________________________________________________________Pin Description

32 CFILT RSSI Filter Capacitor Input

30 ADI+ Positive Analog Data Input, 622.08Mbps serial-data stream

29 ADI- Negative Analog Data Input, 622.08Mbps serial-data stream

28 INSEL Input Select. Connect to GND to select digital data inputs or VCCfor analog data inputs.

27 DDI- Negative Digital Data Input, PECL, 622.08Mbps serial-data stream

26 DDI+ Positive Digital Data Input, PECL, 622.08Mbps serial-data stream

23 FIL+ Positive Filter Input. PLL loop filter connection.

22 FIL- Negative Filter Input. PLL loop filter connection.

20 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCCif not used.

19 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCCif not used.

NAME FUNCTION

1 OLC+ Positive Offset-Correction Loop Capacitor Input
2 OLC- Negative Offset-Correction Loop Capacitor Input

PIN

3 RSSI Received-Signal-Strength Indicator Output

4, 8, 16,

24, 25

GND Supply Ground

9, 12, 15,

18, 21, 31

V

CC

Positive Supply Voltage

7 LOP

Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal
is below threshold set by VTH.

6 VTH

Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCCif LOP function
is not used.

5 INV Op-Amp Inverting Input. Attach to ground if op amp is not used.

17

LOL

Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see

Design Procedure

).

14 SDO+ Positive Serial Data Output, PECL, 622.08Mbps

13 SDO- Negative Serial Data Output, PECL, 622.08Mbps

11 SCLKO+ Positive Serial Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+.

10 SCLKO- Negative Serial Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-.

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

_______________________________________________________________________________________ 7

_______________Detailed Description

The block diagram in Figure 1 shows the MAX3675’s
architecture. It consists of a limiting amplifier input
stage followed by a fully integrated clock/data-recovery
(CDR) block implemented with a phase-locked loop
(PLL). The input stage is selectable between a limiting
amplifier or a simple PECL input buffer. The limiting
amplifier provides a loss-of-power (LOP) monitor and a
received-signal-strength indicator (RSSI). The PLL con­sists of a phase/frequency detector (PFD), a loop filter
amplifier, and a voltage-controlled oscillator (VCO).

Limiting Amplifier

The MAX3675’s on-chip limiting amplifier accepts an
input signal level from 3.0mVp-p to 1.2Vp-p. The ampli­fier consists of a cascade of gain stages that include
full-wave logarithmic detectors. The combined small­signal gain is approximately 42dB, and the -3dB band­width is 800MHz. Input-referred noise is less than

100µV

RMS

, providing excellent sensitivity for small-

amplitude data streams.
In addition to driving the CDR, the limiting amplifier pro-

vides both an RSSI output and an LOP monitor that
allow the user to program the threshold voltage. The
RSSI circuitry provides an output voltage that is linearly
proportional to the input power (in decibels) detected
between the ADI+ and ADI- input pins and is sensitive
enough to reliably detect signals as small as 2mVp-p.

Input DC offset reduces the accuracy of the power
detector; therefore, an integrated feedback loop is
included that automatically nulls the input offset of the
gain stage. The addition of this offset-correction loop
requires that the input signal be AC coupled when
using the ADI+ and ADI- inputs.

Finally, for applications that do not require the limiting
amplifier, selecting the digital inputs conserves power
by turning off the post-amplifier block.

MAX3675

LOL

PHASE/FREQ

DETECTOR

POWER

DETECT

OFFSET

CORRECTION

FILTER

622.08MHz

LIMITER

42dB

BIAS

VCO

Σ

DQ

Q

I

CFILT RSSI INV VTH LOP

FIL+ FIL-PHADJ+

DDI+

DDI-

INSEL

ADI-

ADI+

PHADJ-

1.18V

SDO+
SDO-

PECL

V

CC

V

CC

6k

6k

PECL

PECL

SCLKO+
SCLKO-

OLC+ OLC-

Figure 1. Functional Diagram

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

8 _______________________________________________________________________________________

Phase Detector

The phase detector produces a voltage proportional to
the phase difference between the incoming data and
the internal clock. Because of its feedback nature, the
PLL drives the error voltage to zero, aligning the recov­ered clock to the incoming data. The external phase
adjustment pins (PHADJ+, PHADJ-) allow the user to
vary the internal phase alignment.

Frequency Detector

A frequency detector incorporated into the PLL aids
frequency acquisition during start-up conditions. The
input data stream is sampled by quadrature compo­nents of the VCO clock, generating a difference fre­quency. Depending on the polarity of the difference
frequency, the PFD drives the VCO so that the differ­ence frequency is reduced to zero. Once frequency
acquisition is obtained, the frequency detector returns
to a neutral state.

Loop Filter and VCO

The VCO is fully integrated, while the loop filter requires
an external R-C network. This filter network determines
the bandwidth and peaking of the second-order PLL.

__________________Design Procedure

Received-Signal-Strength

Indicator (RSSI)

The RSSI output voltage is insensitive to temperature
and supply fluctuations. The power detector functions
as a broadband power meter that detects the total RMS
power of all signals within the detector bandwidth
(including input signal noise). The RSSI voltage varies
linearly (in decibels) for inputs of 2mVp-p to 50mVp-p.
The slope over this input range is approximately
29mV/dB.

The high-speed RSSI signal is filtered to an RMS level
with one external capacitor tied from CFILT to V

CC

. The
impedance looking into CFILT is about 500Ω to VCC. As
a result, the lower -3dB cutoff frequency is set by the
following simple relationship:

For 622Mbps applications, Maxim recommends a cut­off frequency of 6.8kHz, which requires CF= 47nF. The
RSSI output is designed to drive a minimum load resis­tance of 10kΩ to ground and a maximum of 20pF.
Loads greater than 20pF must be buffered by a series
resistance of 10kΩ (i.e., voltmeter).

Input Offset Correction

The on-chip limiting amplifier provides more than 42dB
of gain. A low-frequency feedback loop is integrated

into the MAX3675 to remove the input offset. DC cou­pling to the ADI+ and ADI- inputs is not allowed, as this
would prevent the proper functioning of the DC offset­correction circuitry.

The differential input impedance (Z

IN

) is approximately

2.5kΩ. The impedance between OLC+ and OLC- (Z

OLC

)
is approximately 120kΩ. Take care when setting the
combined low-frequency cutoff (f

CUTOFF

), due to the
input DC-blocking capacitor (CIN) and the offset correc­tion loop capacitor (C

OLC

). Refer to Table 1 for selecting

the values of CINand C

OLC

.

These values ensure that the poles associated with C

IN

and C

OLC

work together to provide a flat response at the

lower -3dB corner frequency (no gain peaking).
CINmust be a low-TC, high-quality capacitor of type X7R

or better in order to minimize f

CUTOFF

deviations. C

OLC

must be a capacitor of type Z5U or better.

Loss-of-Power (LOP) Monitor

A LOP monitor with a user-programmable threshold
and a hysteresis comparator is also included with the
limiting amplifier circuitry. Internally, one comparator
input is tied to the RSSI output signal, and the other is
tied to the threshold voltage (VTH), which is set exter­nally and provides a trip point for the LOP indication. A
low-voltage, low-drift op amp, referenced to an internal
bandgap voltage (1.18V), is supplied for programming
a supply-independent threshold voltage. This op amp
requires two external resistors to program the LOP trip
point. VTHis programmable from 1.18V to 2.4V using
the equation:

The op amp can source only 20µA of current.
Therefore, an R1 value greater than or equal to 100kΩ
is recommended for proper operation. The input bias

V = 1.181 + R2 / R1

TH

()

f = 1 / 2 500

FILT

π

()

[]

C

F

C

OLC

COMBINED LOW

f

CUTOFF

(kHz)

2200pF 4700pF 29
1000pF 3300pF 68

C

IN

470pF 1000pF 135
330pF 680pF 190
220pF 470pF 290

Table 1. Setting the Low-Frequency Cutoff

4700pF 0.010µF 13.5

6800pF 0.022µF 10

0.010µF 0.033µF 6.8

0.022µF 0.047µF 3.0

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

_______________________________________________________________________________________ 9

current of the op amp at the INV pin is guaranteed to
be less than ±100nA. To set the threshold voltage
externally (i.e., via a DAC control), completely disable
the op amp by grounding the inverting terminal (INV).
VTHthen becomes high impedance and must be driven
externally.

The comparator is configured with an active-high LOP
output. An on-chip, 6kΩ pull-up resistor is provided to
reduce external part count.

Setting the Loop Filter

The loop filter within the PLL consists of a transconduc­tance amplifier and external filter elements RFand C

F

(Figure 2). The closed-loop bandwidth of a PLL is
approximated by:

where KDis the gain of the phase detector, KOis the
gain of the VCO, and Gm is the transconductance of

the filter amplifier. For the MAX3675, an estimated value
of K

DKO

Gm is 7k.

Because the PLL is a second-order system, a zero in
the open-loop gain is required for stability. This zero is
set by the following equation:

where the recommended external value of CFis 2.2µF.
Increasing the value of RFincreases the PLL bandwidth

(f

LOOP

). Increasing this bandwidth improves jitter toler­ance and jitter-generation performance, but also
reduces jitter-transfer performance. (Decreasing the
bandwidth has the opposite effect.)

This type of PLL is a classical second-order system.
Therefore, as fz(the frequency of the zero) approaches
f

LOOP

, the jitter-transfer peaking increases. For an over-

damped system (fz/f

LOOP

) < 0.25, the jitter peaking of a

second-order system can be approximated by:

Mp = 1 - (fz/ f

LOOP

)

where Mp is the magnitude of the peaking. For
(fz/f

LOOP

) < 0.1, this equation holds to within 10%.

CFcan be made smaller if meeting the jitter-transfer
specifications is not a requirement. For example, setting
RFto 300Ω and CFto 3.3nF increases the loop band­width to approximately 2.2MHz (Figure 3). Loop stability
is ensured by maintaining a separation of 10x between
f

LOOP

and fz. Be careful when changing the value of RF.
Lower values of RFare limited by the internal resistance
of the IC, and upper values are limited by the internal
high-frequency pole.

ω

zFF

= 1 / R C

()

K K Gm R

DO F

MAX3675

F(S)

C

F

R

F

GM

FIL+

FIL-

Figure 2. Loop Filter

F(s) =

Gm

s

s C s/

1

RC
R
C 2.2 F

internal higher- order pole

z

FP

FF

F

F

ω

ω

ω

µ

ω

+











()

+

[]

=

=
=

=

1

1

52 3

z

P

.

Ω

100 1k 10k 100k 1M 10M 100M 1G

MAX3675-B

FREQUENCY (Hz)

GAIN

fZ = 1.38kHz
CF = 2.2µF

HIGHER­ORDER
POLE

>10x

f

LOOP

= 375kHz

RF = 52.3Ω

f

LOOP

= KSKOGmR

F

fZ = 161kHz
CF = 3.3nF

f

LOOP

= 2.2MHz

RF = 300Ω

Figure 3. Loop-Filter Response

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

10 ______________________________________________________________________________________

The MAX3675 is optimally designed to acquire lock and
to provide a bit-error rate (BER) of less than 10

-10

for long
strings of consecutive zeros and ones. Using the recom­mended external component values of RF= 52.3Ω ±1%
and CF= 2.2µF ±20%, measured results show that the
MAX3675 can tolerate 1000 consecutive ones or zeros. It
is important to select a type of capacitor for CFthat has a
temperature stability of ±10% or better. This ensures per­formance over the -40°C to +85°C temperature range.

Lock Detect

The MAX3675’s loss-of-lock (LOL) monitor indicates
when the PLL is locked. Under normal operation, the
loop is locked and the LOL output signal is high. When
the MAX3675 loses lock, a fast negative-edge transition
occurs on LOL. The output level remains at a low
level (held by C

LOL

) until the loop reacquires lock

(Figure 4).
Note that the LOL monitor is only valid when a data

stream is present on the inputs to the MAX3675. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal. See the

Loss-of-Power (LOP) Monitor

section for this type of

indicator.

Input and Output Terminations

The MAX3675 digital data and clock I/Os (DDI+, DDI-,
SDO+, SDO-, SCLK+, and SCLK-) are designed to
interface with PECL signal levels. It is important to bias
these ports appropriately. A circuit that provides a
Thevenin equivalent of 50Ω to VCC- 2V should be used
with fixed-impedance transmission lines for proper ter­mination. Make sure that the differential outputs have
balanced loads.

The digital data input signals (DDI+ and DDI-) are dif­ferential inputs to an emitter-coupled pair. As a result,
the MAX3675 can accept differential input signals as
low as 250mV. These inputs can also be driven single­ended by externally biasing DDI- to the center of the
voltage swing.

The MAX3675’s performance can be greatly affected
by circuit board layout and design. Use good high-fre­quency design techniques, including minimizing
ground inductance and using fixed-impedance trans­mission lines on the data and clock signals. Power-sup­ply decoupling should be placed as close to V

CC

as
possible. Take care to isolate the input from the output
signals to reduce feedthrough.

__________Applications Information

Driving the Limiting Amplifier

Single-Ended

There are three important requirements for driving the
limiting amplifier from a single-ended source (Figure 5):

1) There must be no DC coupling to the ADI+ and ADI-

inputs. DC levels at these inputs disrupt the
offset-correction loop.

2) The terminating resistor RT(50Ω) must be referenced

to the ADI- input to minimize common-mode coupling
problems.

3) The low-frequency cutoff for the limiting amplifier

is determined by either CINand the 2.5kΩ input
impedance or Cb/2 together with RT. With Cb= 0.22µF
and RT= 50Ω, the low-frequency cutoff is 29kHz.

ACQUIRENO DATA

LOP

OUTPUT LEVEL

LOCKED

TIME

LOL

Figure 4. Loss-of-Lock Output

C

IN

5.6nF

C

b

0.22µF

C

b

0.22µF

R

T

50Ω

2.5k

ADI+

ADI-

MAX3675

Figure 5. Single-Ended Input Termination

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

______________________________________________________________________________________ 11

Reduced Power Consumption

Without the Limiting Amplifier

The limiting amplifier is biased independently from the
clock recovery circuitry. Grounding INSEL turns off the
limiting amplifier and selects the PECL DDI inputs.

Converting Average Optical Power

to Signal Amplitude

Many of the MAX3675’s specifications relate to input­signal amplitude. When working with fiber optic
receivers, the input is usually expressed in terms of
average optical power and extinction ratio. The rela­tions given in Table 2 and Figure 6 are helpful for con­verting optical power to input signal when designing
with the MAX3675.

In an optical receiver, the input voltage to the limiting
amplifier can be found by multiplying the relationship in
Table 2 by the photodiode responsivity and transim­pedance amplifier gain.

Optical Hysteresis

Power and hysteresis are often expressed in decibels.
By definition, decibels are always 10log (power). At the
inputs to the MAX3675 limiting amplifier, the power is
V

IN

2

/R. If a receiver’s optical input power (x) increases
by a factor of two, and the preamplifier is linear, then the
voltage at the input to the MAX3675 also increases by a
factor of two.

The optical power increase is 10log(2x / x) = 10log(2) =
+3dB.

At the MAX3675, the voltage increase is:

In an optical receiver, the dB change at the MAX3675
always equals 2x the optical dB change.

The MAX3675’s typical voltage hysteresis is 3.0dB. This
provides an optical hysteresis of 1.5dB.

Jitter in Optical Receivers

Timing jitter, edge speeds, aberrations, optical disper­sion, and attenuation all impact the performance of
high-speed clock recovery for SDH/SONET receivers
(Figure 7). These effects decrease the time available
for error-free data recovery by reducing the received
“eye opening” of non-return-to-zero (NRZ) transmitted
signals.

10 10 2 20 2 6

2

2

2

log log( ) log( )

2V / R

V/ R

IN

IN

()

===+dB

TIME

P0

P1

P

AVE

Figure 6. Optical Power Relations

Table 2. Optical-Power Relations*

*Assuming a 50% average input data duty cycle.

SYMBOL RELATION

Average
Power

P

AVE

Extinction
Ratio

r

e

PARAMETER

Optical Power
of a “1”

P1

Optical Power
of a “0”

P0

Signal
Amplitude

P

IN

Figure 7. Eye Diagram With and Without Timing Jitter

P = P0 + P1

()

AVE

r = 1 / P0

P

e

PP

121=

AVE

PP r

02 1=+

AVE e

PPPP

=−=

102

IN AVE

/2

r

e

r

+

e

/

()

r

−

()

e

r

+

e

AMPLITUDE

EYE DIAGRAM WITH NO TIMING JITTER

AMPLITUDE

1
1

EFFECTS OF TIMING JITTER ON EYE DIAGRAM TIME

MIDPOINT

TIME

MIDPOINT

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

12 ______________________________________________________________________________________

Optical receivers, incorporating transimpedance
preamplifiers and limiting postamplifiers, can signifi­cantly clean up the effects of dispersion and attenua­tion. In addition, these amplifiers can provide fast
transitions with minimal aberrations to the subsequent
clock and data-recovery (CDR) blocks. However, these
stages also add distortions to the midpoint crossing,
contributing to timing jitter. Timing jitter is one of the
most critical technical issues to consider when devel­oping optical receivers and CDR circuits.

A better understanding of the different sources of jitter
helps in the design and application of optical receiver
modules and integrated CDR solutions. SDH/SONET
specifications are well defined regarding the amount of
jitter tolerance allowed at the inputs of optical receivers,
as well as jitter peaking requirements, but they do little
to define the different sources of jitter. The jitter that
must be tolerated at an optical receiver input involves
three significant sources, all of which are present in
varying degrees in typical receiver systems:

1) Random jitter (RJ)

2) Pattern-dependent jitter (PDJ)

3) Pulse-width distortion (PWD)

Random Jitter (RJ)

RJ is caused by random noise present during edge
transitions (Figure 8). This random noise results in ran­dom midpoint crossings. All electrical systems gener­ate some random noise; however, the faster the speed

of the transitions, the lower the effect of noise on ran­dom jitter. The following equation is a simple worst­case estimation of random jitter:

RJ (rms) = (rms noise) / (slew rate)

Pattern-Dependent Jitter (PDJ)

PDJ results from wide variations in the number of con­secutive bits contained in NRZ data streams working
against the bandwidth requirements of the receiver
(Figure 9). The location of the lower -3dB cutoff fre­quency is important, and must be set to pass the low
frequencies associated with long consecutive bit
streams. AC coupling is common in optical receiver
design.

When using a limiting preamplifier with a highpass fre­quency response, select the input AC-coupling capaci­tor, CIN, to provide a low-frequency cutoff (fC) one
decade lower than the preamplifier low-frequency cut­off. As a result, the PDJ is dominated by the low­frequency cutoff of the preamplifier.

When using a preamplifier without a highpass response
with the MAX3675, the following equation provides a
good starting point for choosing CIN:

where t

L

= duration of the longest run of consecutive

bits of the same value (seconds); PDJ = maximum

C

-t

1.25k In

PDJ BW

IN

L

≥

()

−

()()













Ω .1

05

MIDPOINT

MIDPOINT

RANDOM

JITTER

ACTUAL

MIDPOINT

CROSSING

DESIRED
MIDPOINT
CROSSING

0–1
TRANSITION
WITH RANDOM
NOISE

TIME

AMPLITUDE

Figure 8. Random Jitter on Edge Transition

AMPLITUDE

TIME

MIDPOINT

LONG
CONSECUTIVE
BIT STREAM

0-1-0 BIT STREAM

LF DROOP

LF PDJ

Figure 9. Pattern-Dependent Jitter Due to Low-Frequency
Cutoff

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

______________________________________________________________________________________ 13

allowable pattern-dependent jitter, peak-to-peak
(seconds); and BW = typical system bandwidth, nor­mally 0.6 to 1.0 times the data rate (Hertz). If the PDJ is
still larger than desired, continue increasing the value of
CIN. Note that to maintain stability when using the
MAX3675 analog inputs (ADI+, ADI-), it is important to
keep the low-frequency cutoff associated with C

OLC

below the corner frequency associated with CIN(fC)
(Table 1).

PDJ can also be present due to insufficient high-fre­quency bandwidth (Figure 10). If the amplifiers are not
fast enough to allow for complete transitions during sin­gle-bit patterns, or if the amplifier does not allow ade­quate settling time, high-frequency PDJ can result.

Pulse-Width Distortion (PWD)

Finally, PWD occurs when the midpoint crossing of a
0–1 transition and a 1–0 transition do not occur at the

same level (Figure 11). DC offsets and nonsymmetrical
rising and falling edge speeds both contribute to PWD.
For a 1–0 bit stream, calculate PWD as follows:

PWD = [(width of wider pulse) -

(width of narrower pulse)] / 2

Phase Adjust

The internal clock and data alignment in the MAX3675
is well maintained close to the center of the data eye.
Although not required, this sampling point can be shift­ed using the PHADJ inputs to optimize BER perfor­mance. The PHADJ inputs operate with differential
input signals to approximately ±1V. A simple resistor
divider with a bypass capacitor is sufficient to set up
these levels. When the PHADJ inputs are not used, they
should be tied directly to VCC.

Figure 10. Pattern-Dependent Jitter Due to High-Frequency
Rolloff

AMPLITUDE

TIME

MIDPOINT

LONG
CONSECUTIVE
BIT STREAM

0-1-0 BIT STREAM

HF PDJ

Figure 11. Pulse-Width Distortion

AMPLITUDE

TIME

MIDPOINT

WIDTH OF A ONE

WIDTH OF A ZERO

PWD RESULTS WHEN THE WIDTH

OF A ZERO DOES NOT EQUAL

THE WIDTH OF A ONE

t

FALL

≠ t

RISE

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

14 ______________________________________________________________________________________

__________________Pin Configuration

242322

21

201918

17

1

2

3

4

5

6

7

8

25
26
27
28
29
30
31
32

9

10

11

12

13

14

15

16

CFILT

OLC-

GND

MAX3675

TOP VIEW

FIL+

FIL-

V

CC

PHADJ+

PHADJ-

V

CC

OLC+

GND

RSSI

VTH

INV

GND

LOP

GND
V

CC

SDO+
SDO­V

CC

SCLKO+
SCLKO­V

CC

V

CC

ADI+

ADI-

INSEL

DDI-

DDI+

GND

TQFP

LOL

___________________Chip Topography

GND

DDI+

DDI-

INSEL

ADI-

OLC+ RSSI INV LOP

OLC- GND VTH GND

ADI+

V

CC

CFILT

GND
V

CC

SDO+
SDO­V

CC

SCLKO+
SCLKO-

V

CC

GND FIL- V

CC

PHADJ+

FIL+ V

CC

LOLPHADJ-

GND FIL- V

CC

PHADJ+

FIL+ V

CC

LOLPHADJ-

0.069"

(1.753mm)

0.068"

(1.727mm)

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery

and Data-Retiming IC with Limiting Amplifier

______________________________________________________________________________________ 15

________________________________________________________Package Information

32TQFP.EPS

MAX3675

622Mbps, Low-Power, 3.3V Clock-Recovery
and Data-Retiming IC with Limiting Amplifier

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

NOTES