MAXIM MAX3421E Technical data

General Description

The MAX3421E USB peripheral/host controller contains
the digital logic and analog circuitry necessary to
implement a full-speed USB peripheral or a full-/low­speed host compliant to USB specification rev 2.0. A
built-in transceiver features ±15kV ESD protection and
programmable USB connect and disconnect. An inter­nal serial interface engine (SIE) handles low-level USB
protocol details such as error checking and bus retries.
The MAX3421E operates using a register set accessed
by an SPI™ interface that operates up to 26MHz. Any
SPI master (microprocessor, ASIC, DSP, etc.) can add
USB peripheral or host functionality using the simple 3­or 4-wire SPI interface.

The MAX3421E makes the vast collection of USB
peripherals available to any microprocessor, ASIC, or
DSP when it operates as a USB host. For point-to-point
solutions, for example, a USB keyboard or mouse inter­faced to an embedded system, the firmware that oper­ates the MAX3421E can be simple since only a
targeted device is supported.

Internal level translators allow the SPI interface to run at
a system voltage between 1.4V and 3.6V. USB-timed
operations are done inside the MAX3421E with inter­rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3421E includes eight general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.

The MAX3421E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
TQFP package (5mm x 5mm) and a 32-pin TQFN pack­age (5mm x 5mm).

Applications

Features

♦ Microprocessor-Independent USB Solution

♦ Software Compatible with the MAX3420E USB

Peripheral Controller with SPI Interface

♦ Complies with USB Specification Revision 2.0

(Full-Speed 12Mbps Peripheral, Full-/Low-Speed
12Mbps/1.5Mbps Host)

♦ Integrated USB Transceiver

♦ Firmware/Hardware Control of an Internal D+

Pullup Resistor (Peripheral Mode) and D+/D­Pulldown Resistors (Host Mode)

♦ Programmable 3- or 4-Wire, 26MHz SPI Interface

♦ Level Translators and VLInput Allow Independent

System Interface Voltage

♦ Internal Comparator Detects V

BUS

for Self-

Powered Peripheral Applications

♦ ESD Protection on D+, D-, and VBCOMP

♦ Interrupt Output Pin (Level- or Programmable-

Edge) Allows Polled or Interrupt-Driven SPI
Interface

♦ Eight General-Purpose Inputs and Eight General-

Purpose Outputs

♦ Interrupt Signal for General-Purpose Input Pins,

Programmable Edge Polarity

♦ Intelligent USB SIE

♦ Automatically Handles USB Flow Control and

Double Buffering

♦ Handles Low-Level USB Signaling Details

♦ Contains Timers for USB Time-Sensitive

Operations so SPI Master Does Not Need to Time
Events

♦ Space-Saving Lead-Free TQFP and TQFN

Packages (5mm x 5mm)

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

________________________________________________________________ Maxim Integrated Products 1

19-3953; Rev 0; 2/06

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Embedded Systems
Medical Devices
Microprocessors and

DSPs
Custom USB Devices
Cameras

Desktop Routers
PLCs
Set-Top Boxes
PDAs
MP3 Players
Instrumentation

PART

TEMP RANGE

PIN­PACKAGE

PKG CODE

M AX 3421E E H J+

32 TQFP H 32- 1

M AX 3421E E TG+ *

T3255- 4

Ordering Information

*Future product—contact factory for availability.

**EP = Exposed paddle, connected to ground.

SPI is a trademark of Motorola, Inc.

- 40°C to + 85°C

- 40°C to + 85°C 32 TQFN - E P **

MAX3421E

Features in Host Operation

♦ Eleven Registers (R21–R31) are Added to the

MAX3420E Register Set to Control Host Operation

♦ Host Controller Operates at Full Speed or Low

Speed

♦ FIFOS

SNDFIFO: Send FIFO, Double-Buffered 64-Byte
RCVFIFO: Receive FIFO, Double-Buffered 64-Byte

♦ Handles DATA0/DATA1 Toggle Generation and

Checking

♦ Performs Error Checking for All Transfers

♦ Automatically Generates SOF (Full-Speed)/EOP

(Low-Speed) at 1ms Intervals

♦ Automatically Synchronizes Host Transfers with

Beginning of Frame (SOF/EOP)

♦ Reports Results of Host Requests

♦ Supports USB Hubs

♦ Supports ISOCHRONOUS Transfers

♦ Simple Programming

SIE Automatically Generates Periodic SOF
(Full-Speed) or EOP (Low-Speed) Frame
Markers
SPI Master Loads Data, Sets Function Address,
Endpoint, and Transfer Type, and Initiates the
Transfer
MAX3421E Responds with an Interrupt and
Result Code Indicating Peripheral Response
Transfer Request Can be Loaded Any Time
SIE Synchronizes with Frame Markers
For Multipacket Transfers, the SIE
Automatically Maintains and Checks the
Data Toggles

Features in Peripheral Operation

♦ Built-In Endpoint FIFOS

EP0: CONTROL (64 bytes)
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes (Double­Buffered)
EP3: IN, Bulk or Interrupt (64 Bytes)

♦ Double-Buffered Data Endpoints Increase

Throughput by Allowing the SPI Master to
Transfer Data Concurrent with USB Transfers

♦ SETUP Data Has its Own 8-Byte FIFO, Simplifying

Firmware

USB Peripheral/Host Controller
with SPI Interface

2 _______________________________________________________________________________________

The MAX3421E connects to any microprocessor (µP)
using 3 or 4 interface pins (Figure 1). On a simple
microprocessor without SPI hardware, these can be
bit-banged general-purpose I/O pins. Eight GPIN and
eight GPOUT pins on the MAX3421E more than
replace the µP pins necessary to implement the inter­face. Although the MAX3421E SPI hardware includes
separate data-in (MOSI, master-out, slave-in) and data­out (MISO, master-in, slave-out) pins, the SPI interface
can also be configured for the MOSI pin to carry bidi­rectional data, saving an interface pin. This is referred
to as half-duplex mode.

Typical Application Circuits

3.3V

REGULATOR

SPI
3, 4

INT

USB

µ

P

MAX3421E

Figure 1. The MAX3421E Connects to Any Microprocessor
Using 3 or 4 Interface Pins

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

_______________________________________________________________________________________ 3

3.3V

REGULATOR

POWER RAIL

ASIC,

DSP,
ETC.

SPI
3, 4

INT

MAX3421E

USB

Figure 2. The MAX3421E Connected to a Large Chip

3.3V

REGULATOR

MISO

LOCAL
GND

LOCAL
POWER

INT

MAX3421E

SCLK
MOSI

SS

MICRO

ASIC

DSP

I
S
O
L
A
T
O
R
S

USB

Figure 3. Optical Isolation of USB Using the MAX3421E

MICRO,
ASIC,
DSP

USB

PERIPHERAL

USB

"A"

USB

"B"

V

BUS

SWITCH

FAULT

5V

SPI
3, 4

INT

V

BUS

D+

D-

GND

V

BUS

POWER
ON/OFF

3.3V

REGULATOR

MAX3421E

Figure 4. The MAX3421E in an Embedded Host Application

Two MAX3421E features make it easy to connect to
large, fast chips such as ASICs and DSPs (Figure 2).
First, the SPI interface can be clocked up to 26MHz.
Second, the VLpin and internal level translators allow
running the system interface at a lower voltage than
the 3.3V required for VCC.

The MAX3421E provides an ideal method for electrically
isolating a USB interface (Figure 3). USB employs flow
control in which the MAX3421E automatically answers
host requests with a NAK handshake, until the micro­processor completes its data-transfer operations over
the SPI port. This means that the SPI interface can run
at any frequency up to 26MHz. Therefore, the designer
is free to choose the interface operating frequency and
to make opto-isolator choices optimized for cost or per­formance.

Figure 4 shows a block diagram for a system in which
the MAX3421E operates as a USB host. A USB host
supplies 5V power to the V

BUS

pin of the USB “A” con­nector to power USB peripherals. A system that pro­vides power to an external peripheral should use
protection circuitry on the power pin to prevent an
external overcurrent situation from damaging the sys­tem. A V

BUS

switch, such as the MAX4789, provides
power control plus two additional features: it limits the
current delivered to the peripheral (for example to
200mA), and it indicates a fault (overcurrent) condition
to the SPI controller. Maxim offers a variety of V

BUS

switches with various current limits and features.
Consult the Maxim website for details.

A 3.3V regulator (for example, the MAX6349TL) powers
the MAX3421E, and optionally the system controller. If
the system controller operates with a lower voltage, the
MAX3421E SPI and I/O interface can run at the lower
voltage by connecting the system voltage (for exam­ple, 2.5V or 1.8V) to the MAX3421E VLpin.

Typical Application Circuits (continued)

MAX3421E

USB Peripheral/Host Controller
with SPI Interface

4 _______________________________________________________________________________________

Functional Diagram

GPIN0

1V TO 3V

VBCOMP

D-

D+

V

CC

R

GPIN

VBUS

COMP

SS

MISO

SCLK

INT

SPI SLAVE

INTERFACE

USB SIE

(SERIAL-

INTERFACE

ENGINE)

FULL-SPEED/

LOW-SPEED

USB

TRANSCEIVER

RESET
LOGIC

1.5kΩ

INTERNAL

POR

RES XI XO

POWER

DOWN

OSC
AND

4x PLL

48MHz

ESD

PROTECTION

ESD

PROTECTION

GPX

OPERATE

SOF

BUSACT/

INIRQ

MUX

0123

MOSI

VBUS_DET

ENDPOINT

BUFFERS

MAX3421E

GND

GPIN1
GPIN2
GPIN3
GPIN4
GPIN5
GPIN6
GPIN7

GPOUT0
GPOUT1
GPOUT2
GPOUT3
GPOUT4
GPOUT5
GPOUT6
GPOUT7

V

L

R

IN

15kΩ

15kΩ

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

_______________________________________________________________________________________ 5

Pin Description

PIN NAME

INPUT/

FUNCTION

1 GPIN7 Input

General-Purpose Input. GPIN7–GPIN0 are connected to V

L

with internal pullup resistors.

GPIN7–GPIN0 logic levels are referenced to the voltage on V

L

.

2VLInput

Level-Translator Voltage Input. Connect V

L

to the system’s 1.4V to 3.6V logic-level power

supply. Bypass V

L

to ground with a 0.1µF capacitor as close to VL as possible.

3, 19 GND Input Ground

4

5

6

7

8

9

10

11

General-Purpose Push-Pull Outputs. GPOUT7–GPOUT0 logic levels are referenced to the
voltage on V

L

.

12 RES Input

Device Reset. Drive RES low to clear all of the internal registers except for PINCTL (R17),
USBCTL (R15), and SPI logic. The logic level is referenced to the voltage on VL. (See the
Device Reset section for a description of resets available on the MAX3421E.)

13 SCLK Input

SPI Serial-Clock Input. An external SPI master supplies SCLK with frequencies up to 26MHz.
The logic level is referenced to the voltage on V

L

. Data is clocked into the SPI slave interface
on the rising edge of SCLK. Data is clocked out of the SPI slave interface on the falling edge of
SCLK.

14 SS Input

SPI Slave Select Input. The SS logic level is referenced to the voltage on V

L

. When SS is driven

high, the SPI slave interface is not selected, the MISO pin is high impedance, and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low SS transition and ends with a
low-to-high SS transition.

15 MISO

SPI Serial-Data Output (Master-In Slave-Out). MISO is a push-pull output. MISO is tri-stated in
half-duplex mode or when SS = 1. The MISO logic level is referenced to the voltage on V

L

.

16 MOSI

Input or

Input/

SPI Serial-Data Input (Master-Out Slave-In). The logic level on MOSI is referenced to the
voltage on V

L

. MOSI can also be configured as a bidirectional MOSI/MISO input and output.

(See Figure 15.)

17 GPX

General-Purpose Multiplexed Push-Pull Output. The internal MAX3421E signal that appears on
GPX is programmable by writing to the GPXB and GPXA bits of the PINCTL (R17) register and
the SEPIRQ bit of the MODE (R27) register. GPX indicates one of five signals (see the GPX
section).

18 INT

Interrupt Output. In edge mode, the logic level on INT is referenced to the voltage on VL and is
a push-pull output with programmable polarity. In level mode, INT is open-drain and active low.
Set the IE bit in the CPUCTL (R16) register to enable INT.

20 D-

Input/

USB D- Signal. Connect D- to a USB connector through a 33Ω ±1% series resistor. A
switchable 15kΩ D- pulldown resistor is internal to the device.

OUTPUT

GPOUT0

GPOUT1

GPOUT2

GPOUT3

GPOUT4

GPOUT5

GPOUT6

GPOUT7

Output

Output

Output

Output

Output

Output

MAX3421E

USB Peripheral/Host Controller
with SPI Interface

6 _______________________________________________________________________________________

Pin Description (continued)

PIN NAME

INPUT/

FUNCTION

21 D+

Input/

USB D+ Signal. Connect D+ to a USB connector through a 33Ω ±1% series resistor. A
switchable 1.5kΩ D+ pullup resistor and 15kΩ D+ pulldown resistor is internal to the device.

22

Input

V

BUS

Comparator Input. VBCOMP is internally connected to a voltage comparator to allow the
SPI master to detect (through an interrupt or checking a register bit) the presence or loss of
power on V

BUS

. Bypass VBCOMP to ground with a 1.0µF ceramic capacitor. VBCOMP is pulled

down to ground with R

IN

(see Electrical Characteristics).

23 V

CC

Input

USB Transceiver and Logic Core Power-Supply Input. Connect V

CC

to a positive 3.3V power

supply. Bypass V

CC

to ground with a 1.0µF ceramic capacitor as close to the V

CC

pin as

possible.

24 XI Input

Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz ±0.25% crystal
and a load capacitor to GND. XI can also be driven by an external clock referenced to V

CC

.

25 XO

Crystal Oscillator Output. Connect XO to the other side of a parallel resonant 12MHz ±0.25%
crystal and a load capacitor to GND. Leave XO unconnected if XI is driven with an external
source.

26 GPIN0

27 GPIN1

28 GPIN2

29 GPIN3

30 GPIN4

31 GPIN5

32 GPIN6

Input

General-Purpose Inputs. GPIN7–GPIN0 are connected to V

L

with internal pullup resistors.

GPIN7–GPIN0 logic levels are referenced to the voltage on V

L

.

EP GND Input

Exposed Paddle, Connected to Ground. Connect EP to GND or leave unconnected. EP is
located on the bottom of the TQFN package. The TQFP package does not have an exposed
paddle.

OUTPUT

Output

VBCOMP

Output

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

_______________________________________________________________________________________ 7

Register Description

The SPI master controls the MAX3421E by reading and
writing 26 registers in peripheral mode (see Table 1) or
reading and writing 23 registers in host mode (see Table

2). Setting the HOST bit in the MODE (R27) register con­figures the MAX3421E for host operation. When operating
as a USB peripheral, the MAX3421E is register-compati­ble with the MAX3420E with the additional features listed
in Note 1b below Table 1. For a complete description of
register contents, refer to the MAX3421E Programming
Guide on the Maxim website.

A register access consists of the SPI master first writing
an SPI command byte followed by reading or writing the
contents of the addressed register. All SPI transfers are
MSB first. The command byte contains the register
address, a direction bit (read = 0, write = 1), and the
ACKSTAT bit (Figure 5). The SPI master addresses the
MAX3421E registers by writing the binary value of the
register number in the Reg4 through Reg0 bits of the
command byte. For example, to access the IOPINS1
(R20) register, the Reg4 through Reg0 bits would be as
follows: Reg4 = 1, Reg3 = 0, Reg2 = 1, Reg1 = 0, Reg0
= 0. The DIR (direction) bit determines the direction for
the data transfer. DIR = 1 means the data byte(s) are
written to the register, and DIR = 0 means the data
byte(s) are read from the register. The ACKSTAT bit sets
the ACKSTAT bit in the EPSTALLS (R9) register (periph­eral mode only). The SPI master sets this bit to indicate
that it has finished servicing a CONTROL transfer. Since
the bit is frequently used, having it in the SPI command
byte improves firmware efficiency. The ACKSTAT bit is
ignored in host mode. In SPI full-duplex mode, the
MAX3421E clocks out eight USB status bits as the com-

mand byte is clocked in (Figures 6, 7). In half-duplex
mode, these status bits are accessed as register bits.

The first five registers (R0–R4) address FIFOs in both
peripheral and host modes. Repeated accesses to these
registers freeze the internal register address so that mul­tiple bytes may be written to or read from a FIFO in the
same SPI access cycle (while SS is low). Accesses to

registers R5–R19 increment the internal register address
for every byte transferred during the SPI access cycle.
Accessing R20 freezes access at that register, access­ing R21–R31 increments the internal address, and
repeated accesses to R31 freeze at R31.

The register maps in Table 1 and Table 2 show which
register bits apply in peripheral and host modes.
Register bits that do not apply to a particular mode are
shown as zeros. These register bits read as zero values
and should not be written to with a logic 1.

Register Map in Peripheral Mode

The MAX3421E maintains register compatibility with the
MAX3420E when operating in USB peripheral mode
(MAX3421E HOST bit is set to 0 (default)). Firmware
written for the MAX3420E runs without modification on
the MAX3421E. To support new MAX3421E features,
the register set includes new bits, described in Note 1b
at the bottom of Table 1.

Register Map in Host Mode

As Table 2 shows, in host mode (HOST = 1), some
MAX3420E registers are renamed (for example R1
becomes RCVFIFO), some are not used (shown with
zeros), and some still apply to host mode. In addition, 11
registers (R21–R31) add the USB host capability.

Figure 7. USB Status Bits Clocked Out as First Byte of Every Transfer in Host Mode (Full-Duplex Mode Only)

STATUS BITS (HOST MODE)

b7 b6 b5 b4 b3 b2 b1 b0

HXFRDNIRQ

CONNIRQ

BUSEVENTIRQ

*The ACKSTAT bit is ignored in host mode.

Figure 5. SPI Command Byte

b7 b6 b5 b4 b3 b2 b1 b0

Reg4 Reg3 Reg2 Reg1 Reg0 0 DIR

ACKSTAT*

Figure 6. USB Status Bits Clocked Out as First Byte of Every Transfer in Peripheral Mode (Full-Duplex Mode Only)

STATUS BITS (PERIPHERAL MODE)

b7 b6 b5 b4 b3 b2 b1 b0

SUSPIRQ URESIRQ

IN0BAVIRQ

SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ

FRAMEIRQ

SUSDNIRQ SNDBAVIRQ RCVDAVIRQ RSMREQIRQ

MAX3421E

USB Peripheral/Host Controller
with SPI Interface

8 _______________________________________________________________________________________

Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b)

R EG

NAME b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0

a c c

R0

EP0 F IF O b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R1

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R2

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R3

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R4

SU D F IF O b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R5

EP0 B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

R6

0b 6b 5b 4b 3b 2b 1b 0

RS C

R7

EP2 IN B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

R8

EP3 IN B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

R9

0

RS C

R10

C L R T O G S

00

RS C

R11

EPI R Q 00

RC

R12

EPI EN 00

RS C

R13

U SB IR Q

RC

R14

U SB IEN

V BU S IE

RS C

R15

U SB C T L

S IG RWU 0 0

RS C

R16

C PU C T L

000 0 0IE

RS C

R17

PIN C T L

P OS IN TGP X BGP X A

RS C

R18

R EVISIO N 00 000 0 0 1

R

R19

F N A D D R 0b 6b 5b 4b 3b 2b 1b 0

R

R20

IO PIN S1 GP IN 3GP IN 2GP IN 1GP IN 0

GP O U T2 GP O U T1

RS C

R21

IOPINS2

GP IN 7GP IN 6GP IN 5GP IN 4

GP O U T6 GP O U T5

RS C

R22

GPINIRQ

RS C

R23

GPINIEN

RS C

R24

GPINPOL

RS C

R25

—

00 000 0 0 0

—

R26

—

00 000 0 0 0

—

R27

MODE

00 0

00 0

RS C

R28

—

00 000 0 0 0

—

R29

—

00 000 0 0 0

—

R30

—

00 000 0 0 0

—

R31

—

00 000 0 0 0

—

Note 1a: The acc (access) column indicates how the SPI master can access the register.

R = read, RC = read or clear, RSC = read, set, or clear.
Writing to an R register (read only) has no effect.
Writing a 1 to an RC bit (read or clear) clears the bit.
Writing a zero to an RC bit has no effect.

EP1 O U T F IF O

EP2 IN F IF O

EP3 IN F IF O

EP1 O U T B C

EPST A L L S

E P 3D IS AB E P 2D IS AB E P 1D IS AB C TG E P 3IN C TG E P 2IN C TG E P 1OU T

U RE S D N IRQ V BU S IRQ N OV BU S IRQ S U S P IRQ U RE S IRQ BU S AC TIRQ RWU D N IRQ OS C OKIRQ

U RE S D N IE

H OS C S TE N V BG ATE C H IP RE S P WRD OWN C ON N E C T

P U LS E WID 1P U LS E WID 0

E P 3IN AK E P 2IN AK E P 0IN AK FD U P S P IIN TLE V E L

GP IN IRQ7 GP IN IRQ6 GP IN IRQ5 GP IN IRQ4 GP IN IRQ3 GP IN IRQ2 GP IN IRQ1 GP IN IRQ0

GP IN IE N 7GP IN IE N 6GP IN IE N 5GP IN IE N 4GP IN IE N 3GP IN IE N 2GP IN IE N 1GP IN IE N 0

GP IN P OL7 GP IN P OL6 GP IN P OL5 GP IN P OL4 GP IN P OL3 GP IN P OL2 GP IN P OL1 GP IN P OL0

AC KS TAT S TLS TAT S TLE P 3IN S TLE P 2IN S TLE P 1OU TS TLE P 0OU TS TLE P 0IN

S U D AV IRQ IN 3BAV IRQ IN 2BAV IRQ OU T1D AV IRQ OU T0D AV IRQ IN 0BAV IRQ

S U D AV IE IN 3BAV IE IN 2BAV IE OU T1D AV IE OU T0D AV IE IN 0BAV IE

N OV BU S IE S U S P IE U RE S IE BU S AC TIE RWU D N IE OS C OKIE

GP O U T3

GP O U T7

S E P IRQ

GP O U T0

GP O U T4

H OS T = 0

MAX3421E

USB Peripheral/Host Controller

with SPI Interface

_______________________________________________________________________________________ 9

Note 1b: In peripheral mode, the MAX3421E performs identically to the MAX3420E with the following enhancements:

1) R16 adds the PULSEWID0 and PULSEWID1 bits to control the INT pulse width in edge interrupt mode
(see Figure 12.) These bits default to the MAX3420E setting of 10.6µs.

2) R21 adds four more GPIO bits.

3) R22 and R23 add general-purpose input pins to the interrupt system. R24 controls the edge polarity.

4) R27 controls the peripheral/host mode and the SEPIRQ bit.

5) When [GPXB:GPXA] = [1:0] and the bit SEPIRQ = 1 (R27 bit 4), the GPX output replaces the BUSACT
signal with a second IRQ pin dedicated to the GPIN pin interrupts.

Table 2. MAX3421E Register Map in Host Mode (HOST = 1) (Note 2)

R EG

b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0

a c c

R0

—00000000—

R1

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R2

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R3

—00000000—

R4

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

R5

—00000000—

R6

RCVBC

0BC 6BC 5BC 4BC 3BC 2BC 1BC 0

RS C

R7

SNDBC

0BC 6BC 5BC 4BC 3BC 2BC 1BC 0

RS C

R8

—

00000 0 0 0—

R9

—

00000 0 0 0—

R10

—

00000 0 0 0—

R11

—

00000 0 0 0—

R12

—

00000 0 0 0—

R13

USBIRQ

0

00 0 0

RC

R14

USBIEN

0V BU S IE

00 0 0OS C OKIE

RS C

R15

USBCTL

00

00 0 0

RS C

R16

CPUCTL

00 0 0 0 IE

RS C

R17

PINCTL

E P 3IN AK

P OS IN TGP X BGP X A

RS C

R18

00000 0 0 1R

R19

—

00000 0 0 0—

R20

IOPINS1

GP IN 3GP IN 2GP IN 1GP IN 0GP O U T3 GP O U T2 GP O U T1 GP O U T0

RS C

R21

IOPINS2

GP IN 7GP IN 6GP IN 5GP IN 4GP O U T7 GP O U T6 GP O U T5 GP O U T4

RS C

R22

GP IN IRQ0

RC

R23

GPINIEN

GP IN IE N 1GP IN IE N 0

RS C

R24

GP IN P OL0

RS C

R25

HIRQ

RC

R26

HIEN

RS C

R27

MODE

H U BP RE S P E E D H OS T = 1

RS C

R28

0b 6b 5b 4b 3b 2b 1b 0

RS C

R29

HCTL

S IG RS M

FRM RS TBU S RS TLS

R30

HXFR

H S IS O

S E TU P E P 3E P 2E P 1E P 0LS

R31

HRSL

H RS LT3 H RS LT2 H RS LT1 H RS LT0 R

Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b) (Continued)

NAME

RCVFIFO

SNDFIFO

SUDFIFO

REVISION

GPINIRQ

GPINPOL

PERADDR

P U LS E WID 1P U LS E WID 0

GP IN IRQ7 GP IN IRQ6 GP IN IRQ5 GP IN IRQ4 GP IN IRQ3 GP IN IRQ2 GP IN IRQ1

GP IN IE N 7GP IN IE N 6GP IN IE N 5GP IN IE N 4GP IN IE N 3GP IN IE N 2

GP IN P OL7 GP IN P OL6 GP IN P OL5 GP IN P OL4 GP IN P OL3 GP IN P OL2 GP IN P OL1

H X FRD N IRQ FRAM E IRQ C ON N IRQ S U S D N IRQ S N D BAV IRQ RC V D AV IRQ RS M RE QIRQ BU S E V E N TIRQ

H X FRD N IE FRAM E IE C ON N IE S U S D N IE S N D BAV IE RC V D AV IE RS M RE QIE BU S E V E N TIE

D P P U LLD N D M P U LLD N D E LAY IS OS E P IRQ S OFKAE N AB

S N D TOG1 S N D TOG0 RC V TOG1 RC V TOG0

JS TATU S KS TATU S S N D TOGRD RC V TOGRD

V BU S IRQ N OV BU S IRQ

N OV BU S IE

C H IP RE S P WRD OWN

E P 2IN AK E P 0IN AK FD U P S P IIN TLE V E L

BU S S AM P LE

OU TN IN

OS C OKIRQ