The MAX3301E/MAX3302E fully integrated USB On-theGo (OTG) transceivers and charge pumps allow mobile
devices such as PDAs, cellular phones, and digital
cameras to interface directly with USB peripherals and
each other without the need of a host PC. Use the
MAX3301E/MAX3302E with an embedded USB host to
directly connect to peripherals such as printers or
external hard drives.
The MAX3301E/MAX3302E integrate a USB OTG transceiver, a V
BUS
charge pump, a linear regulator, and an
I
2
C-compatible, 2-wire serial interface. An internal level
shifter allows the MAX3301E/MAX3302E to interface
with +1.65V to +3.6V logic supply voltages. The
MAX3301E/MAX3302E’s OTG-compliant charge pump
operates with +3V to +4.5V input supply voltages, and
supplies an OTG-compatible output on V
BUS
while
sourcing more than 8mA of output current.
The MAX3301E/MAX3302E enable USB OTG communi-
cation from highly integrated digital devices that cannot
supply or tolerate the +5V V
BUS
levels that USB OTG
requires. The device supports USB OTG session-request
protocol (SRP) and host-negotiation protocol (HNP).
The MAX3301E/MAX3302E provide built-in ±15kV electrostatic-discharge (ESD) protection for the V
BUS
, ID_IN,
D+, and D- terminals. The MAX3301E/MAX3302E are
available in 25-bump chip-scale (UCSP™), 25-bump
WLP package, 28-pin TQFN, and 32-pin TQFN packages and operate over the extended -40°C to +85°C
temperature range.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Note: All devices specified over the -40°C to +85°C operating
range.
‡
UCSP bumps are in a 5 x 5 array. The UCSP package size is
2.5mm x 2.5mm x 0.62mm. Requires solder temperature profile
described in the Absolute Maximum Ratings section. UCSP reliability is integrally linked to the user’s assembly methods, circuit
board material and environment. See the UCSP Applications
Information section of this data sheet for more information.
*
Future product—contact factory for availability.
**
EP = Exposed paddle.
T = Tape and reel.
+
Denotes a lead-free package.
Selector Guide
†
The MAX3301E powers up in its lowest power state and the
MAX3302E powers up in the operational, VP/VM USB mode.
Pin Configurations appear at end of data sheet.
I2C ADDRESSES FOR
†
PARTPOWER-UP STATE
Shutdown (sdwn = 1,
MAX3301E
MAX3302E
bit 0 of specialfunction register 2)
Operating (sdwn = 1,
bit 0 of specialfunction register 2)
Note 1: The UCSP package is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the
device can be exposed to during board-level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is
required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referenced to GND.
V
CC
, VL.....................................................................-0.3V to +6V
TRM (regulator off or supplied by V
BUS
) ..-0.3V to (V
BUS
+ 0.3V)
TRM (regulator supplied by V
CC
)...............-0.3V to (VCC+ 0.3V)
D+, D- (transmitter tri-stated) ...................................-0.3V to +6V
D+, D- (transmitter functional)....................-0.3V to (V
CC
+ 0.3V)
V
BUS
.........................................................................-0.3V to +6V
ID_IN, SCL, SDA.......................................................-0.3V to +6V
INT, SPD, RESET, ADD, OE/INT, RCV, VP,
VM, SUS, DAT_VP, SE0_VM ......................-0.3V to (V
L
+ 0.3V)
C+.............................................................-0.3V to (V
BUS
+ 0.3V)
C-................................................................-0.3V to (V
Note 2: Parameters are 100% production tested at +25°C. Limits over temperature are guaranteed by design.
Note 3: Guaranteed by bench characterization. Limits are not production tested.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 5: C
B
is the total capacitance of one bus line in pF, tested with CB= 400pF.
Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
78A1SDAI2C-Compatible Serial Data Interface. Open-drain data input/output.
810B2SCLI2C-Compatible Serial Clock Input
1011A2OE/INT
1113A3RCV
1214B3SPD
1315A4V
1416A5SUS
MAX3301E
32-PIN TQFN
1, 4, 9, 12, 17,
25, 28
UCSP/
WLP
NAMEFUNCTION
System-Side Data Input/Output. DAT_VP is an input if OE/INT is logic 0.
DAT_VP is an output if OE/INT is logic 1. Program the function of DAT_VP
with the dat_se0 bit (bit 2 of control register 1, see Table 7).
Input Power Supply. Connect a +3V to +4.5V supply to VCC and bypass to
GND with a 1µF capacitor. The supply range enables direct powering from
CC
one Li+ battery.
—N.C.No Connection. Not internally connected.
System-Side Data Input/Output. SE0_VM is an input if OE/INT is logic 0.
SE0_VM is an output if OE/INT is logic 1. Program the function of SE0_VM
with the dat_se0 bit (bit 2 of control register 1, see Table 7).
O utp ut E nab l e. O E/INT contr ol s the i np ut or outp ut status of D AT_V P /S E 0_V M
and D + /D - . W hen O E/INT i s l og i c 0, the d evi ce i s i n tr ansm i t m od e. W hen
O E/INT i s l og i c 1, the d evi ce i s i n r ecei ve m od e. When i n susp end m od e,
O E/INT can b e p r og r am m ed to functi on as an i nter r up t outp ut that d etects the
sam e i nter r up ts as
7) enab l es and d i sab l es the i nter r up t ci r cui tr y of O E/INT. The i r q _m od e b i t ( b i t 1
of sp eci al - functi on r eg i ster 2, see Tab l e 15) p r og r am s the outp ut confi g ur ati on
of INT and O E/INT as op en- d r ai n or p ush- p ul l .
D+ and D- Differential Receiver Output. In receive mode (see Table 4), when
D+ is high and D- is low, RCV is high. In receive mode, when D+ is low and
D- is high, RCV is low. RCV is low in suspend mode.
Speed-Selector Input. Connect SPD to GND to select the low-speed data rate
(1.5Mbps). Connect SPD to V
Disable the SPD input by writing a 1 to spd_susp_ctl (bit 1 in special-function
register 1, see Table 14). The speed bit (bit 0 of control register 1, see Table
7) determines the maximum data rate of the MAX3301E/MAX3302E when the
SPD input is disabled.
System-Side Logic-Supply Input. Connect to the system’s logic-level power
supply, +1.65V to +3.6V. This sets the maximum output levels of the logic
L
outputs and the input thresholds of the logic inputs. Bypass to GND with a
0.1µF capacitor.
Active-High Suspend Input. Drive SUS low for normal USB operation. Drive
SUS high to enable suspend mode. RCV asserts low in suspend mode.
Disable the SUS input by writing a 1 to spd_susp_ctl (bit 1 in special-function
register 1, see Table 14). The suspend bit (bit 1 of control register 1, see
Table 7) determines the operating mode of the MAX3301E/MAX3302E when
the SUS input is disabled.
INT. The oe_i nt_en b i t ( b i t 5 of contr ol r eg i ster 1, see Tab l e
Figure 2. Load for Enable Time, Transmitter Propagation Delay,
and Transmitter Rise/Fall Times
PIN
MAX3302E
28-PIN TQFN
MAX3301E
32-PIN TQFN
UCSP/
WLP
1518B4INT
NAMEFUNCTION
Active-Low Interrupt Source. Program the INT output as push-pull or open-
drain with the irq_mode bit (bit 1 of special-function register 2, see Tables 15
and 16).
1619B5RESET
Active-Low Reset Input. Drive RESET low to asynchronously reset the
MAX3301E/MAX3302E.
1720C3ADDI2C-Interface Address Selection Input. (See Table 5.)
1922C4ID_IN
2023D5D-
2124E5D+
2226D4VM
ID Input. ID_IN is internally pulled up to V
ID bits 3 and 5 of the interrupt source register (see Table 10).
USB Differential Data Input/Output. Connect D- to the D- terminal of the USB
connector through a 27.4Ω ±1% series resistor.
USB Differential Data Input/Output. Connect D+ to the D+ terminal of the USB
connector through a 27.4Ω ±1% series resistor.
Single-Ended Receiver Output. VM functions as a receiver output in all
operating modes. VM duplicates D-.
USB Transceiver Regulated Output Voltage. TRM provides a regulated 3.3V
output. Bypass TRM to GND with a 1µF ceramic capacitor installed as close
to the device as possible. TRM normally derives power from V
2427E4TRM
provides power to internal circuitry and provides the pullup voltage for the
internal USB pullup resistor. Do not use TRM to power external circuitry. The
reg_sel bit (bit 3 of special-function register 2, see Table 15 and Table 16)
controls the TRM power source with software.
2630D3VP
Single-Ended Receiver Output. VP functions as a receiver output in all
operating modes. VP duplicates D+.
USB Bus Power. Use V
2731E2V
to power the internal linear regulator. Bits 5 to 7 of control register 2 (see
BUS
Table 8) control the charging and discharging functions of V