MAXIM MAX3109 Technical data
19-5806; Rev 1; 5/12
Dual Serial UART with 128-Word FIFOs
General Description
The MAX3109 advanced dual universal asynchronous
receiver-transmitter (UART) has 128 words of receive
and transmit first-in/first-out (FIFO) and a high-speed SPI
or I2C controller interface. The 2x and 4x rate modes
allow a maximum of 24Mbps data rates. A phase-locked
loop (PLL) and the fractional baud-rate generators allow
a high degree of flexibility in baud-rate programming and
reference clock selection.
Independent logic-level translation on the transceiver
and controller interfaces allows ease of interfacing to
microcontrollers, FPGAs, and transceivers that are powered by differing supply voltages. Automatic hardware
and software flow control with selectable FIFO interrupt
triggering offloads low-level activity from the host controller. Automatic half-duplex transceiver control with programmable setup and hold times allow the MAX3109 to
be used in high-speed applications such as PROFIBUSDP. The 128-word FIFOs have advanced FIFO control,
reducing host processor data flow management.
The MAX3109 is available in a 32-pin TQFN (5mm x
5mm) package and is specified over the -40°C to +85°C
extended temperature range.
Applications
Handheld Devices
Power Meters
Programmable Logic
Controllers (PLCs)
Medical Systems
Automotive Infotainment
Systems
Point-of-Sales Systems
HVAC or Building Control
Functional Diagram
V
L
V
CC
Features
S 24Mbps (max) Baud Rate
S Integrated PLL and Divider
S 1.71V to 3.6V Supply Range
S High-Resolution Programmable Baud Rate
S SPI Up to 26MHz Clock Rate
S Fast Mode Plus I2C Up to 1MHz
S Automatic RTS_ and CTS_ Flow Control
S Automatic XON/XOFF Software Flow Control
S Special Character Detection
S 9-Bit Multidrop Mode Data Filtering
S SIR- and MIR-Compliant IrDASM Encoder/Decoder
S Flexible Logic Levels on the Controller and
Transceiver Interfaces
S Line Noise Indication
S 1FA Shutdown Current
S Two Timers Routed to GPIOs
S 8 Flexible GPIOs with 20mA Drive Capability
S Register Compatible with MAX3107, MAX3108,
MAX14830
S Small TQFN (5mm x 5mm) Package
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX3109ETJ+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
V
18
-40NC to +85NC
V
EXT
32 TQFN-EP*
MAX3109
LDOEN
SPI/I2C
MOSI/A1
MISO/SDA
CS/A0
SCLK/SCL
RST
XOUT
LOGIC-LEVEL
TRANSLATION
IRQ
XIN
CRYSTAL
OSCILLATOR
LDO
SPI
AND
2
C
I
INTERFACE
DIVIDER
REGISTERS
AND
CONTROL
PLL
TRANSMITTER
SYNC
MAX3109
FRACTIONAL
BAUD-RATE
GENERATOR
2
UART0
LOGIC-LEVEL
TRANSLATION
UART1
2
DGNDAGND
TX0
RX0
CTS0
RTS0
GPIO0
GPIO1
GPIO2
GPIO3
TX1
RX1
CTS1
RTS1
GPIO4
GPIO5
GPIO6
GPIO7
IrDA is a service mark of Infrared Data Association Corporation.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual Serial UART with 128-Word FIFOs
TABLE OF CONTENTS
Absolute Maximum Ratings ...................................................................... 7
Package Thermal Characteristics.................................................................. 7
DC Electrical Characteristics .....................................................................7
AC Electrical Characteristics .................................................................... 10
Timing Diagrams ............................................................................. 12
MAX3109
Typical Operating Characteristics ................................................................ 13
Pin Configuration ............................................................................. 14
Pin Description ............................................................................... 14
Detailed Description........................................................................... 16
Receive and Transmit FIFOs...................................................................16
Transmitter Operation ........................................................................17
Receiver Operation ..........................................................................17
Line Noise Indication.........................................................................18
Clock Selection .............................................................................19
Crystal Oscillator .........................................................................19
External Clock Source .....................................................................19
PLL and Predivider ..........................................................................19
Fractional Baud-Rate Generators ...............................................................19
2x and 4x Rate Modes .......................................................................20
Low-Frequency Timer ........................................................................20
UART Clock to GPIO.........................................................................21
Multidrop Mode .............................................................................21
Auto Data Filtering in Multidrop Mode ...........................................................21
Auto Transceiver Direction Control ..............................................................21
Transmitter Triggering and Synchronization .......................................................21
Transmitter Synchronization .................................................................22
Intrachip and Interchip Synchronization........................................................22
Delayed Triggering........................................................................22
Trigger Accuracy .........................................................................22
Synchronization Accuracy ..................................................................23
Auto Transmitter Disable ...................................................................24
Echo Suppression ...........................................................................24
Auto Hardware Flow Control ...................................................................24
AutoRTS Control..........................................................................24
AutoCTS Control..........................................................................25
Auto Software (XON/XOFF) Flow Control .........................................................25
Receiver Flow Control .....................................................................25
Transmitter Flow Control....................................................................26
2 ______________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
TABLE OF CONTENTS (continued)
FIFO Interrupt Triggering......................................................................26
Low-Power Standby Modes ...................................................................26
Forced-Sleep Mode .......................................................................26
Auto-Sleep Mode .........................................................................26
Multiple UARTs in Sleep Mode ..............................................................26
Shutdown Mode ..........................................................................27
Power-Up and IRQ ..........................................................................27
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupt Enabling.........................................................................27
Interrupt Clearing .........................................................................27
Register Map ................................................................................28
Detailed Register Descriptions................................................................... 29
Serial Controller Interface....................................................................... 57
SPI Interface ...............................................................................57
SPI Single-Cycle Access ...................................................................57
SPI Burst Access .........................................................................58
Fast Read Cycle..........................................................................58
I2C Interface ...............................................................................58
START, STOP, and Repeated START Conditions.................................................58
Slave Address ...........................................................................59
Bit Transfer ..............................................................................59
Single-Byte Write .........................................................................60
Burst Write ..............................................................................60
Single-Byte Read .........................................................................61
Burst Read ..............................................................................61
Acknowledge Bits ........................................................................62
Applications Information ........................................................................ 62
Startup and Initialization ......................................................................62
Low-Power Operation ........................................................................63
Interrupts and Polling ........................................................................63
Logic-Level Translation .......................................................................63
Power-Supply Sequencing ....................................................................64
Connector Sharing ..........................................................................64
RS-232 5x3 Application ......................................................................64
Typical Application Circuit ......................................................................65
Chip Information ..............................................................................65
Package Information........................................................................... 65
Revision History ..............................................................................66
MAX3109
_______________________________________________________________________________________ 3
Dual Serial UART with 128-Word FIFOs
LIST OF FIGURES
Figure 1. I2C Timing Diagram.................................................................... 12
Figure 2. SPI Timing Diagram ................................................................... 12
Figure 3. Transmit FIFO Signals .................................................................. 17
Figure 4. Receive Data Format................................................................... 17
Figure 5. Receive FIFO ........................................................................ 18
MAX3109
Figure 6. Midbit Sampling ...................................................................... 18
Figure 7. Clock Selection Diagram ................................................................ 19
Figure 8. 2x and 4x Baud Rates.................................................................. 20
Figure 9. GPIO_ Clock Pulse Generator............................................................ 20
Figure 10. Auto Transceiver Direction Control .......................................................22
Figure 11. Setup and Hold Times in Auto Transceiver Direction Control ................................... 22
Figure 12. Single Transmitter Trigger Accuracy ...................................................... 23
Figure 13. Multiple Transmitter Synchronization Accuracy.............................................. 23
Figure 14. Half-Duplex with Echo Suppression ...................................................... 24
Figure 15. Echo Suppression Timing .............................................................. 25
Figure 16. Simplified Interrupt Structure............................................................ 27
Figure 17. PLL Signal Path ......................................................................49
Figure 18. SPI Write Cycle ...................................................................... 57
Figure 19. SPI Ready Cycle ..................................................................... 57
Figure 20. SPI Fast Read Cycle .................................................................. 58
Figure 21. I2C START, STOP, and Repeated START Conditions ......................................... 59
Figure 22. Write Byte Sequence.................................................................. 60
Figure 23. Burst Write Sequence ................................................................. 60
Figure 24. Read Byte Sequence ................................................................. 61
Figure 25. Burst Read Sequence................................................................. 61
Figure 26. Acknowledge ....................................................................... 62
Figure 27. Startup and Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 28. Logic-Level Translation ................................................................ 63
Figure 29. Connector Sharing with a USB Transceiver ................................................ 64
Figure 30. RS-232 Application ................................................................... 64
Figure 31. RS-485 Half-Duplex Application ......................................................... 65
4 ______________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
LIST OF TABLES
Table 1. StopBits Truth Table .................................................................... 40
Table 2. Lengthx Truth Table ....................................................................40
Table 3. SwFlow[3:0] Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 4. PLLFactorx Selection Guide.............................................................. 49
Table 5. GloblComnd Command Descriptions ......................................................53
Table 6. Extended Mode Addressing (SPI Only) ..................................................... 53
Table 7. SPI Command Byte Configuration ......................................................... 57
Table 8. I2C Address Map ...................................................................... 59
LIST OF REGISTERS
Receive Hold Register (RHR).................................................................... 29
Transmit Hold Register (THR)....................................................................29
IRQ Enable Register (IRQEn) .................................................................... 30
Interrupt Status Register (ISR) ................................................................... 31
Line Status Interrupt Enable Register (LSRIntEn)..................................................... 32
Line Status Register (LSR) ...................................................................... 33
Special Character Interrupt Enable Register (SpclChrIntEn) ............................................ 34
Special Character Interrupt Register (SpclCharInt) ...................................................35
STS Interrupt Enable Register (STSIntEn) .......................................................... 36
Status Interrupt Register (STSInt) ................................................................. 37
MODE1 Register.............................................................................. 38
MODE2 Register .............................................................................39
Line Control Register (LCR) .....................................................................40
Receiver Timeout Register (RxTimeOut) ........................................................... 41
HDplxDelay Register .......................................................................... 41
IrDA Register ................................................................................ 42
Flow Level Register (FlowLvl)....................................................................42
FIFO Interrupt Trigger Level Register (FIFOTrgLvl) ................................................... 43
Transmit FIFO Level Register (TxFIFOLvl) ..........................................................43
Receive FIFO Level Register (RxFIFOLvl) ..........................................................43
Flow Control Register (FlowCtrl).................................................................. 44
XON1 Register ............................................................................... 45
XON2 Register ............................................................................... 46
XOFF1 Register .............................................................................. 46
XOFF2 Register .............................................................................. 47
GPIO Configuration Register (GPIOConfg) ......................................................... 47
MAX3109
_______________________________________________________________________________________ 5
Dual Serial UART with 128-Word FIFOs
LIST OF REGISTERS (continued)
GPIO Data Register (GPIOData) .................................................................48
PLL Configuration Register (PLLConfig) ........................................................... 49
Baud-Rate Generator Configuration Register (BRGConfig) ............................................. 50
Baud-Rate Generator LSB Divisor Register (DIVLSB) ................................................. 50
Baud-Rate Generator MSB Divisor Register (DIVMSB) ................................................ 51
MAX3109
Clock Source Register (CLKSource) .............................................................. 51
Global IRQ Register (GlobalIRQ) ................................................................. 52
Global Command Register (GloblComnd) .......................................................... 53
Transmitter Synchronization Register (TxSynch) .....................................................54
Synchronization Delay Register 1 (SynchDelay1) .................................................... 55
Synchronization Delay Register 2 (SynchDelay2) .................................................... 55
Timer Register 1 (TIMER1) ......................................................................56
Timer Register 2 (TIMER2) ...................................................................... 56
Revision Identification Register (RevID) ............................................................56
6 ______________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to AGND.)
VL, VCC, V
XOUT ........................................................ -0.3V to (VCC + 0.3V)
V
18 ......................
RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL,
MISO/SDA, LDOEN, SPI/I2C .................... -0.3V to (VL + 0.3V)
TX_, RX_, CTS_, GPIO_ ........................... -0.3V to (V
DGND ................................................................... -0.3V to +0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
, XIN ............................................... -0.3V to +4.0V
EXT
-0.3V to the lesser of (VCC + 0.3V) and 2.0V
EXT
+ 0.3V)
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (BJA) ...........47NC/W
Junction-to-Case Thermal Resistance (BJC) ...............1.7NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital Interface Supply Voltage V
Analog Supply Voltage V
UART Interface Logic Supply
Voltage
Logic Supply Voltage V
CURRENT CONSUMPTION
VCC Supply Current I
V18 Input Power-Supply Current
in Shutdown Mode
VCC + VL + VA Shutdown Supply
Current
= 2.5V, TA = +25NC.) (Notes 2, 3)
EXT
V
I
18SHDN
I
SHDN
= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at
EXT
L
CC
EXT
CC
Internal PLL disabled and bypassed 1.71 3.6
Internal PLL enabled 2.35 3.6
18
1.8MHz crystal oscillator active, PLL
disabled, SPI/I2C interface idle, UART
interfaces idle, LDOEN = high
Baud rate = 1Mbps, 20MHz external clock,
SPI/I2C interface idle, PLL disabled, all
UARTs in loopback mode, LDOEN = low
RST = low, all inputs and outputs are idle
RST = low, MISO, SCLK, MOSI, SPI_I2C,
CS, LDOEN = 0/VL, CTSB0/1 = 0/V
CTSB0/1 = 0/V
Continuous Power Dissipation (TA = +70NC)
TQFN (derate 34.5mW/NC above +70NC) .............. 2758.6mW
Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
1.71 3.6 V
1.71 3.6 V
1.65 1.95 V
500
500
100
0 1
EXT
EXT
,
V
FA
FA
FA
MAX3109
_______________________________________________________________________________________ 7
Dual Serial UART with 128-Word FIFOs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V
= 2.5V, TA = +25NC.) (Notes 2, 3)
EXT
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V18 Input Power-Supply Current I
MAX3109
SCLK/SCL, MISO/SDA
MISO/SDA Output Logic-Low
Voltage in I2C Mode
MISO/SDA Output Low Voltage
in SPI Mode
MISO/SDA Output High Voltage
in SPI Mode
Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Hysteresis V
Input Leakage Current I
Input Capacitance C
SPI/I2C, CS/A0, MOSI/A1 INPUTS
Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Hysteresis V
Input Leakage Current I
Input Capacitance C
IRQ OUTPUT (OPEN DRAIN)
Output Logic-Low Voltage V
Output Leakage Current I
LDOEN AND RST INPUTS
Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Hysteresis V
Input Leakage Current I
V
V
V
= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at
EXT
Baud rate = 1Mbps, 20MHz external clock,
18
PLL disabled, UART in loopback mode,
LDOEN = low (Note 4)
Sink current = 3mA, VL > 2V 0.4
OLI2C
OLSPI
OHSPI
HYST
HYST
OL
OL
HYST
Sink current = 3mA, VL < 2V
Sink current = 2mA 0.4 V
Source current = 2mA
SPI and I2C mode
IL
SPI and I2C mode
IH
VL -
0.4
0.7 x
V
SPI and I2C mode
VIN = 0 to VL, SPI and I2C mode -1 +1
IL
SPI and I2C mode 5 pF
IN
SPI and I2C mode
IL
SPI and I2C mode
IH
0.7 x
V
SPI and I2C mode 50 mV
VIN = 0 to VL, SPI and I2C mode -1 +1
IL
SPI and I2C mode 5 pF
IN
Sink current = 2mA 0.4 V
V
= 0 to VL, IRQ is not asserted
IRQ
IL
IH
IL
VIN = 0 to V
L
0.7 x
V
0.2 x
V
0.3 x
V
L
0.05 x
V
L
0.3 x
V
L
-1 +1
0.3 x
V
L
50 mV
-1 +1
4 mA
V
L
V
L
V
V
V
FA
L
V
V
FA
FA
L
V
V
FA
8 ______________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V
= 2.5V, TA = +25NC.) (Notes 2, 3)
EXT
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UART INTERFACE
RTS_, TX_ OUTPUTS
Output Logic-Low Voltage V
Output Logic-High Voltage V
Input Leakage Current I
Input Capacitance C
CTS_, RX_ INPUTS
Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Hysteresis V
CTS_ Input Leakage Current
RX_ Pullup Current I
Input Capacitance C
GPIO_ INPUTS/OUTPUTS
Output Logic-Low Voltage V
Output Logic-High Voltage V
Input Logic-Low Voltage V
Input Logic-High Voltage V
Pulldown Current I
XIN
Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Capacitance C
XOUT
Input Capacitance C
= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at
EXT
OL
OH
HYST
I
PU
Sink current = 2mA 0.4 V
Source current = 2mA
Output is three-stated, V
IL
High-Z mode 5 pF
IN
IL
IH
V
IL
IN
= 0 to V
CTS_
V
= 0V -7.5 -5.5 -3.5
RX_
EXT
Sink current = 20mA, push-pull or open-
OL
OH
IL
IH
PD
IL
IH
XIN
XOUT
drain output type, V
Sink current = 20mA, push-pull or opendrain output type, V
Source current = 5mA, push-pull output
type
GPIO_ is configured as an input 0.4 V
GPIO_ is configured as an input
V
= V
GPIO_
, GPIO_ is configured as an
EXT
input
EXT
EXT
> 2.3V
< 2.3V
RTS
= 0 to V
EXT
0.7 x
V
EXT
-1 +1
0.3 x
V
EXT
0.7 x
V
EXT
50 mV
-1 +1
5 pF
0.45
0.55
V
-
EXT
0.4
2/3 x
V
EXT
3.5 5.5 7.5
0.6 V
1.2 V
16 pF
16 pF
MAX3109
V
FA
V
V
FA
FA
V
V
V
FA
_______________________________________________________________________________________ 9
Dual Serial UART with 128-Word FIFOs
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
External Cystal Frequency f
External Clock Frequency f
External Clock Duty Cycle (Note 5) 45 55 %
MAX3109
Baud-Rate Generator Clock
Input Frequency
I2C BUS: TIMING CHARACTERISTICS (Figure 1)
SCL Clock Frequency f
Bus Free Time Between a STOP
and START Condition
Hold Time for START Condition
and Repeated START Condition
Low Period of the SCL Clock t
High Period of the SCL Clock t
Data Hold Time
Data Setup Time t
Setup Time for Repeated START
Condition
Rise Time of Incoming SDA and
SCL Signals
Fall Time of SDA and SCL
Signals
= 2.5V, TA = +25NC.) (Notes 2, 3)
EXT
XOSC
t
HD:STA
t
HD:DAT
SU:DAT
t
SU:STA
= 1.71V to 3.6V TA = -40NC to +85NC, unless otherwise noted. Typical values are at
EXT
1 4 MHz
CLK
f
REF
SCL
t
BUF
LOW
HIGH
t
R
t
F
(Note 5) 96 MHz
Standard mode 100
Fast mode plus 1000
Standard mode 4.7
Fast mode 1.3
Fast mode plus 0.5
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
Standard mode 4.7
Fast mode 1.3
Fast mode plus 0.5
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
Standard mode 0 0.9
Fast mode 0 0.9
Fast mode plus 0
Standard mode 250
Fast mode plus 50
Standard mode 4.7
Fast mode 0.2
Fast mode plus 0.26
Standard mode (0.3 x VL to 0.7 x VL)
(Note 6)
Fast mode (0.3 x VL to 0.7 x VL) (Note 6)
Fast mode plus 120
Standard mode (0.3 x VL to 0.7 x VL)
(Note 6)
Fast mode (0.3 x VL to 0.7 x VL) (Note 6)
Fast mode plus 120
0.5 35 MHz
20 +
0.1C
20 +
0.1C
20 +
0.1C
20 +
0.1C
B
B
B
B
1000
1000
300
300
kHzFast mode 400
Fs
Fs
Fs
Fs
Fs
nsFast mode 100
Fs
ns
ns
10 _____________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for STOP Condition t
Capacitive Load for SDA and
SCL
SCL and SDA I/O Capacitance C
Pulse Width of Spike Suppressed t
SPI BUS: TIMING CHARACTERISTICS (Figure 2)
SCLK Clock Period tCH+t
SCLK Pulse Width High t
SCLK Pulse Width Low t
CS Fall to SCLK Rise Time
MOSI Hold Time t
MOSI Setup Time t
Output Data Propagation Delay t
MISO Rise and Fall Times t
CS Hold Time
Note 2: All units are production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Currents entering the IC are negative and currents exiting the IC are positive.
Note 4: When V18 is powered by an external voltage supply, it must have current capability above or equal to I18.
Note 5: Guaranteed by design; not production tested.
Note 6: CB is the total capacitance of either the clock or data line of the synchronous bus in pF.
= 2.5V, TA = +25NC.) (Notes 2, 3)
EXT
SU:STO
t
t
= 1.71V to 3.6V TA = -40NC to +85NC, unless otherwise noted. Typical values are at
EXT
Standard mode 4.7
Fast mode 0.6
Fast mode plus 0.26
Standard mode (Note 5) 400
C
B
Fast mode plus (Note 5) 550
(Note 5) 10 pF
I/O
SP
CL
CH
CL
CSS
DH
DS
DO
FT
CSH
38.4 ns
16 ns
16 ns
0 ns
3 ns
5 ns
30 ns
MAX3109
Fs
pFFast mode (Note 5) 400
50 ns
20 ns
10 ns
______________________________________________________________________________________ 11
Dual Serial UART with 128-Word FIFOs
Timing Diagrams
START CONDITION
(S)
SDA
MAX3109
t
HD:STA
SCL
Figure 1. I2C Timing Diagram
CS
SCLK
t
CSH
t
CSS
t
HD:DAT
t
t
DS
t
SU:DAT
HIGH
t
DH
REPEATED START CONDITION
t
SU:STA
t
R
t
CL
t
F
t
CH
(Sr)
t
R
t
HD:STA
t
LOW
t
SU:STO
t
F
STOP CONDITION
t
CSH
(P)
t
BUF
START CONDITION
(S)
MOSI
t
DO
MISO
t
FT
Figure 2. SPI Timing Diagram
12 _____________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
04
04
Typical Operating Characteristics
(VCC = 2.5V, VL = 2.5V, V
= 2.5V, V
EXT
= VL, UART1 in sleep mode, TA = +25°C unless otherwise noted.)
LDOEN
MAX3109
SINK CURRENT (OPEN DRAIN)
vs. GPIO_ OUTPUT LOW VOLTAGE
180
160
140
120
100
(mA)
SINK
80
I
60
40
20
0
V
EXT
V
EXT
= 1.71V
VOL (V)
V
EXT
= 2.5V
MAX3109 toc01
= 3.6V
321
TRANSMITTER SYNCHRONIZATION
10µs/div
(mA)
I
MAX3109 toc03
I2C MODE
SOURCE CURRENT (PUSH-PULL)
vs. GPIO_OUTPUT HIGH VOLTAGE
70
60
50
V
= 2.5V
EXT
40
30
V
= 1.8V
EXT
SOURCE
20
10
0
V
SCL
2V/div
0V
V
TX0
2V/div
115.2kBaud
0V
V
TX1
2V/div
460.8kBaud
0V
V
VOH (V)
EXT
= 3.3V
MAX3109 toc02
321
______________________________________________________________________________________ 13
Dual Serial UART with 128-Word FIFOs
Pin Configuration
TOP VIEW
RTS1
GPIO2
RTS0
RX1
21
MAX3109
4567
GPIO7
CS/A0
SCLK/SCL
RX0
*EP
MOSI/A1
TX0
IRQ
TX1
17
16
CTS1
CTS0
15
14
GPIO5
GPIO1
13
12
GPIO4
GPIO0
11
10
DGND
9
SPI/I2C
8
L
V
MAX3109
V
EXT
XIN
XOUT
GPIO6
AGND
LDOEN
V
V
GPIO3
2324 22 20 19 18
25
26
27
28
29
30
31
18
CC
32
+
12
RST
MISO/SDA
3
TQFN
(5mm × 5mm)
*CONNECT EP TO AGND.
Pin Description
PIN NAME FUNCTION
Active-Low Reset Input. Drive RST low to force all of the UARTs into hardware reset mode. Driving RST
1
2 MISO/SDA
3 SCLK/SCL
4 GPIO7
RST
low also enables low-power shutdown mode. When RST is low, the internal V18 LDO is switched off,
even if the LDOEN input is kept high.
Serial-Data Output. When SPI/I2C is high, MISO/SDA functions as the SPI master input-slave output
(MISO). When SPI/I2C is low, MISO/SDA functions as the SDA, I2C serial-data input/output. MISO/SDA is
high impedance when RST is driven low or when the externally supplied V18 is powered off.
Serial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK SPI serial-clock input (up to
26 MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I2C serial-clock input (up to 1MHz in
fast mode plus).
General-Purpose Input/Output 7. GPIO7 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO7 has a weak pulldown resistor to DGND when
configured as an input.
Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI
5
CS/A0
active-low chip-select. When SPI/I2C is low, CS/A0 functions as the A0 I2C device address programming
input. Connect CS/A0 to DGND, VL, SCL, or SDA when SPI/I2C is low.
Serial-Data Input and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the SPI master
6 MOSI/A1
output-slave input (MOSI). When SPI/I2C is low, MOSI/A1 functions as the A1 I2C device address
programming input. Connect MOSI/A1 to DGND, VL, SCL, or SDA when SPI/I2C is low.
7
IRQ
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending. IRQ is high
impedance when RST is driven low.
14 _____________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
Pin Description (continued)
PIN NAME FUNCTION
8 V
9
10 DGND Digital Ground
11 GPIO0
12 GPIO4
13 GPIO1
14 GPIO5
15
16
17 TX1
18 TX0
19 RX0 Serial Receiving Data Input for UART0. RX0 has an internal weak pullup resistor to V
20 RX1 Serial Receiving Data Input for UART1. RX1 has an internal weak pullup resistor to V
21
22
23 GPIO2
24 GPIO3
25 V
26 XIN
L
SPI/I2C SPI Selector Input or Active-Low I2C. Drive SPI/I2C low to enable I2C. Drive SPI/I2C high to enable SPI.
CTS0 Active-Low Clear-to-Send Input for UART0. CTS0 is a flow-control status input.
CTS1 Active-Low Clear-to-Send Input for UART1. CTS1 is a flow-control status input.
RTS0
RTS1
EXT
Digital Interface Power Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/A1, CS/A0,
SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to DGND.
General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO0 has a weak pulldown resistor to DGND when
configured as an input. GPIO0 is the reference clock output when bit 7 of the TxSynch register is set to
high (see the UART Clock to GPIO section for more information).
General-Purpose Input/Output 4. GPIO4 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO4 has a weak pulldown resistor to DGND when
configured as an input. GPIO4 is the reference clock output when bit 7 of the TxSynch register is set to
high (see the UART Clock to GPIO section for more information).
General-Purpose Input/Output 1. GPIO1 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO1 has a weak pulldown resistor to DGND when
configured as an input. GPIO1 is the TIMER output when bit 7 of the TIMER2 register is set high.
General-Purpose Input/Output 5. GPIO5 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO5 has a weak pulldown resistor to DGND when
configured as an input. GPIO5 is the TIMER output when bit 7 of the TIMER2 register is set high.
Serial Transmitting Data Output for UART1. TX1 is logic-high when RST is low or when the externally
supplied V18 is not powered.
Serial Transmitting Data Output for UART0. TX0 is logic-high when RST is low or when the externally
supplied V18 is not powered.
.
EXT
.
EXT
Active-Low Request-to-Send Output for UART0. RTS0 can be set high or low by programming the LCR
register. RTS0 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set high. RTS0 is logic-high when RST is low or when the externally supplied V18 is not powered.
Active-Low Request-to-Send Output for UART1. RTS1 can be set high or low by programming the LCR
register. RTS1 is the UART system clock/fractional divider output when bit 7 of the CLKSource register is
set high. RTS1 is logic-high when RST is low or when the externally supplied V18 is not powered.
General-Purpose Input/Output 2. GPIO2 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO2 has a weak pulldown resistor to DGND when
configured as an input.
General-Purpose Input/Output 3. GPIO3 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO3 has a weak pulldown resistor to DGND when
configured as an input.
Transceiver Interface Power Supply. V
CTS_, and GPIO_. Bypass V
Crystal/Clock Input. When using an external crystal, connect one end of the crystal to XIN and the other
end to XOUT. When using an external clock source, drive XIN with the single-ended external clock.
with a 0.1FF ceramic capacitor to DGND.
EXT
powers the internal logic-level translators for RX_, TX_, RTS_,
EXT
MAX3109
______________________________________________________________________________________ 15
Dual Serial UART with 128-Word FIFOs
Pin Description (continued)
PIN NAME FUNCTION
27 XOUT
28 GPIO6
MAX3109
29 AGND Analog Ground
30 LDOEN
31 V
32 V
— EP Exposed Pad. Connect EP to AGND. Do not use EP as the main AGND connection.
18
CC
Crystal Output. When using an external crystal, connect one end of the crystal to XOUT and the other
end to XIN. When using an external clock source, leave XOUT unconnected.
General-Purpose Input/Output 6. GPIO6 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO6 has a weak pulldown resistor to DGND when
configured as an input.
LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN low to disable the
internal LDO. Supply V
Internal 1.8V LDO Output and 1.8V Power-Supply Input. Bypass V18 with a 0.1FF ceramic capacitor to
DGND.
Analog Power Supply. VCC powers the PLL and internal LDO. Bypass VCC with a 0.1FF ceramic
capacitor to AGND.
with an external voltage source when LDOEN is low.
18
Detailed Description
The MAX3109 dual universal asynchronous receivertransmitter (UART) bridges an SPI/MICROWIREK or
I2C microprocessor bus to an asynchronous serial-data
communication link, such as RS-485, RS-232, or IrDA.
The MAX3109 is configured through 8-bit registers,
which are accessed through the SPI or I2C interface.
These registers are organized by related function as
shown in the Register Map section.
The host controller loads data into the Transmit Hold register (THR) through the SPI or I2C interface. This data is
automatically pushed into the transmit FIFOs, formatted,
and sent out at TX_. The MAX3109 adds START, STOP,
and parity bits to the data before transmitting the data
out at the selected baud rate. The clock configuration
registers determine the baud rates, clock source selection, clock frequency prescaling, and fractional baudrate generator settings for each UART.
The MAX3109 receivers detect a START bit as a highto-low transition on RX_. An internal clock samples this
data at 16 times the baud rate. The received data is
automatically placed in the receive FIFOs and can then
be read out by the host controller through the Receiver
Hold register (RHR).
The device features two identical UARTs that are completely independent except for the input clock. Text in
this data sheet references individual UART operation,
unless otherwise noted.
The MAX3109’s register set is compatible with the MAX3107.
Refer to Application Note 4938: Differences Between
Maxim's Advanced UART Devices for information on how
to transfer firmware from the MAX3107 to the MAX3109.
Receive and Transmit FIFOs
Each UART’s receiver and transmitter has a 128-worddeep FIFOs, reducing the number of intervals that the
host processor needs to dedicate for high-speed, highvolume data transfer to and from the device. As the data
rates of the asynchronous RX_/TX_ interfaces increase
and get closer to those of the host controller’s SPI/I2C
data rates, UART management and flow-control can
make up a significant portion of the host’s activity. By
increasing FIFO size, the host is interrupted less often
and can use data block transfers to and from the FIFOs.
FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels
have been reached. The transmitter and receiver trigger
levels are programmed through the FIFOTrgLvl register
with a resolution of eight FIFO locations. The receive
FIFO trigger signals to the host either that the receive
FIFO has a defined number of words waiting to be read
out in a block or that a known number of vacant FIFO
locations are available and ready to be filled. The transmit FIFO trigger generates an interrupt when the transmit
FIFO fill level is above the programmed trigger level. The
host then knows to throttle data writing to the transmit
FIFO through THR.
The host can read out the number of words present in each of the FIFOs through the TxFIFOLvl and
RxFIFOLvl registers.
MICROWIRE is a trademark of National Semiconductor Corp.
16 _____________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
The contents of the TxFIFO and RxFIFO are both cleared
when the MODE2[1]: FIFORst bit is set high
.Transmitter Operation
Figure 3 shows the structure of the transmitter with the
TxFIFO. The transmit FIFO can hold up to 128 words of
data that are added by writing to the THR register.
The current number of words in the TxFIFO can be read
out by the host controller through the TxFIFOLvl register. The transmit FIFO fill level can be programmed to
generate an interrupt when greater than or equal to a
programmed number of words are present in the TxFIFO
through the FIFOTrgLvl register. This TxFIFO interrupt
2
TRIGGER
LEVEL
EMPTY
C INTERFACE
CURRENT FILL LEVEL
THR
FIFOTrgLvl[3:0]
TRANSMIT FIFO
TRANSMITTER TX_
128
3
2
1
DATA FROM SPI/I
ISR[4]
TxFIFOLvl
ISR[5]
Figure 3. Transmit FIFO Signals
trigger level is selectable by the FIFOTrgLvl[3:0] bits.
MAX3109
When the transmit FIFO fill level increases to at least the
programmed trigger level, an interrupt is generated in
ISR[4]: TxTrigInt.
An interrupt is generated in ISR[5]: TFifoEmptyInt when
the transmit FIFO is empty. ISR[5] goes high when
the transmitter starts transmitting the last word in the
TxFIFO. An additional interrupt is generated in STSInt[7]:
TxEmptyInt when the transmitter completes transmitting
the last word.
To halt transmission, set the MODE1[1]: TxDisabl bit
high. After TxDisabl is set, the transmitter completes the
transmission of the current character and then ceases
transmission. Turn the transmitter off prior to enabling
auto software flow control and AutoRTS flow control.
The TX_ output logic can be inverted through the
IrDA[5]: TxInv bit. Unless otherwise noted, all transmitter
logic described in this data sheet assumes that TxInv is
set low.
Receiver Operation
The receiver expects the format of the data at RX_ to
be as shown in Figure 4. The quiescent logic state is
logic-high and the first bit (the START bit) is logic-low
(RxInv = 0). The 8-bit data word expected to be received
LSB first. The receiver samples the data near the midbit
instant (Figure 4). The received words and their associated errors are deposited into the receive FIFO. Errors
and status information are stored for every received word
(Figure 5). The host reads the data out of the receive
FIFO by reading RHR, which comes out oldest data first.
After a word is read out of RHR, LSR contains the status
information for that word.
RECEIVED DATA
MIDDATA
SAMPLING
NOTE: RxInv = 0.
Figure 4. Receive Data Format
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP
______________________________________________________________________________________ 17
LSB
MSB
Dual Serial UART with 128-Word FIFOs
The following three error conditions are checked for each
received word: parity error, frame error, and noise on the
line. Parity errors are detected by calculating either even
or odd parity of the received word as programmed by
register settings. Framing errors are detected when the
received data frame does not match the expected frame
format in length. Line noise is detected by checking the
logical congruency of the three samples taken of each
bit (Figure 6).
The receiver can be turned off by setting the MODE1[0]:
RxDisabl bit high. After this bit is set high, the MAX3109
turns the receiver off immediately following the current
word and does not receive any further data.
The RX_ input logic can be inverted by setting the
IrDA[4]: RxInv bit high. Unless otherwise noted, all
receiver logic described in this data sheet assumes that
RxInv is set low.
When operating in standard or 2x (i.e., not 4x) rate mode,
the MAX3109 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples per received bit have differing logic
levels, then noise on the transmission line has affected
the received data and it is considered to be noisy. This
noise indication is reflected in the LSR[5]: RxNoise bit for
each received byte. Parity errors are another indication
of noise, but are not as sensitive.
ISR[3]
ISR[6]
OVERRUN
TRIGGER
TIMEOUT
LSR[1]
MAX3109
CURRENT FILL LEVEL
I2C/SPI INTERFACE
LSR[0]
LSR[5:2]
Figure 5. Receive FIFO
EMPTY
ERRORS
RECEIVER RX_
WORD ERROR 128
FIFOTrgLvl[7:4]
RECEIVE FIFO
RxFIFOLvl
RHR
RECEIVED
DATA
4
3
2
1
Line Noise Indication
ONE BIT PERIOD
RX_
BAUD
BLOCK
A
1
23456789
10 11
MAJORITY
CENTER
SAMPLER
12 13 14 15 16
Figure 6. Midbit Sampling
18 _____________________________________________________________________________________
Dual Serial UART with 128-Word FIFOs
MAX3109
CrystalEn
XOUT
XIN
Figure 7. Clock Selection Diagram
CRYSTAL
OSCILLATOR
Clock Selection
The MAX3109 can be clocked by either an external
crystal or an external clock source. Figure 7 shows a
simplified diagram of the clock selection circuitry. When
the MAX3109 is clocked by a crystal, the STSInt[5]:
ClkReady bit indicates when the crystal oscillator has
reached steady state and the baud-rate generator is
ready for stable operation.
Each UART baud rate can be individually programmed
and both share the same reference clock input.
The baud-rate clock can be routed to the RTS_ output by
setting the CLKSource[7]: CLKtoRTS bit high. The clock
rate is 16x the baud rate in standard operating mode, 8x
the baud rate in 2x rate mode, and 4x the baud rate in 4x
rate mode. If the fractional portion of the baud-rate generator is used, the clock is not regular and exhibits jitter.
Crystal Oscillator
The MAX3109 is equipped with a crystal oscillator to provide high baud-rate accuracy and low power consumption. Set the CLKSource[1]: CrystalEn bit high to enable
and select the crystal oscillator. The on-chip crystal
oscillator has integrated load capacitances of 16pF in
both the XIN and XOUT pins. Connect only an external
crystal or ceramic oscillator between XIN and XOUT.
External Clock Source
Connect an external single-ended clock source to XIN
when not using the crystal oscillator. Leave XOUT unconnected. Set the CLKSource[1]: CrystalEn bit low to
select external clocking.
PLL and Predivider
The internal predivider and PLL allow for compatibility with
a wide range of external clock frequencies and baud rates.
The PLL can be configured to multiply the input clock
rate by a factor of 6, 48, 96, or 144 by the PLLConfig[7:6]
bits. The predivider is located between the input clock
and the PLL and allows division of the input clock by an
PLLBypass
FRACTIONAL
BAUD-RATE
GENERATOR 0
PLLDIVIDER
PLLEn
FRACTIONAL
BAUD-RATE
GENERATOR 1
integer factor between 1 and 63. This value is defined
by the PLLConfig[5:0] bits. See the PLLConfig register
description for more information. Use of the PLL requires
VCC to be higher than 2.35V.
Fractional Baud-Rate Generators
Each UART has an internal fractional baud-rate generator that provides a high degree of flexibility and high
resolution in baud-rate programming. The baud-rate
generator has a 16-bit integer divisor and a 4-bit word for
the fractional divisor. The fractional baud-rate generator
can be used either with the crystal oscillator or external
clock source.
The integer and fractional divisors are calculated by the
divisor, D:
×
f RateMode
REF
=
where f
D
is the reference frequency input to the baud-
REF
×
16 BaudRate
rate generator, RateMode is the rate mode multiplier (1x
default), BaudRate is the desired baud rate, and D is the
ideal divisor. f
must be less than 96MHz. RateMode
REF
is 1 in 1x rate mode, 2 in 2x rate mode, and 4 in 4x rate
mode.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIV = TRUNC(D)
DIV can be a maximum of 16 bits (65,535) wide and
is programmed into the two single-byte-wide registers
DIVMSB and DIVLSB. The minimum allowed value for
DIVLSB is 1.
The fractional portion of the divisor, FRACT, is a 4-bit
nibble that is programmed into BRGConfig[3:0]. The
maximum value is 15, allowing the divisor to be programmed with a resolution of 0.0625. FRACT is calculated as: FRACT = ROUND(16 x (D - DIV)).
______________________________________________________________________________________ 19
Dual Serial UART with 128-Word FIFOs
The following is an example of how to calculate the divisor. It is based on a required baud rate of 190kbaud
and a reference input frequency of 28.23MHz and 1x
(default) rate mode.
The ideal divisor is calculated as:
D = 28,230,000/(16 x 190,000) = 9.286
hence DIV = 9.
MAX3109
FRACT = ROUND(16 x 0.286) = 5
so DIVMSB = 0x00, DIVLSB = 0x09, and BRGConfig[3:0]
= 0x05.
The resulting actual baud rate can be calculated as:
×
f RateMode
REF
BR
ACTUAL
=
×
16 D
ACTUAL
For this example:
D
ACTUAL
BR
= 9 + 5/16 = 9.3125, RateMode = 1, and
ACTUAL
= 28,230,000/(16 x 9.3125) = 189463 baud.
Thus, the actual baud rate is within 0.28% of the ideal
rate.
2x and 4x Rate Modes
To support higher baud rates than possible with standard operation using 16x sampling, the MAX3109 offers
2x and 4x rate modes. In these modes, the reference
clock rate only needs to be either 8x or 4x higher than the
baud rate, respectively. In 4x rate mode, each received
bit is only sampled once at the midbit instant instead of
the usual three samples to determine the logic value of
the received bit. This reduces the ability to detect line
noise on the received data in 4x rate mode. The 2x and
4x rate modes are selectable through BRGConfig[5:4].
Note that IrDA encoding and decoding does not operate
in 2x and 4x rate modes.
When 2x rate mode is selected, the actual baud rate is
twice the rate programmed into the baud-rate generator. If 4x rate mode is enabled, the actual baud rate on
the line is quadruple that of the programmed baud rate
(Figure 8).
Low-Frequency Timer
Each UART has a general-purpose timer that can be
used to generate a low-frequency clock at a GPIO
output and can, for example, be used to drive external
LEDs. The low-frequency clock is a divided replica of the
given UART baud-rate clock. The timer for each UART
is internally routed to the respective GPIO_ output when
enabled by the TIMER2 register as follows:
U UART0: GPIO1
U UART1: GPIO5
The clock pulses at the GPIOs are generated at a rate
defined by the baud-rate generator and the timer divider
(Figure 9). The baud-rate generator clock frequency is
divided by (1024 x Timer[14:0]) to produce the GPIO_
clock, where Timer[14:0] is the 15-bit value programmed
into the TIMER1 and TIMER2 registers. The timer output
is 50% duty cycle clock.
DIVLSB
DIVMSB
FRACT
RATE
FRACTIONAL
RATE
GENERATOR
÷1024
f
REF
NOTE: IrDA DOES NOT WORK IN 2x AND 4x MODES.
Figure 8. 2x and 4x Baud Rates
DIVLSB
DIVMSB
FRACT
f
REF
Figure 9. GPIO_ Clock Pulse Generator
20 _____________________________________________________________________________________
FRACTIONAL
GENERATOR
BRGConfig[5:4]
1x, 2x, 4x RATE
MODES
÷TIMERx
GPIO_
BAUD RATE
TmrToGPIO
GPIO_
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