MAXIM MAX3108 Technical data

19-5723; Rev 1; 2/11

SPI/I2C UART with 128-Word FIFOs in WLP

General Description

The MAX3108 small form factor universal asynchronous
receiver-transmitter (UART) with 128 words each of
receive and transmit FIFOs is controlled through a serial
I2C or SPI™ controller interface. Auto-sleep and shut­down modes help reduce power consumption during
periods of inactivity. A low 500FA (max) supply current
and tiny 25-bump WLP (2.1mm x 2.1mm) package make
the MAX3108 ideal for low-power portable devices. The
MAX3108 operates from a supply voltage of 1.71V to 3.6V.

Baud rates up to 24Mbps make the MAX3108 suitable for
today’s high data rate applications. A phase-locked loop
(PLL), predivider, and fractional baud-rate generator allow
high-resolution baud-rate programming and minimize the
dependency of baud rate on reference clock frequency.

Four GPIOs can be used as inputs, outputs, or interrupt inputs.
When configured as outputs, they can be programmed to be
open-drain outputs and sink up to 20mA of current.

The MAX3108 is ideal for portable and handheld devic­es, is available in a 25-bump (2.1mm x 2.1mm) 0.4mm
pitch WLP package, and is specified over the -40NC to
+85NC extended temperature range.

Applications

Portable Communication Devices
Mobile Internet Devices
Low-Power Handheld Devices
Medical Systems
Point-of-Sale Systems

SPI is a trademark of Motorola, Inc.
IrDA is a service mark of Infrared Data Association Corporation.

Functional Diagram

Features

S 24Mbps (max) Baud Rate
S Integrated PLL and Divider
S 1.71V to 3.6V Supply Range
S High-Resolution Programmable Baud Rate
S SPI Up to 26MHz Clock Rate
S Fast Mode Plus I
S Automatic RTS and CTS Hardware Flow Control
S Automatic XON/XOFF Software Flow Control
S Special Character Detection
S 9-Bit Multidrop Mode Data Filtering
S SIR- and MIR-Compliant IrDA
S Flexible Logic Levels on the Controller and

2

C Up to 1MHz

SM

Encoder/Decoder

Transceiver Interfaces

S Four Flexible GPIOs
S Line Noise Indication
S Shutdown and Auto-Sleep Modes

S Low 35µA (max) V
S Register Compatible with the MAX3107
S Tiny, 25-Bump WLP Package (2.1mm x 2.1mm)

Shutdown Current

CC

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX3108EWA+

-40NC to +85NC

+Denotes a lead(Pb)-free/RoHS-compliant package.

25 WLP

MAX3108

LDOEN

SPI/I2C

MOSI/A1

MISO/SDA

CS/A0

SCLK/SCL

RST

IRQ

XIN

XOUT

V

CC

V

L

LDO

SPI/I2C

LOGIC-LEVEL

TRANSLATION

CRYSTAL

OSCILLATOR

DIVIDER

PLL

V

18

MAX3108

Tx AND FIFO

REGISTERS

AND

CONTROL

FRACTIONAL

BAUD-RATE
GENERATOR

DGNDAGND

FLOW

CONTROL

LOGIC-LEVEL

TRANSLATION

Rx AND FIFO

GPIO

V

EXT

TX

CTS

RTS

RX

GPIO0
GPIO1
GPIO2
GPIO3

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

SPI/I2C UART with 128-Word FIFOs in WLP

TABLE OF CONTENTS

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MAX3108

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bump Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bump Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Receive and Transmit FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Line Noise Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PLL and Predivider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Fractional Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2x and 4x Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Auto Data Filtering in Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Auto Transceiver Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Auto Hardware Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AutoRTS Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AutoCTS Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Auto Software (XON/XOFF) Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Receiver Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Transmitter Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FIFO Interrupt Triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Low-Power Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Forced-Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Auto-Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-Up and IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2 ______________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

TABLE OF CONTENTS (continued)

Interrupt Enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Interrupt Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SPI Single-Cycle Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

SPI Burst Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

START, STOP, and Repeated START Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Single-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Acknowledge Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Startup and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupts and Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Logic-Level Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Connector Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

RS-232 5x3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

MAX3108

_______________________________________________________________________________________ 3

SPI/I2C UART with 128-Word FIFOs in WLP

LIST OF FIGURES

Figure 1. I2C Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3. Transmit FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 4. Receive Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MAX3108

Figure 6. Midbit Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Clock Selection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. 2x and 4x Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Auto Transceiver Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 10. Setup and Hold times in Auto Transceiver Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. Half-Duplex with Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. Echo Suppression Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13. Simplified Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. PLL Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 15. Single-Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 16. Single-Cycle Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 17. I2C START, STOP, and Repeated START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 18. Write Byte Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 19. Burst Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 20. Read Byte Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 21. Burst Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 22. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 23. Startup and Initialization Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 24. Logic-Level Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 25. Connector Sharing with a USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 26. RS-232 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 27. RS-485 Half-Duplex Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

LIST OF TABLES

Table 1. StopBits Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 2. Lengthx Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 3. SwFlow[3:0] Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 4. PLLFactorx Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 5. I2C Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4 ______________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

LIST OF REGISTERS

Receive Hold Register (RHR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Transmit Hold Register (THR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

IRQ Enable Register (IRQEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Line Status Interrupt Enable Register (LSRIntEn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Line Status Register (LSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Special Character Interrupt Enable Register (SpclChrIntEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Special Character Interrupt Register (SpclCharInt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

STS Interrupt Enable Register (STSIntEn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Status Interrupt Register (STSInt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

MODE1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

MODE2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Line Control Register (LCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Receiver Timeout Register (RxTimeOut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

HDplxDelay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IrDA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Flow Level Register (FlowLvl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FIFO Interrupt Trigger Level Register (FIFOTrgLvl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Transmit FIFO Level Register (TxFIFOLvl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Receive FIFO Level Register (RxFIFOLvl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Flow Control Register (FlowCtrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

XON1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

XON2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

XOFF1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

XOFF2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

GPIO Configuration Register (GPIOConfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

GPIO Data Register (GPIOData) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PLL Configuration Register (PLLConfig). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Baud-Rate Generator Configuration Register (BRGConfig) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Baud-Rate Generator LSB Divisor Register (DIVLSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Baud-Rate Generator MSB Divisor Register (DIVMSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Clock Source Register (CLKSource) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

MAX3108

_______________________________________________________________________________________ 5

SPI/I2C UART with 128-Word FIFOs in WLP

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to AGND.)
VL, VCC, V

XOUT ........................................................ -0.3V to (VCC + 0.3V)

V18 ...................... -0.3V to the lesser of (VCC + 0.3V) and 2.0V

RST, IRQ, MOSI/A1, CS/A0, SCLK/SCL,

MISO/SDA, LDOEN, SPI/I2C .................... -0.3V to (VL + 0.3V)

TX, RX, RTS, CTS, GPIO_ ....................... -0.3V to (V

, XIN ...............................................-0.3V to +4.0V

EXT

EXT

+ 0.3V)

DGND ...................................................................-0.3V to +0.3V

Continuous Power Dissipation (TA = +70NC)

WLP (derate 19.2mW/NC above +70NC) ................... 1536mW

Operating Temperature Range .......................... -40NC to +85NC

Maximum Junction Temperature .....................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Soldering Temperature (reflow) ......................................+260NC

MAX3108

PACKAGE THERMAL CHARACTERISTICS

WLP

Junction-to-Ambient Thermal Resistance (BJA) ...........52NC/W

Junction-to-Case Thermal Resistance (BJC) ................11NC/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Digital Interface Supply Voltage V

Analog Supply Voltage V

UART Interface Logic Supply
Voltage

Logic Supply Voltage V

CURRENT CONSUMPTION

VCC Supply Current I

VCC Shutdown Supply Current I

VL Shutdown or Sleep Supply
Current

V

Shutdown Supply Current I

EXT

V18 Input Power-Supply Current
in Shutdown Mode

= 2.5V, TA = +25NC.) (Notes 2, 3)

EXT

V

CCSHDN

I

18SHDN

= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at

EXT

L

CC

EXT

CC

I

EXT

Internal PLL disabled and bypassed 1.71 3.6
Internal PLL enabled 2.35 3.6

18

1.8MHz crystal oscillator active, PLL
disabled, SPI/I2C interface idle, UART
interfaces idle, LDOEN = high

Baud rate = 1Mbps, 20MHz external clock,
SPI/I2C interface idle, PLL disabled, UART
in loopback mode, LDOEN = low

Shutdown mode, LDOEN = low, RST = low,
all inputs and outputs are idle

Shutdown or sleep mode, all inputs and

L

outputs are idle

Shutdown mode, RST = low, all inputs and
outputs are idle

Shutdown mode, LDOEN = low, RST = low,
all inputs and outputs are idle

(Note 1)

1.71 3.6 V

1.71 3.6 V

1.65 1.95 V

500

500

35

15

10

50

V

FA

FA

FA

FA

FA

6 ______________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V

= 2.5V, TA = +25NC.) (Notes 2, 3)

EXT

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V18 Input Power-Supply Current I

SCLK/SCL, MISO/SDA

MISO/SDA Output Logic-Low
Voltage in I2C Mode

MISO/SDA Output Logic-Low
Voltage in SPI Mode

MISO/SDA Output Logic-High
Voltage in SPI Mode

V

V

V

OHSPI

Input Logic-Low Voltage V

Input Logic-High Voltage V

Input Hysteresis V

Input Leakage Current I
Input Capacitance C

SPI/I2C, CS/A0, MOSI/A1 INPUTS

Input Logic-Low Voltage V

Input Logic-High Voltage V

Input Hysteresis V
Input Leakage Current I
Input Capacitance C

IRQ OUTPUT (OPEN DRAIN)

Output Logic-Low Voltage V
Output Leakage Current I

LDOEN AND RST INPUTS

Input Logic-Low Voltage V

Input Logic-High Voltage V

Input Hysteresis V
Input Leakage Current I

= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at

EXT

Baud rate = 1Mbps, 20MHz external clock,

18

PLL disabled, UART in loopback mode,
LDOEN = low (Note 4)

Sink current = 3mA, VL > 2V 0.4

OLI2C

OLSPI

Sink current = 3mA, VL < 2V

Sink current = 2mA 0.4 V

Source current = 2mA

SPI and I2C mode

IL

SPI and I2C mode

IH

HYST

HYST

OL

OL

HYST

SPI and I2C mode

VIN = 0 to VL, SPI and I2C mode -1 +1

IL

SPI and I2C mode 5 pF

IN

SPI and I2C mode

IL

SPI and I2C mode

IH

SPI and I2C mode 50 mV
VIN = 0 to VL, SPI and I2C mode -1 +1

IL

SPI and I2C mode 5 pF

IN

Sink current = 2mA 0.4 V

V

= 0 to VL, IRQ is not asserted

IRQ

IL

IH

VIN = 0 to V

IL

L

VL -

0.4

0.7 x
V

L

0.05 x
V

L

0.7 x
V

L

-1 +1

0.7 x
V

L

50 mV

-1 +1

2 mA

0.2 x
V

L

0.3 x
V

L

0.3 x
V

L

0.3 x
V

L

MAX3108

V

V

V

V

V

FA

V

V

FA

FA

V

V

FA

_______________________________________________________________________________________ 7

SPI/I2C UART with 128-Word FIFOs in WLP

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V

= 2.5V, TA = +25NC.) (Notes 2, 3)

EXT

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

UART INTERFACE
RTS, TX OUTPUTS

Output Logic-Low Voltage V

MAX3108

Output Logic-High Voltage V

Input Leakage Current I
Input Capacitance C

CTS, RX INPUTS

Input Logic-Low Voltage V

Input Logic-High Voltage V

Input Hysteresis V
CTS Input Leakage Current

RX Pullup Current I
Input Capacitance C

GPIO_ INPUTS/OUTPUTS

Output Logic-Low Voltage V

Output Logic-High Voltage V

Input Logic-Low Voltage V

Input Logic-High Voltage V

Pulldown Current I

XIN

Input Logic-Low Voltage V
Input Logic-High Voltage V
Input Capacitance C

XOUT

Input Capacitance C

= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at

EXT

OL

OH

HYST

I

PU

Sink current = 2mA 0.4 V

Source current = 2mA

Output is three-stated, V

IL

High-Z mode 5 pF

IN

IL

IH

RTS

= 0 to V

EXT

0.7 x
V

EXT

-1 +1

0.7 x
V

EXT

50 mV

V

IL

CTS

= 0 to V

EXT

-1 +1

VRX = 0V -7.5 -5.5 -3.5

IN

5 pF

Sink current = 20mA, push-pull or open-

OL

OH

IL

IH

PD

IL

IH

XIN

XOUT

drain output type, V

Sink current = 20mA, push-pull or open­drain output type, V

Source current = 5mA, push-pull output
type

GPIO_ is configured as an input 0.4 V

GPIO_ is configured as an input

V

= V

GPIO_

, GPIO_ is configured as an

EXT

input

EXT

EXT

> 2.3V

< 2.3V

V

-

EXT

0.4V

2/3 x
V

EXT

3.5 5.5 7.5

1.2 V
16 pF

16 pF

0.3 x
V

EXT

0.45

0.55

0.6 V

V

FA

V

V

FA
FA

V

V

V

FA

8 ______________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

AC ELECTRICAL CHARACTERISTICS

(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

External Cystal Frequency f
External Clock Frequency f
External Clock Duty Cycle (Note 5) 45 55 %

Baud-Rate Generator Clock
Input Frequency

I2C BUS: TIMING CHARACTERISTICS (Figure 1)

SCL Clock Frequency f

Bus Free Time Between a STOP
and START Condition

Hold Time for START Condition
and Repeated START Condition

Low Period of the SCL Clock t

High Period of the SCL Clock t

Data Hold Time

Data Setup Time t

Setup Time for Repeated START
Condition

Rise Time of Incoming SDA and
SCL Signals

Fall Time of SDA and SCL
Signals

= 2.5V, TA = +25NC.) (Note 2)

EXT

XOSC

t

HD:STA

t

HD:DAT

SU:DAT

t

SU:STA

= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at

EXT

1 4 MHz

CLK

f

REF

SCL

t

BUF

LOW

HIGH

t

R

t

F

Standard mode 100

Fast mode plus 1000
Standard mode 4.7
Fast mode 1.3
Fast mode plus 0.5
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
Standard mode 4.7
Fast mode 1.3
Fast mode plus 0.5
Standard mode 4.0
Fast mode 0.6
Fast mode plus 0.26
Standard mode 0 0.9
Fast mode 0 0.9
Fast mode plus 0
Standard mode 250

Fast mode plus 50
Standard mode 4.7
Fast mode 0.2
Fast mode plus 0.26

Standard mode (0.3 x VL to 0.7 x VL)
(Note 6)

Fast mode (0.3 x VL to 0.7 x VL) (Note 6)

Fast mode plus 120

Standard mode (0.3 x VL to 0.7 x VL)
(Note 6)

Fast mode (0.3 x VL to 0.7 x VL) (Note 6)

Fast mode plus 120

0.5 35 MHz

20 +

0.1C

20 +

0.1C

20 +

0.1C

20 +

0.1C

B

B

B

B

1000

1000

96 MHz

300

300

MAX3108

kHzFast mode 400

Fs

Fs

Fs

Fs

Fs

nsFast mode 100

Fs

ns

ns

_______________________________________________________________________________________ 9

SPI/I2C UART with 128-Word FIFOs in WLP

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC = 1.71V to 3.6V, VL = 1.71V to 3.6V, V
VCC = 2.8V, VL = 1.8V, V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Setup Time for STOP Condition t

= 2.5V, TA = +25NC.) (Note 2)

EXT

SU:STO

MAX3108

Capacitive Load for SDA and
SCL

SCL and SDA I/O Capacitance C
Pulse Width of Spike Suppressed t

SPI BUS: TIMING CHARACTERISTICS (Figure 2)

SCLK Clock Period t
SCLK Pulse Width High t
SCLK Pulse Width Low t
CS Fall to SCLK Rise Time
MOSI Hold Time t
MOSI Setup Time t
Output Data Propagation Delay t
MISO Rise and Fall Times t
CS Hold Time

Note 2: All units are production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Currents entering the IC are positive and currents exiting the IC are negative.
Note 4: When V18 is powered by an external voltage supply, it must have current capability above or equal to I18.
Note 5: Guaranteed by design; not production tested.
Note 6: CB is the total capacitance of either the clock or data line of the synchronous bus in pF.

CH+tCL

= 1.71V to 3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values are at

EXT

Standard mode 4.7
Fast mode 0.6
Fast mode plus 0.26
Standard mode (Note 5) 400

C

B

Fast mode plus (Note 5) 550
(Note 5) 10 pF

I/O

SP

38.4 ns

CH

t

CSS

DH

DO

t

CSH

CL

DS

FT

16 ns
16 ns

0 ns
3 ns
5 ns

30 ns

Fs

pFFast mode (Note 5) 400

50 ns

20 ns
10 ns

10 _____________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

Timing Diagrams

MAX3108

START CONDITION

(S)

SDA

t

HD:STA

SCL

Figure 1. I2C Timing Diagram

CS

t

CSH

SCLK

t

CSS

t

HD:DAT

t

t

DS

t

SU:DAT

HIGH

t

DH

REPEATED START CONDITION

t

SU:STA

t

R

t

CL

t

F

t

CH

(Sr)

t

R

t

HD:STA

t

LOW

t

SU:STO

t

F

STOP CONDITION

t

CSH

(P)

t

BUF

START CONDITION

(S)

MOSI

MISO

t

Figure 2. SPI Timing Diagram

______________________________________________________________________________________ 11

t

DO

FT

SPI/I2C UART with 128-Word FIFOs in WLP

Typical Operating Characteristics

(VCC = 2.5V, VL = 2.5V, V

= 2.5V, V

EXT

= VL, TA = +25°C unless otherwise noted.)

LDOEN

180

160

MAX3108

(mA)

SINK

I

140

120

100

80

60

40

20

0

SINK CURRENT (OPEN DRAIN)

vs. GPIO_ OUTPUT LOW VOLTAGE

V

= 3.6V

EXT

V

= 2.5V

EXT

V

= 1.71V

EXT

0 4

VOL (V)

321

MAX3108 toc01

SOURCE CURRENT (PUSH-PULL)

vs. GPIO_ OUTPUT HIGH VOLTAGE

70

60

V

= 3.3V

50

V

= 2.5V

EXT

40

(mA)

30

V

= 1.8V

EXT

SOURCE

I

20

10

0

0 4

EXT

VOH (V)

MAX3108 toc02

321

12 _____________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

Bump Configuration

TOP VIEW

(BUMPS ON BOTTOM)

+

A

CC

2 3 41

MISO/

SDA

MAX3108

CS/A0 IRQV

5

V

L

MAX3108

B

V

C

D

E

RST

18

LDOEN N.C.

XOUT SPI/I2C GPIO3 CTSXIN

GPIO2 RTS TX

EXT

SCLK/

SCL

MOSI/

A1

GPIO0

DGND

GPIO1AGND

RXV

WLP

(2.1mm × 2.1mm)

Bump Description

BUMP NAME FUNCTION

A1 V

CC

A2 MISO/SDA

A3

A4

A5 V

B1 V

B2

CS/A0

IRQ

L

18

RST

B3 SCLK/SCL

Analog Power Supply. VCC powers the PLL and internal LDO. Bypass VCC with a 0.1FF ceramic capaci­tor to AGND.

Serial-Data Output. When SPI/I2C is high, MISO/SDA functions as the SPI master input, slave output
(MISO). When SPI/I2C is low, MISO/SDA functions as the SDA, I2C serial-data input/output.

Active-Low Chip-Select and Address 0 Input. When SPI/I2C is high, CS/A0 functions as the CS, SPI
active-low chip-select. When SPI/I2C is low, CS/A0 functions as the A0 I2C device address program­ming input. Connect CS/A0 to DGND, VL, SCL, or SDA when SPI/I2C is low.

Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is pending and during initial
power-up.

Digital Interface Power Supply. VL powers the internal logic-level translators for RST, IRQ, MOSI/A1, CS/A0,
SCLK/SCL, MISO/SDA, LDOEN, and SPI/I2C. Bypass VL with a 0.1FF ceramic capacitor to DGND.

Internal 1.8V LDO Output and 1.8V Power-Supply Input. Bypass V18 with a 0.1FF ceramic capacitor to
DGND.

Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode. In hardware reset
mode, the internal PLL is shut down and there is no clock activity.

Serial-Clock Input. When SPI/I2C is high, SCLK/SCL functions as the SCLK SPI serial-clock input (up to
26MHz). When SPI/I2C is low, SCLK/SCL functions as the SCL, I2C serial-clock input (up to 1MHz in fast
mode plus).

______________________________________________________________________________________ 13

SPI/I2C UART with 128-Word FIFOs in WLP

Bump Description (continued)

BUMP NAME FUNCTION

Serial-Data Input and Address 1 Input. When SPI/I2C is high, MOSI/A1 functions as the SPI master

B4 MOSI/A1

B5 DGND Digital Ground
C1 AGND Analog Ground

MAX3108

C2 LDOEN

C3 N.C. Not Connected. Internally not connected.

C4 GPIO0

C5 GPIO1

D1 XIN

D2 XOUT

D3

D4 GPIO3

D5

E1 V

E2 GPIO2

E3
E4 TX Serial Transmitting Data Output
E5 RX Serial Receiving Data Input. RX has an internal weak pullup resistor to V

SPI/I2C SPI Selector Input or Active-Low I2C. Drive SPI/I2C low to enable I2C. Drive SPI/I2C high to enable SPI.

CTS Active-Low Clear-to-Send Input. CTS is a flow-control status input.

EXT

RTS Active-Low Request-to-Send Output. RTS can be set high or low by programming the LCR register.

output-slave input (MOSI). When SPI/I2C is low, MOSI/A1 functions as the A1 I2C device address pro­gramming input. Connect MOSI/A1 to DGND, VL, SCL, or SDA when SPI/I2C is low.

LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN low to disable the
internal LDO. Supply V

General-Purpose Input/Output 0. GPIO0 is user-programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO0 has a weak pulldown resistor to DGND when
configured as an input.

General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO1 has a weak pulldown resistor to DGND when
configured as an input.

Crystal/Clock Input. When using an external crystal, connect one end of the crystal to XIN and the other
end to XOUT. When using an external clock source, drive XIN with the single-ended external clock.

Crystal Output. When using an external crystal, connect one end of the crystal to XOUT and the other
end to XIN. When using an external clock source, leave XOUT unconnected.

General-Purpose Input/Output 3. GPIO3 is user-programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO3 has a weak pulldown resistor to DGND when
configured as an input.

Transceiver Interface Power Supply. V
CTS, and GPIO_. Bypass V

General-Purpose Input/Output 2. GPIO2 is user programmable as input or output (push-pull or open
drain) or an external event-driven interrupt source. GPIO2 has a weak pulldown resistor to DGND when
configured as an input.

with an external voltage source when LDOEN is low.

18

powers the internal logic-level translators for RX, TX, RTS,

EXT

with a 0.1FF ceramic capacitor to DGND.

EXT

EXT

.

14 _____________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

Detailed Description

The MAX3108 universal asynchronous receiver-trans­mitter (UART) bridges an SPI/MICROWIREK or I2C
microprocessor bus to an asynchronous serial-data
communication link. The MAX3108 contains an advanced
UART, a fractional baud-rate generator, and four GPIOs.
Eight-bit registers configure and monitor the MAX3108
and are accessed through SPI or I2C, selectable by an
external pin. The registers are organized by related func­tion as shown in the Register Map section.

The host controller loads data into the Transmit Hold
register (THR) through the SPI or I2C interface. This data
is automatically pushed into the transmit first-in/first-out
(FIFO), formatted, and sent out at TX. The MAX3108
adds START, STOP, and parity bits to the data before
transmitting at the selected baud rate. The clock configu­ration registers determine the baud rate, clock source,
and clock frequency prescaling.

The MAX3108 receiver detects a START bit as a high­to-low transition on RX. An internal clock samples this
data at 16 times the baud rate. The received data is
automatically placed in the receive FIFO and can be
read out by the host microcontroller through the Receive
Hold register (RHR).

The MAX3108’s register set is compatible with the
MAX3107.

levels are programmed through the FIFOTrgLvl register
with a resolution of eight FIFO locations. The receive
FIFO trigger signals to the host either that the receive
FIFO has a defined number of words waiting to be read
out in a block or that a known number of vacant FIFO
locations are available and ready to be filled. The trans­mit FIFO trigger generates an interrupt when the transmit
FIFO fill level is above the programmed trigger level. The
host then knows to throttle data writing to the transmit
FIFO through THR.

The host can read out the number of words pres­ent in each of the FIFOs through the TxFIFOLvl and
RxFIFOLvl registers.

The contents of the TxFIFO and RxFIFO are both cleared
when the MODE2[1]: FIFORst bit is set high.

Transmitter Operation

Figure 3 shows the structure of the transmitter with the
TxFIFO. The transmit FIFO can hold up to 128 words of
data that are added by writing to the THR register.

The current number of words in the TxFIFO can be
manually read out by the host controller through the
TxFIFOLvl register. The transmit FIFO fill level can be

2

DATA FROM SPI/I

C INTERFACE

MAX3108

Register Set

The MAX3108 has a flat register structure without shadow
registers. The registers are 8 bits wide. The MAX3108
registers have some similarities to the 16C550 registers.

Receive and Transmit FIFOs

The UART’s receiver and transmitter each have a
128-word-deep FIFO, reducing the number of intervals
that the host processor needs to dedicate for high­speed, high-volume data transfer to and from the device.
As the data rates of the asynchronous RX/TX interfaces
increase and get closer to those of the host controller’s
SPI/I2C data rates, UART management and flow-control
can make up a significant portion of the host’s activity.
By increasing FIFO size, the host is interrupted less often
and can use data block transfers to and from the FIFOs.

FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels
have been reached. The transmitter and receiver trigger

MICROWIRE is a trademark of National Semiconductor Corp.

______________________________________________________________________________________ 15

ISR[4]

TxFIFOLvl

ISR[5]

Figure 3. Transmit FIFO Signals

TRIGGER

LEVEL

EMPTY

THR

FIFOTrgLvl[3:0]

CURRENT FILL LEVEL

TRANSMIT FIFO

TRANSMITTER TX

128

3
2
1

SPI/I2C UART with 128-Word FIFOs in WLP

LSB

RECEIVED DATA

MIDDATA

SAMPLING

Figure 4. Receive Data Format

START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP

MAX3108

RECEIVED

RECEIVER RX

ISR[3]

ISR[6]

OVERRUN

TRIGGER

TIMEOUT

EMPTY

ERRORS

LSR[1]

CURRENT FILL LEVEL

I2C/SPI INTERFACE

LSR[0]

LSR[5:2]

Figure 5. Receive FIFO

programmed to generate an interrupt when more than a
programmed number of words are present in the TxFIFO
through the FIFOTrgLvl register. This TxFIFO interrupt
trigger level is selectable by the FIFOTrgLvl[3:0] bits.
When the transmit FIFO fill level increases beyond the

WORD ERROR 128

FIFOTrgLvl[7:4]

RECEIVE FIFO

RxFIFOLvl

RHR

4
3
2
1

DATA

MSB

programmed trigger level, an interrupt is generated in
ISR[4]: TxTrgInt.

An interrupt is generated in ISR[5]: TFifoEmptyInt when
the transmit FIFO is empty. ISR[5] goes high when
the transmitter starts transmitting the last word in the
TxFIFO. An additional interrupt is generated in STSInt[7]:
TxEmptyInt when the transmitter completes transmitting
the last word.

To halt transmission, set the MODE1[1]: TxDisabl bit
high. After TxDisabl is set, the transmitter completes the
transmission of the current character and then ceases
transmission. Turn the transmitter off prior to enabling
auto software flow control and AutoRTS flow control.

The TX output logic can be inverted through the IrDA[5]:
TxInv bit. Unless otherwise noted, all transmitter logic
described in this data sheet assumes that TxInv is set
low.

Receiver Operation

The receiver expects the format of the data at RX to
be as shown in Figure 4. The quiescent logic state is
logic-high and the first bit (the START bit) is logic-low.
The 8-bit data word expected to be received LSB first.
The receiver samples the data near the midbit instant
(Figure 4). The received words and their associated
errors are deposited into the receive FIFO. Errors and
status information are stored for every received word
(Figure 5). The host reads the data out of the receive
FIFO by reading RHR, which comes out oldest data
first. The status and error information for the word most
recently read from RHR is located in the Line Status
register (LSR). After a word is read out of RHR, LSR
contains the status information for that word.

16 _____________________________________________________________________________________

SPI/I2C UART with 128-Word FIFOs in WLP

ONE BIT PERIOD

RX

A

MAX3108

BAUD

BLOCK

Figure 6. Midbit Sampling

Figure 7. Clock Selection Diagram

1

2 3 4 5 6 7 8 9

CrystalEn

XOUT

XIN

CRYSTAL

OSCILLATOR

The following three error conditions are checked for each
received word: parity error, frame error, and noise on the
line. Parity errors are detected by calculating either even
or odd parity of the received word as programmed by
register settings. Framing errors are detected when the
received data frame does not match the expected frame
format in length. Line noise is detected by checking the
logical congruency of the three samples taken of each
bit (Figure 6).

The receiver can be turned off by setting the MODE1[0]:
RxDisabl bit high. After this bit is set high, the MAX3108
turns the receiver off immediately following the current
word and does not receive any further data.

10 11

MAJORITY

CENTER

SAMPLER

PLLPREDIVIDER

PLLEn

12 13 14 15 16

PLLBypass

BAUD-RATE

GENERATOR

The RX input logic can be inverted by setting the IrDA[4]:
RxInv bit high. Unless otherwise noted, all receiver logic
described in this data sheet assumes that RxInv is set
low.

Line Noise Indication

When operating in standard or 2x (i.e., not 4x) rate mode,
the MAX3108 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples per received bit have differing logic
levels, then noise on the transmission line has affected
the received data and it is considered to be noisy. This
noise indication is reflected in the LSR[5]: RxNoise bit for
each received byte. Parity errors are another indication
of noise, but are not as sensitive.

______________________________________________________________________________________ 17