MAX3000E/MAX3001E/MAX3002–MAX3012
+1.2V to +5.5V, ±15kV ESD-Protected, 0.1µA,
35Mbps, 8-Channel Level Translators
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Detailed Description
The MAX3000E/MAX3001E/MAX3002–MAX3012 logiclevel translators provide the level shifting necessary to
allow data transfer in a multivoltage system. Externally
applied voltages, V
CC
and VL, set the logic levels on
either side of the device. Logic signals present on the
VLside of the device appear as a higher voltage logic
signal on the VCCside of the device, and vice-versa.
The MAX3000E/MAX3001E/MAX3002/MAX3003 are
bidirectional level translators allowing data translation
in either direction (VL↔ VCC) on any single data line.
These devices use an architecture specifically
designed to be bidirectional without the use of a direction pin. The MAX3004–MAX3012 unidirectional level
translators level shift data in one direction (VL → VCCor
V
CC
→ VL) on any single data line. The
MAX3000E/MAX3001E/ MAX3002–MAX3012 accept V
L
from +1.2V to +5.5V. All devices have VCCranging
from +1.65V to +5.5V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems.
The MAX3000E/MAX3001E/MAX3002/MAX3004–
MAX3012 feature an output enable mode that reduces
VCCsupply current to less than 2µA, and VLsupply
current to less than 2µA when in shutdown. The
MAX3000E/MAX3001E have ±15kV ESD protection on
the VCCside for greater protection in applications that
route signals externally. The MAX3000E operates at a
guaranteed data rate of 230kbps; the MAX3001E operates at a guaranteed data rate of 4Mbps and the
MAX3002–MAX3012 are guaranteed with a data rate of
20Mbps of operation over the entire specified operating
voltage range.
Level Translation
For proper operation, ensure that +1.65V ≤ VCC≤ +5.5V,
+1.2V ≤ VL≤ +5.5V, and VL≤ VCC. During power-up
sequencing, VL≥ VCCdoes not damage the device.
During power-supply sequencing, when VCCis floating
and VLis powering up, up to 10mA current can be
sourced to each load on the VL side, yet the device does
not latch up.
The maximum data rate also depends heavily on the
load capacitance (see the Typical Operating
Characteristics), output impedance of the driver, and
the operational voltage range (see the Timing
Characteristics table).
Input Driver Requirements
The MAX3001E/MAX3002–MAX3012 architecture is
based on a one-shot accelerator output stage. See
Figure 5. Accelerator output stages are always in three-
state except when there is a transition on any of the
translators on the input side, either I/O VLor I/O VCC.
When there is such a transition, the accelerator stages
become active, charging (discharging) the capacitances
at the I/Os. Due to its bidirectional nature, both stages
become active during the one-shot pulse. This can lead
to some current feeding into the external source that is
driving the translator. However, this behavior helps to
speed up the transition on the driven side.
For proper full-speed operation, the output current
of a device that drives the inputs of the MAX3000E/
MAX3001E/MAX3002–MAX3012 should meet the following requirements:
• MAX3000E (230kbps):
i > 1mA, R
drv
< 1kΩ
• MAX3001E (4Mbps):
i > 10
7
x V x (C + 10pF)
• MAX3002–MAX3012 (20Mbps):
i > 10
8
x V x (C + 10pF)
where i is the driver output current, V is the logic-supply
voltage (i.e., VLor VCC) and C is the parasitic capacitance of the signal line.
Enable Output Mode (EN, EN A/B)
The MAX3000E/MAX3001E/MAX3002 and the MAX3004–
MAX3012 feature an EN input, and the MAX3003 has an
EN A/B input. Pull EN low to set the MAX3000E/
MAX3001E/MAX3002/MAX3004–MAX3012s’ I/O VCC1
through I/O V
CC
8 in three-state output mode, while I/O
V
L
1 through I/O VL8 have internal 6kΩ pulldown resistors. Drive EN to logic-high (VL) for normal operation. The
MAX3003 is intended for bus multiplexing or bus switching applications. Drive EN A/B low to place channels 1B
through 4B in active mode, while channels 1A through
4A are in three-state mode. Drive EN A/B to logic-high
(V
L
) to enable channels 1A through 4A, while channels
1B through 4B remain in three-state mode.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electrostatic discharges encountered during handling and
assembly. The I/O VCClines have extra protection
against static discharge. Maxim’s engineers have
developed state-of-the-art structures to protect these
pins against ESD of ±15kV without damage. The ESD
structures withstand high ESD in all states: normal
operation, three-state output mode, and powered
down. After an ESD event, Maxim’s E versions keep
working without latchup, whereas competing products
can latch and must be powered down to remove
latchup.