MAXIM MAX2852 Technical data

19-5010; Rev 1; 3/10

EVALUATION KIT

AVAILABLE

General Description

The MAX2852 is a single-chip RF receiver IC designed
for 5GHz wireless HDMI applications. The IC includes
all circuitry required to implement the complete receiver
function and crystal oscillator, providing a fully integrated
transmit path, VCO, frequency synthesis, and baseband/
control interface. It includes a fast-settling, sigma-delta
RF fractional synthesizer with 76Hz frequency program­ming step size. The IC also integrates on-chip I/Q ampli­tude and phase-error calibration circuits.

The receiver includes both an in-channel RSSI and an
RF RSSI.

The receiver chip is housed in a small, 68-pin thin QFN
leadless plastic package with exposed pad.

Applications

5GHz Wireless HDMIK (WHDI)

5GHz FDD Backhaul and WiMAXK

5GHz Receiver

Features

S 5GHz Single IEEE 802.11a Receiver

4900MHz to 5900MHz Frequency Range

4.5dB Rx Noise Figure
70dB Rx Gain-Control Range with 2dB Step
Size, Digitally Controlled
60dB Dynamic Range Receiver RSSI
RF Wideband Receiver RSSI
Programmable 20MHz/40MHz Rx I/Q Lowpass
Channel Filters
Sigma-Delta Fractional-N PLL with 76Hz
Resolution
Monolithic Low-Noise VCO with -35dBc
Integrated Phase Noise
4-Wire SPI™
I/Q Analog Baseband Interface
On-Chip Digital Temperature Sensor Readout
Complete Baseband Interface

+2.7V to +3.6V Supply Voltage

S

S

Small, 68-Pin Thin QFN Package (10mm x 10mm)

Digital Interface

MAX2852

SPI is a trademark of Motorola, Inc.
HDMI is a trademark of HDMI Licensing, LLC.
WiMAX is a trademark of WiMAX Forum.

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX2852ITK+

*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.

Typical Operating Circuit appears at end of data sheet.

-25NC to +85NC

68 Thin QFN-EP*

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

5GHz Receiver

ABSOLUTE MAXIMUM RATINGS

V

Pins to GND ................................................-0.3V to +3.9V

CC_

RF Inputs Maximum Current: RXRF+, RXRF-

to GND ................................................................-1mA to +1mA

RF Outputs: TXRF+, TXRF- to GND .....................-0.3V to +3.9V

Analog Inputs: TXBBI+, TXBBI-, TXBBQ+, TXBBQ-, XTAL

to GND ..............................................................-0.3V to +3.9V

Analog Outputs: RXBBI+, RXBBI-, RXBBQ+,

RXBBQ-, RSSI, CLKOUT2, VCOBYP, CPOUT+,

MAX2852

CPOUT- to GND ...............................................-0.3V to +3.9V

Digital Inputs: ENABLE, CS, SCLK, DIN to GND ...-0.3V to +3.9V

Digital Outputs: DOUT, CLKOUT to GND ............-0.3V to +3.9V

Short-Circuit Duration

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION! ESD SENSITIVE DEVICE

DC ELECTRICAL CHARACTERISTICS

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, ENABLE set according to operating mode, CS = high, SCLK
= DIN = low, transmitter in maximum gain, T
using the Typical Operating Circuit. 100mV
calibration mode. Typical values measured at V
40MHz. PA control pins open circuit, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage, V

Supply Current

Rx I/Q Output Common-Mode
Voltage

Tx Baseband Input Common­Mode Voltage Operating Range

Tx Baseband Input Bias Current Source current 10 20

LOGIC INPUTS: ENABLE, SCLK, DIN, CS

Digital Input-Voltage High, V

Digital Input-Voltage Low, V
Digital Input-Current High, I
Digital Input-Current Low, I

CC

Shutdown mode, T
Clock-out only mode 7.4 11
Standby mode 60 89
Receive mode 135 174
Transmit calibration mode, one transmitter is on 214 261
Receive calibration mode 268 327

IH

IL

IH

IL

= -25NC to +85NC. Power matching and termination for the differential RF output pins

A

differential I and Q signals applied to I/Q baseband inputs of transmitters in transmit

RMS

= 2.85V, LO frequency = 5.35GHz, TA = +25NC. Channel bandwidth is set to

CC

CC_PA_BIAS

is disconnected.) (Note 1)

= +25NC

A

Analog Outputs ................................................................. 10s

Digital Outputs ................................................................... 10s

RF Input Power .............................................................. +10dBm

RF Output Differential Load VSWR ........................................6:1

Continuous Power Dissipation (T

68-Pin Thin QFN (derate 29.4mW/NC above +70NC) ....2352mW

Operating Temperature Range .......................... -25NC to +85NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +160NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

= +85NC)

A

2.7 3.6 V
10

0.9 1.1 1.3 V

0.5 1.1 V

V

-

CC

0.4

0.4 V

-1 +1

-1 +1

FA

mA

FA

V

FA
FA

2 ______________________________________________________________________________________

5GHz Receiver

DC ELECTRICAL CHARACTERISTICS (continued)

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, ENABLE set according to operating mode, CS = high, SCLK
= DIN = low, transmitter in maximum gain, T
using the Typical Operating Circuit. 100mV
calibration mode. Typical values measured at V
40MHz. PA control pins open circuit, V

PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC OUTPUTS: DOUT, CLKOUT

Digital Output-Voltage High, V

Digital Output-Voltage Low, V

Digital Output Voltage in
Shutdown Mode

Sourcing 1mA

OH

Sinking 1mA 0.4 V

OL

Sinking 1mA V

AC ELECTRICAL CHARACTERISTICS—Rx MODE

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF+ and
RXRF- differential ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
resistance and 10pF load capacitance. The RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
= 2.85V, channel bandwidths of 40MHz, T

PARAMETER CONDITIONS MIN TYP MAX UNITS

RECEIVER SECTION: RF INPUT TO I/Q BASEBAND LOADED OUTPUT (Includes 50I to 100I RF Balun and Matching)

RF Input Frequency Range 4.9 5.9 GHz

Peak-to-Peak Gain Variation
over RF Frequency Range at
One Temperature

RF Input Return Loss All LNA settings -6 dB

Total Voltage Gain

RF Gain Steps Relative to
Maximum Gain

Baseband Gain Range

Baseband Gain Step 2 dB
RF Gain-Change Settling Time Gain settling to within Q0.5dB of steady state; RXHP = 1 400 ns

Baseband Gain-Change Settling
Time

4.9GHz to 5.35GHz 0.3 2.6

5.35GHz to 5.9GHz 2.2 5.3

Maximum gain; Main address 1 D7:0 = 11111111 61 68
Minimum gain; Main address 1 D7:0 = 00000000 -2 +0.5
Main address 1 D7:D5 = 110 -8
Main address 1 D7:D5 = 101 -16
Main address 1 D7:D5 = 001 -32
Main address 1 D7:D5 = 000 -40

From maximum baseband gain (Main address 1 D3:D0
= 1111) to minimum baseband gain (Main address 1
D3:D0 = 0000)

Gain settling to within Q0.5dB of steady state; RXHP = 1 200 ns

= -25NC to +85NC. Power matching and termination for the differential RF output pins

A

differential I and Q signals applied to I/Q baseband inputs of transmitters in transmit

RMS

= 2.85V, LO frequency = 5.35GHz, TA = +25NC. Channel bandwidth is set to

CC

CC_PA_BIAS

A

is disconnected.) (Note 1)

= +25NC.) (Note 1)

-

V

CC

0.4

OL

loaded with 10kI differential load

RMS

27.5 30 32.5 dB

V

V

CC

dB

dB

dB

MAX2852

_______________________________________________________________________________________ 3

5GHz Receiver

AC ELECTRICAL CHARACTERISTICS—Rx MODE (continued)

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF+ and
RXRF- differential ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
resistance and 10pF load capacitance. The RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
= 2.85V, channel bandwidths of 40MHz, T

PARAMETER CONDITIONS MIN TYP MAX UNITS

MAX2852

DSB Noise Figure

Out-of-Band Input IP3

1dB Gain Desensitization by
Alternate Channel Blocker

Input 1dB Gain Compression

Output 1dB Gain Compression

= +25NC.) (Note 1)

A

Balun input referred,
integrated from 10kHz
to 9.5MHz at I/Q base­band output for 20MHz
RF bandwidth

Balun input referred,
integrated from 10kHz
to 19MHz at I/Q base­band output for 40MHz
RF bandwidth

20MHz RF channel;
two-tone jammers at
+25MHz and +48MHz
frequency offset with

-39dBm/tone

40MHz RF channel;
two-tone jammers at
+50MHz and +96MHz
frequency offset with

-39dBm/tone

Blocker at Q40MHz offset frequency for 20MHz RF
channel

Blocker at Q80MHz offset frequency for 40MHz RF
channel

Max RF gain (Main address 1 D7:D5 = 111) -32
Max RF gain - 8dB (Main address 1 D7:D5 = 110) -24
Max RF gain - 16dB (Main address 1 D7:D5 = 101) -16
Max RF gain - 32dB (Main address 1 D7:D5 = 001) 0

Over passband frequency range; at any gain setting;
1dB compression point

Maximum RF gain (Main
address 1 D7:D5 = 111)

Maximum RF gain - 16dB
(Main address 1 D7:D5 = 101)

Maximum RF gain (Main
address 1 D7:D5 = 111)

Maximum RF gain - 16dB
(Main address 1 D7:D5 = 101)

-65dBm wanted signal; RF
gain = max (Main address 1
D7:D0 = 11101001)

-49dBm wanted signal; RF
gain = max - 16dB (Main
address 1 D7:D0 = 10101001)

-45dBm wanted signal; RF
gain = max - 32dB (Main
address 1 D7:D0 = 00111111)

-65dBm wanted signal; RF
gain = max (Main address 1
D7:D0 = 11101001)

-49dBm wanted signal; RF
gain = max - 16dB (Main
address 1 D7:D0 = 10101001)

-45dBm wanted signal; RF
gain = max - 32dB (Main
address 1 D7:D0 = 00101001)

loaded with 10kI differential load

RMS

4.5

15

4.5

15

-13

-5

11

-13

-5

11

-24

-24

0.63 V

dB

dBm

dBm

dBm

P-P

CC

4 ______________________________________________________________________________________

5GHz Receiver

AC ELECTRICAL CHARACTERISTICS—Rx MODE (continued)

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF+ and
RXRF- differential ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
resistance and 10pF load capacitance. The RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
= 2.85V, channel bandwidths of 40MHz, T

PARAMETER CONDITIONS MIN TYP MAX UNITS

Baseband -3dB Lowpass Corner
Frequency

Baseband Filter Stopband
Rejection

Baseband -3dB Highpass Corner
Frequency

Steady-State I/Q Output DC Error
with AC-Coupling

I/Q Gain Imbalance 1MHz baseband output, 1-sigma value 0.1 dB
I/Q Phase Imbalance 1MHz baseband output, 1-sigma value 0.2 degrees
Sideband Suppression 1MHz baseband output (Note 2) 40 dB

Receiver Spurious Signal
Emissions

RF RSSI Output Voltage -20dBm input power 1.75 V
Baseband RSSI Slope 19.5 26.5 35.5 mV/dB

Baseband RSSI Maximum Output
Voltage

Baseband RSSI Minimum Output
Voltage

RF Loopback Conversion Gain

= +25NC.) (Note 1)

A

Main address 0 D1 = 0 9.5
Main address 0 D1 = 1 19
Rejection at 30MHz offset frequency for 20MHz channel 57 70
Rejection at 60MHz offset frequency for 40MHz channel 57 70
Main address 5 D1 = 1 600
Main address 5 D1 = 0 10

50Fs after enabling receive mode and toggling RxHP
from 1 to 0, averaged over many measurements if I/Q
noise voltage exceeds 1mV
ting, no input signal, 1-sigma value

LO frequency -75
2 x LO frequency -62
3 x LO frequency -75
4 x LO frequency -60

Tx VGA gain at maximum (Main address 9 D9:D4
= 111111); Rx VGA gain at maximum - 24dB (Main
address 1 D3:D0 = 0101)

, at any given gain set-

RMS

loaded with 10kI differential load

RMS

2 mV

2.3 V

0.5 V

-6 +2 +10 dB

CC

MHz

dB

kHz

dBm/

MHz

MAX2852

_______________________________________________________________________________________ 5

5GHz Receiver

AC ELECTRICAL CHARACTERISTICS—Tx CALIBRATION MODE

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at TXRF+ and
TXRF- differential ports using the Typical Operating Circuit. 100mV
transmitter (differential DC-coupled). Typical values measured at V

PARAMETER CONDITIONS MIN TYP MAX UNITS

Tx I/Q Input Impedance (R||C)

MAX2852

Tx Calibration Ftone Level

Tx Calibration Gain Range Adjust Local address 27 D2:D0 35 dB

Minimum differential resistance 100
Maximum differential capacitance 1.2 pF

At Tx gain code (Main address 9 D9:D4) = 100010 and

-15dBc carrier leakage (Local address 27 D2:D0 = 110
and Main address 1 D3:D0 = 0000)

AC ELECTRICAL CHARACTERISTICS—FREQUENCY SYNTHESIS

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, frequency = 5.35GHz, TA = -25NC to +85NC. Reference fre­quency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low. Typical values measured at V
quency = 5.35GHz, T

PARAMETER CONDITIONS MIN TYP MAX UNITS

FREQUENCY SYNTHESIZER

RF Channel Center Frequency 4.9 5.9 GHz

Channel Center Frequency
Programming Step

Closed-Loop Integrated Phase
Noise

Charge-Pump Output Current 0.8 mA

Spur Level

Reference Frequency 40 MHz

Reference Frequency Input
Levels

CLKOUT Signal Level 10pF load capacitance

= +25NC.) (Note 1)

A

Loop BW = 200kHz, integrate phase noise from 1kHz to
10MHz

f

OFFSET

f

OFFSET

AC-coupled to XTAL pin 800 mV

= 0 to 19MHz -42
= 40MHz -66

sine and cosine signal applied to I/Q baseband inputs of

RMS

= 2.85V, channel bandwidths of 40MHz, TA = +25NC.) (Note 1)

CC

-28 dBV

= 2.85V, TA = +25NC, LO fre-

CC

76.294 Hz

-35 dBc

-

V

CC

0.8

VCC -

0.1

kI

dBc

V

P-P

RMS

P-P

6 ______________________________________________________________________________________

5GHz Receiver

AC ELECTRICAL CHARACTERISTICS—MISCELLANEOUS BLOCKS

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, TA = -25NC to +85NC. Reference frequency = 40MHz, ENABLE
= high, CS = high, SCLK = DIN = low. Typical values measured at V

PARAMETER CONDITIONS MIN TYP MAX UNITS

ON-CHIP TEMPERATURE SENSOR

Digital Output Code

Read-out at DOUT pin through
Main address 3 D4:D0

AC ELECTRICAL CHARACTERISTICS—TIMING

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, frequency = 5.35GHz, TA = -25NC to +85NC. Reference
frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low. Typical values measured at V

5.35GHz, T

SYSTEM TIMING

Shutdown Time 2

Maximum Channel Switching
Time

Maximum Channel Switching
Time With Preselected VCO
Sub-Band

Rx Turn-On Time (from
Standby Mode)

Rx Turn-Off Time (to Standby
Mode)

4-WIRE SERIAL-INTERFACE TIMING (See Figure 1)

SCLK Rising Edge to CS
Falling Edge Wait Time

Falling Edge of CS to Rising
Edge of First SCLK Time

DIN to SCLK Setup Time t
DIN to SCLK Hold Time t

= +25NC.) (Note 1)

A

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Loop bandwidth = 200kHz, settling to within
Q1kHz from steady state

Loop bandwidth = 200kHz, settling to within
Q1kHz from steady state

Measured from CS rising edge, Rx gain settles
to within 0.5dB of steady state

From CS rising edge

t

CSO

t

CSS

DS

DH

= 2.85V, TA = +25NC.) (Note 1)

CC

= +25NC

T

A

T

= +85NC

A

T

= -20NC

A

17
25

9

= 2.85V, LO frequency =

CC

2 ms

56

2

0.1

6 ns

6 ns

6 ns
6 ns

Fs

Fs

Fs

Fs

MAX2852

_______________________________________________________________________________________ 7

5GHz Receiver

AC ELECTRICAL CHARACTERISTICS—TIMING (continued)

(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, frequency = 5.35GHz, TA = -25NC to +85NC. Reference
frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low. Typical values measured at V

5.35GHz, T

SCLK Pulse-Width High t
SCLK Pulse-Width Low t

MAX2852

Last Rising Edge of SCLK to
Rising Edge of CS or Clock to
Load Enable Setup Time

CS High Pulse Width

Time Between Rising Edge of
CS and the Next Rising Edge
of SCLK

SCLK Frequency f
Rise Time t
Fall Time t

SCLK Falling Edge to Valid
DOUT

Note 1: The MAX2852 is production tested at T

Note 2: For optimal Rx and Tx quadrature accuracy over temperature, the user can utilize the Rx calibration and Tx calibration

= +25NC.) (Note 1)

A

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CH

CL

t

CSH

t

CSW

t

CS1

CLK

t

specified otherwise. Minimum/maximum limits at TA = -25NC and +85NC are guaranteed by design and characterization.
There is no power-on register settings self-reset; recommended register settings must be loaded after VCC is applied.

circuit to assist quadrature calibration.

6 ns

R

F

D

= +25NC; minimum/maximum limits at TA = +25NC are guaranteed by test, unless

A

= 2.85V, LO frequency =

CC

6 ns
6 ns

50 ns

6 ns

40 MHz

2.5 ns

2.5 ns

12.5 ns

8 ______________________________________________________________________________________

5GHz Receiver

Rx EVM vs. Rx BASEBAND

Typical Operating Characteristics

(VCC = 2.8V, f
balun, T

A

141

140

139

138

137

136

135

SUPPLY CURRENT (mA)

134

133

132

2.6 3.6

71

70

69

68

67

66

65

MAXIMUM GAIN (dB)

64

63

62

4.9 5.9

-15

-20

-25

LNA = MAX = -8dB

EVM (dB)

-30

LNA = MAX = -16dB

-35

-40

-90 10

= 5.35GHz, f

LO

= 40MHz, CS = high, SCLK = DIN = low, RF BW = 20MHz, Tx output at 50I unbalanced output of

REF

= +25NC, using the MAX2852 Evaluation Kit.)

Rx MODE SUPPLY CURRENT

45

40

TA = +85°C

TA = -20°C

TA = +25°C

SUPPLY VOLTAGE (V)

MAX2852 toc01

35

30

25

20

NOISE FIGURE (dB)

15

10

5

3.53.43.2 3.32.8 2.9 3.0 3.12.7

0

0 14 15

Rx MAXIMUM GAIN vs.

TEMPERATURE AND FREQUENCY

80

TA = -20°C

TA = +25°C

TA = +85°C

5.75.55.35.1

FREQUENCY (GHz)

MAX2852 toc04

70

60

LNA = MAX - 16dB

50

40

30

GAIN (dB)

20

10

0

-10
0 16

Rx EVM vs. INPUT POWER

(CHANNEL BANDWIDTH = 20MHz)

MAX2852 toc07

12

10

8

6

Rx EVM (%)

4

2

0

-30 0

LNA = MAX

LNA = MAX = -24dB

INPUT POWER (dBm)

LNA = MAX = -40dB

LNA = MAX = -32dB

-10-30-50-70

Rx NOISE FIGURE vs. VGA GAIN

SETTINGS (BALUN INPUT REFERRED)

MAX - 40dB

MAX - 32dB

MAX - 24dB

MAX - 16dB

MAX - 8dB

MAX

131210 113 4 5 6 7 8 91 2

Rx VGA GAIN SETTINGS

Rx GAIN vs. BASEBAND VGA GAIN

LNA = MAX

LNA = MAX - 8dB

LNA = MAX - 32dB

LNA = MAX - 24dB

BASEBAND VGA GAIN CODE

LNA = MAX - 40dB

14128 104 62

OUTPUT LEVEL

VGA GAIN = 2/4/6/8/10/12/14

VGA GAIN = 0

VGA GAIN =

3/5/7/9/11/13/15

-5-10-15-20-25

Rx BASEBAND OUTPUT LEVEL (dBV

)

rms

MAX2852 toc02

MAXIMUM GAIN (dB)

0.60

0.55

MAX2852 toc05

0.50

)

RMS

0.45

(V

1dB

0.40

0.35

OUTPUT V

0.30

0.25

0.20

MAX2852 toc08

Rx EVM (%)

Rx MAXIMUM GAIN vs. FREQUENCY

80

70

60

50

40

30

20

4.9 5.9

Rx OUTPUT V

TA = -20°C

0

LNA = MAX GAIN

LNA = MAX - 8dB

LNA = MAX - 16dB

LNA = MAX - 24dB

LNA = MAX - 32dB

LNA = MAX - 40dB

FREQUENCY (GHz)

vs. GAIN SETTING

1dB

TA = +25°C

6

BASEBAND VGA GAIN CODE

TA = +85°C

8 10

5.75.55.35.1

Rx EVM vs. OFDM JAMMER POWER AT

20MHz AND 40MHz OFFSET FREQUENCY

WITH WANTED SIGNAL AT -66dBm

14

12

10

8

6

4

2

0

-40 10

20MHz OFFSET

40MHz OFFSET

INPUT POWER (dBm)

50-5-10-15-20-25-30-35

MAX2852

MAX2852 toc03

MAX2852 toc06

14122 4

MAX2852 toc09

_______________________________________________________________________________________ 9

5GHz Receiver

Typical Operating Characteristics (continued)

(VCC = 2.8V, f
balun, T

= +25NC, using the MAX2852 Evaluation Kit.)

A

= 5.35GHz, f

LO

= 40MHz, CS = high, SCLK = DIN = low, RF BW = 20MHz, Tx output at 50I unbalanced output of

REF

Rx EMISSION SPECTRUM AT

LNA INPUT (LNA = MAX GAIN)

-10

-20

MAX2852

-30

-40

-50

-60

(dBm)

-70

-80

-90

-100

-110
0 26.5

Rx RF RSSI OUTPUT

2.5

LOW GAIN, TA = +85°C

2.0

1.5

1.0

RF RSSI OUTPUT VOLTAGE (V)

0.5

0

LOW GAIN,
TA = +25°C

LOW GAIN,
TA = -20°C

-50 0
RF INPUT POWER (dBm)

2LO 4LO

2.65GHz/div

HIGH GAIN,
T

= +85°C

A

HIGH GAIN,

= +25°C

T

A

HIGH GAIN, TA = -20°C

MAX2852 toc10

40

30

20

10

REAL PART (I)

-10

-20

MAX - 32dB

MAX GAIN

0

4.80 6.00

RF FREQUENCY (GHz)

MAX GAIN

MAX - 40dB

Rx INPUT IMPEDANCE

MAX2852 toc11

MAX - 32dB

MAX - 40dB

5.805.605.405.205.00

20

10

0

-10

-20

-30

-40

0

-2

-4

-6

-8

-10

-12

IMAGINARY PART (I)

-14

Rx INPUT RETURN LOSS (dB)

-16

-18

-20

Rx RF RSSI ATTACK TIME

(+40dB SIGNAL STEP)

D: 280ns

MAX2852 toc13

1.0V/div

0V

1.0V/div

0V

-5-10-15-20-25-30-35-40-45

GAIN CONTROL

V

RSSI

@: 192ns

400ns/div

MAX2852 toc14

D: 1.32V
@: 1.84V

1.0V/div

0V

1.0V/div

0V

Rx INPUT RETURN LOSS

LNA = MAX

LNA = MAX - 32dB

LNA = MAX - 40dB

4900 5900

FREQUENCY (MHz)

5700550053005100

Rx RF RSSI DELAY TIME

(-40dB SIGNAL STEP)

D: 216ns
@: 128ns

GAIN CONTROL

V

RSSI

400ns/div

MAX2852 toc15

D: 1.30V
@: 460mV

MAX2852 toc12

BASEBAND RSSI VOLTAGE

vs. INPUT POWER

3.0

2.5

2.0

1.5

1.0

0.5

BASEBAND RSSI OUTPUT VOLTAGE (V)

0

-100 20

LNA = MAX

LNA = MAX - 8dB

RF INPUT POWER (dBm)

LNA = MAX - 40dB

LNA = MAX - 32dB

LNA = MAX - 16dB

LNA =

MAX - 24dB

0-20-40-60-80

MAX2852 toc16

2.7V

0V

2.4V

0.8V

Rx BASEBAND RSSI

+40dB STEP RESPONSE

D: 460ns
@: 440ns

LNA GAIN CONTROL

RSSI OUTPUT

1

µs/div

MAX2852 toc17

D: 1.50V
@: 2.30V

2.7V

2.0V

0.6V

0V

Rx BASEBAND RSSI

-32dB STEP RESPONSE

LNA GAIN CONTROL

RSSI OUTPUT

10 _____________________________________________________________________________________

1

µs/div

D: 1.18µs
@: 1.16

µs

MAX2852 toc18

D: 1.62V
@: 480mV

5GHz Receiver

Typical Operating Characteristics (continued)

(VCC = 2.8V, f
balun, T

A

= 5.35GHz, f

LO

= 40MHz, CS = high, SCLK = DIN = low, RF BW = 20MHz, Tx output at 50I unbalanced output of

REF

= +25NC, using the MAX2852 Evaluation Kit.)

MAX2852

Rx LPF 20MHz CHANNEL BANDWIDTH

RESPONSE

-35

RESPONSE (dB)

-135
10k 100M

BASEBAND FREQUENCY (Hz)

Rx LPF 40MHz CHANNEL

BANDWIDTH GROUP DELAY

100

GROUP DELAY (ns)

MAX2852 toc22

MAX2852 toc19

RESPONSE (dB)

-135

Rx BASEBAND

I/Q OUTPUT

50mV/div

Rx LPF 40MHz CHANNEL BANDWIDTH

RESPONSE

-35

10k 100M

FREQUENCY (Hz)

Rx DC OFFSET SETTLING RESPONSE

(-30dB Rx VGA GAIN STEP)

GAIN-CONTROL
TOGGLE

0V

MAX2852 toc23

CH1 PEAK TO
PEAK: 81.9mV

MAX2852 toc20

10mV/div

Rx BASEBAND

I/Q OUTPUT

Rx LPF 20MHz CHANNEL

BANDWIDTH GROUP DELAY

100

GROUP DELAY (ns)

0

10k

FREQUENCY (Hz)

Rx DC OFFSET SETTLING RESPONSE

(+8dB Rx VGA GAIN STEP)

CH1 PEAK TO

GAIN-CONTROL

0V

TOGGLE

PEAK: 8.60mV

MAX2852 toc21

100M

MAX2852 toc24

10mV/div

Rx BASEBAND

I/Q OUTPUT

0

10k 100M

FREQUENCY (Hz)

Rx DC OFFSET SETTLING RESPONSE

(+16dB Rx VGA GAIN STEP)

CH1 PEAK TO

0V

GAIN-CONTROL

TOGGLE

200ns/div

PEAK: 17.3mV

______________________________________________________________________________________ 11

MAX2852 toc25

Rx BASEBAND

I/Q OUTPUT

50mV/div

200ns/div

Rx DC OFFSET SETTLING RESPONSE

(+32dB Rx VGA GAIN STEP)

GAIN-CONTROL TOGGLE

0V

200ns/div

CH1 PEAK TO
PEAK: 69.0mV

MAX2852 toc26

Rx BASEBAND

I/Q OUTPUT

10mV/div

200ns/div

Rx BASEBAND DC OFFSET SETTLING

RESPONSE WITH RxHP = 1

(MAX - 40dB TO MAX LNA GAIN STEP)

GAIN-CONTROL

TOGGLE

0V

10µs/div

MAX2852 toc27

5GHz Receiver

100ns/div

100ns/div

Typical Operating Characteristics (continued)

(VCC = 2.8V, f
balun, T

A

= 5.35GHz, f

LO

= 40MHz, CS = high, SCLK = DIN = low, RF BW = 20MHz, Tx output at 50I unbalanced output of

REF

= +25NC, using the MAX2852 Evaluation Kit.)

Rx BASEBAND DC OFFSET SETTLING

RESPONSE WITH RxHP = 0

(MAX TO MAX - 40dB LNA GAIN STEP)

MAX2852

GAIN-CONTROL

TOGGLE

Rx BASEBAND

I/Q OUTPUT

0V

50mV/div

Rx BASEBAND VGA SETTLING

RESPONSE (-30dB BASEBAND

VGA GAIN STEP)

Rx BASEBAND

I/Q OUTPUT

0V

0.1V/div

10µs/div

MAX2852 toc28

MAX2852 toc31

CH1 PEAK TO
PEAK : 652mV

GAIN-CONTROL

TOGGLE

Rx BASEBAND

I/Q OUTPUT

10mV/div

Rx BASEBAND

OUTPUT

0.1V/div

Rx BASEBAND DC OFFSET SETTLING

RESPONSE WITH RxHP = 1

(MAX - 40dB TO MAX LNA GAIN STEP)

GAIN-CONTROL

TOGGLE

0V

10µs/div

Rx BASEBAND VGA SETTLING

RESPONSE (+4dB BASEBAND

VGA GAIN STEP)

GAIN-CONTROL

TOGGLE

0V

CH1 PEAK TO
PEAK: 568mV

MAX2852 toc29

MAX2852 toc32

Rx BASEBAND

I/Q OUTPUT

50mV/div

Rx BASEBAND

OUTPUT

0.1V/div

Rx BASEBAND DC OFFSET SETTLING

RESPONSE WITH RxHP = 0

(MAX - 40dB TO MAX LNA GAIN STEP)

GAIN-CONTROL

TOGGLE

0V

10µs/div

Rx BASEBAND VGA SETTLING

RESPONSE (+16dB BASEBAND

VGA GAIN STEP)

CH1 PEAK TO
PEAK: 532mV

GAIN-CONTROL

TOGGLE

0V

MAX2852 toc30

MAX2852 toc33

100ns/div

100ns/div

Rx BASEBAND VGA SETTLING

Rx BASEBAND

OUTPUT

0.1V/div

RESPONSE (+30dB BASEBAND

VGA GAIN STEP)

CH1 PEAK TO
PEAK: 800mV
CLIPPING NEGATIVE

GAIN-CONTROL

TOGGLE

0V

100ns/div

MAX2852 toc34

0.1V/div

Rx BASEBAND

OUTPUT

Rx LNA SETTLING RESPONSE

(MAX TO MAX - 40dB GAIN STEP)

0V

MAX2852 toc35

D: 130mv
@: 132mv

CH1 RMS:
168mV

GAIN-CONTROL

TOGGLE

Rx LNA SETTLING RESPONSE

(MAX - 8dB TO MAX GAIN STEP)

GAIN-CONTROL

TOGGLE

Rx BASEBAND

OUTPUT

0V

0.1V/div

D: 130mv
@: 132mv

CH1 RMS:
188mV

12 _____________________________________________________________________________________

100ns/div

MAX2852 toc36

5GHz Receiver

Typical Operating Characteristics (continued)

(VCC = 2.8V, f
balun, T

A

= 5.35GHz, f

LO

= 40MHz, CS = high, SCLK = DIN = low, RF BW = 20MHz, Tx output at 50I unbalanced output of

REF

= +25NC, using the MAX2852 Evaluation Kit.)

MAX2852

Rx BASEBAND

OUTPUT

0.1V/div

Rx BASEBAND

OUTPUT

0.1V/div

132

110

Rx LNA SETTLING RESPONSE

(MAX - 16dB TO MAX GAIN STEP)

CH1 RMS: 176mV

GAIN-CONTROL

TOGGLE

0V

D: 130mv
@: 132mv

100ns/div

Rx LNA SETTLING RESPONSE

(MAX - 40dB TO MAX GAIN STEP)

CH1 RMS: 154mV

GAIN-CONTROL

TOGGLE

0V

D: 130mv
@: 132mv

200ns/div

HISTOGRAM: Rx STATIC DC OFFSET

88

66

44

22

0

MAX2852 toc37

MAX2852 toc40

MAX2852 toc43

Rx BASEBAND

OUTPUT

0.1V/div

648

540

432

324

216

108

2V/div

0.1V/div

Rx LNA SETTLING RESPONSE

(MAX - 24dB TO MAX GAIN STEP)

CH1 RMS: 174mV

GAIN-CONTROL

TOGGLE

0V

D: 130mv
@: 132mv

100ns/div

HISTOGRAM: Rx I/Q GAIN IMBALANCE

0

-800.00m

SAMPLES = 3413, AVG = -0.015dB, STDEV = 0.042dB

0

MAX2852 toc38

MAX2852 toc41

800.00m

POWER-ON DC OFFSET CANCELLATION

0V

0V

ENGAGE 600kHz
HIGHPASS CORNER

WITH INPUT SIGNAL

D: 2.14µs
@: 2.12

Rx ENABLE

Rx BASEBAND OUTPUT

µs

MAX2852 toc44

D: 112mV
@: 104mV

Rx BASEBAND

OUTPUT

0.1V/div

180

150

120

90

60

30

RXBB_I

50mV/div

RXBB_Q

500mV/div

Rx LNA SETTLING RESPONSE

(MAX - 32dB TO MAX GAIN STEP)

CH1 RMS: 155mV

GAIN-CONTROL

TOGGLE

0V

D: 130mv
@: 132mv

200ns/div

HISTOGRAM: Rx I/Q PHASE IMBALANCE

0

-2.0000

SAMPLES = 3413, AVG = -0.015deg, STDEV = 0.042dB

0

MAX2852 toc39

MAX2852 toc42

2.0000

POWER-ON DC OFFSET CANCELLATION

WITHOUT INPUT SIGNAL

Rx ENABLE

TURN-ON
TRANSIENT

MAX2852 toc45

-15.0000

SAMPLES = 3413, AVG = -0.5mV, STDEV = 2.14mV

0

15.0000

______________________________________________________________________________________ 13

1µs/div

400ns/div

5GHz Receiver

Typical Operating Characteristics (continued)

(VCC = 2.8V, f
balun, T

A

7.0

6.5

MAX2852

6.0

5.5

5.0

LO FREQUENCY (GHz)

4.5

4.0
0 2.5

LO PHASE NOISE AT 5900MHz AND HOT

-50

-60

-70

-80

-90

-100

-110

PHASE NOISE (dBc/Hz)

-120

-130

-140

-150
1k 10M

= 5.35GHz, f

LO

= 40MHz, CS = high, SCLK = DIN = low, RF BW = 20MHz, Tx output at 50I unbalanced output of

REF

= +25NC, using the MAX2852 Evaluation Kit.)

LO FREQUENCY vs. DIFFERENTIAL

TUNE VOLTAGE AT T

DIFFERENTIAL TUNE VOLTAGE (V)

TEMPERATURE

OFFSET FREQUENCY (Hz)

= +25°C

A

600

500

MAX2852 toc46

400

300

LO GAIN (MHz/V)

200

100

2.01.51.00.5

0

0 2.5

AUTOMATIC VCO SUB-BAND SELECTION)

25kHz

MAX2852 toc49

FREQUENCY (5kHz/div)

-25kHz
0s 3.99ms

CHANNEL SWITCHING FREQUENCY
SETTLING (4900MHz TO 5900MHz,

MANUAL VCO SUB-BAND SELECTION)

25kHz

LO GAIN vs. DIFFERENTIAL

TUNE VOLTAGE AT TA = +25°C

2.01.51.00.5

DIFFERENTIAL TUNE VOLTAGE (V)

CHANNEL SWITCHING FREQUENCY
SETTLING (4900MHz TO 5900MHz,

400µs/div

MANUAL VCO SUB-BAND SELECTION)

25kHz

LO PHASE NOISE AT 5350MHz AND ROOM

TEMPERATURE

-50

-60

MAX2852 toc47

-70

-80

-90

-100

-110

PHASE NOISE (dBc/Hz)

-120

-130

-140

-150
1k 10M

OFFSET FREQUENCY (Hz)

CHANNEL SWITCHING FREQUENCY
SETTLING (5900MHz TO 4900MHz,

AUTOMATIC VCO SUB-BAND SELECTION)

25kHz

MAX2852 toc50

FREQUENCY (5kHz/div)

-25kHz
0s 3.99ms

CHANNEL SWITCHING FREQUENCY

SETTLING (5900MHz TO 4900MHz,

400µs/div

MAX2852 toc48

MAX2852 toc51

MAX2852 toc52

FREQUENCY (5kHz/div)

-25kHz
0s 99.22µs

10µs/div

FREQUENCY (5kHz/div)

-25kHz
0s 99.22µs

10µs/div

14 _____________________________________________________________________________________

MAX2852 toc53

5GHz Receiver

Pin Configuration

TOP VIEW

MAX2852

V

CC_XTAL

ENABLE

V

CC_BB1

XTAL

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

V

V

N.C.

CC_DIG

CPOUT+

CPOUT-

V

DOUT

CLKOUT

51 50 49 48 47 46 45 44

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

CC

67

CC

68

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

N.C.

GND

CC

V

CCVCC

V

BYP_VCO

GND_VCO

CC

V

GND

CC_VCO

V

RSSI

43 42 41 40 39 38 37 36 35

RXBBQ-

RXBBI-

RXBBQ+

MAX2852

CC

CC

V

V

N.C.

N.C.

RXBBI+

CCVCC

V

N.C.

N.C.

N.C.

GND

N.C.

CC

V

N.C.

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

CC_UCX

V

DIN

SCLK

CS

TXBBQ-

TXBBQ+

TXBBI-

TXBBI+

V

CC_BB2

V

CC_MXR

RXRF+

RXRF-

V

CC_LNA

N.C.

TXRF-

TXRF+

N.C.

GND

TQFN

10mm x 10mm

______________________________________________________________________________________ 15

5GHz Receiver

Pin Description

PIN NAME FUNCTION

1, 2, 5, 6, 9,

10, 12, 13,

16, 66, 67

3, 8, 11, 14,

MAX2852

19, 22,

35–38, 54,

56–59, 61–65,

68

4, 7, 15, 18 GND Ground

17 V

20 TXRF­21 TXRF+
23 V
24 RXRF­25 RXRF+
26 V
27 V
28 TXBBI+
29 TXBBI­30 TXBBQ+
31 TXBBQ­32
33 SCLK Serial-Clock Logic Input of 4-Wire Serial Interface
34 DIN Data Logic Input of 4-Wire Serial Interface
39 RXBBI+
40 RXBBI­41 RXBBQ+
42 RXBBQ­43 RSSI Receiver Signal Strength Indicator Output
44 V

45 BYP_VCO

46 GND_VCO VCO Ground
47 CPOUT+
48 CPOUT­49 V
50 DOUT Data Logic Output of 4-Wire Serial Interface
51 CLKOUT Reference Clock Buffer Output
52 V

V

CC

N.C. No Connection

CC_UCX

CC_LNA

CC_MXR

CC_BB2

CS

CC_VCO

CC_DIG

CC_XTAL

Supply Voltage

Transmitter Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.

Transmitter Differential Outputs. These pins are in open-collector configuration. They hould be
biased at supply voltage with differential impedance terminated at 300W.

Receiver LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.

Receiver LNA Differential Inputs. Inputs are DC-coupled and biased internally at 1.2V.

Receiver Downconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver Baseband Supply Voltage 2. Bypass with a capacitor as close as possible to the pin.

Transmitter Baseband I-Channel Differential Inputs

Transmitter Baseband Q-Channel Differential Inputs

Chip-Select Logic Input of 4-Wire Serial Interface

Receiver Baseband I-Channel Differential Outputs

Receiver Baseband Q-Channel Differential Outputs

VCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.

On-Chip VCO Regulator Output Bypass. Bypass with an external 1FF capacitor to GND_VCO
with minimum PCB trace. Do not connect other circuitry to this pin.

Differential Charge-Pump Outputs. Connect the frequency synthesizer’s loop filter between
CPOUT+ and CPOUT- (see the Typical Operating Circuit).

Digital Block Supply Voltage. Bypass with a capacitor as close as possible to the pin.

Crystal Oscillator Supply Voltage. Bypass with a capacitor as close as possible to the pin.

16 _____________________________________________________________________________________

5GHz Receiver

Pin Description (continued)

PIN NAME FUNCTION

53 XTAL Crystal Oscillator Base Input. AC-couple crystal unit to this pin.
55 ENABLE Enable Logic Input
60 V

— EP

CC_BB1

Table 1. Operating Modes

MODE

SHUTDOWN

CLKOUT

STANDBY

Rx

Tx CALIBRATION

RF LOOPBACK

BASEBAND
LOOPBACK

*CLKOUT signal is active independent of SPI, and is only dependent on the ENABLE pin.

Receiver Baseband Supply Voltage 1. Bypass with a capacitor as close as possible to the pin.

Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat
dissipation. Do not share with any other pin grounds and bypass capacitors’ ground.

MODE-CONTROL

LOGIC INPUTS

SPI MAIN

ENABLE PIN

0 XXX Off Off Off Off None
1 000 Off Off Off On None
1 001 Off Off On On None
1 010 On Off On On None

1 100 Off On On On

1 101

1 11X

ADDRESS 0,

D4:D2

Rx PATH Tx PATH LO PATH CLKOUT*

On (except

LNA)

On (except

RXRF)

CIRCUIT BLOCK STATES

On On On RF loopback

Off On On

Calibration

Sections On

AM detector

+ Rx I/Q buffers

Tx 4 baseband

buffer

MAX2852

Detailed Description

Modes of Operation

The modes of operation for the MAX2852 are shutdown,
clockout, standby, receive, transmit calibration, RF
loopback, and baseband loopback. See Table 1 for a
summary of the modes of operation. The logic input pin
ENABLE (pin 55) and SPI Main address 0 D4:D2 control
the various modes.

Shutdown Mode

The MAX2852 features a low-power shutdown mode. All
circuit blocks are powered down, except the 4-wire serial
bus and its internal programmable registers.

Clockout Mode

In clockout mode, only the crystal oscillator signal is
active at the CLKOUT pin. The rest of the transceiver is
powered down.

______________________________________________________________________________________ 17

Standby Mode

In standby mode, PLL, VCO, and LO generation are on.
Rx mode can be quickly enabled from this mode. Other
blocks may be selectively enabled in this mode.

Receive (Rx) Mode

In receive mode, all Rx circuit blocks are powered on
and active. Antenna signal is applied; RF is downcon­verted, filtered, and buffered at Rx baseband I and Q
outputs.

Transmit Calibration

In transmit calibration mode, all Tx circuit blocks are
powered on and active. The AM detector and receiver
I/Q channel buffers are also on. Output signals are
routed to Rx baseband I and Q outputs.

5GHz Receiver

The AM detector multiplies the Tx RF output signal with
itself. The self-mixing product of the wanted sideband
becomes DC voltage and is filtered on-chip. The mixing
product between wanted sideband and the carrier leak­age forms Ftone at Rx baseband output. The mixing
product between the wanted sideband and the unwant­ed sideband forms 2Ftone at Rx baseband output.

MAX2852

In RF loopback mode, part of the Rx and Tx circuit
blocks (except the LNA) are powered on and active. The
transmitter 4 I/Q input signal is upconverted to RF, and
the output of the transmitter is fed to the receiver down­converter input. Output signals are delivered to receiver
4 baseband I/Q outputs. The I/Q lowpass filters in the
transmitter signal path are bypassed.

Baseband Loopback

In baseband loopback mode, part of the Rx and Tx
baseband circuit blocks are powered and active. The
transmitter 4 IQ input signal is routed to receiver lowpass
filter input. Output signals are delivered to receiver 4
baseband I/Q outputs.

Power-On Sequence

Set the ENABLE pin to VCC for 2ms to start the crystal
oscillator. Program all SPI addresses according to rec­ommended values. Set SPI Main address 0 D4:D2 from
000 to 001 to engage standby mode. To lock the LO
frequency, the user can set SPI in order of Main address
15, Main address 16, and then Main address 17 to trig­ger VCO sub-band autoacquisition; the acquisition will
take 2ms. After the LO frequency is locked, set SPI Main
address 0 D4:D2 = 010 and 011 for Rx and Tx operat­ing modes, respectively. Before engaging Rx mode, set
Main address 5 D1 = 1 to allow fast DC offset settling.
After engaging Rx mode and Rx baseband DC offset
settles, the user can set Main address 5 D1 = 0 to com­plete Rx DC offset cancellation.

RF Loopback

Programmable Registers and

4-Wire SPI Interface

The MAX2852 includes 60 programmable 16-bit reg­isters. The most significant bit (MSB) is the read/write
selection bit (R/W in Figure 1). The next 5 bits are register
address (A4:A0 in Figure 1). The 10 least significant bits
(LSBs) are register data (D9:D0 in Figure 1). Register
data is loaded through the 4-wire SPI/MICROWIRE™­compatible serial interface. MSB of data at the DIN pin
is shifted in first and is framed by CS. When CS is low,
the clock is active, and input data is shifted at the rising
edge of the clock at SCLK pin. At the CS rising edge,
the 10-bit data bits are latched into the register selected
by address bits. See Figure 1. To support more than a
32-register address using a 5-bit wide address word,
the bit 0 of address 0 is used to select whether the 5-bit
address word is applied to the main address or local
address. The register values are preserved in shutdown
mode as long as the power-supply voltage is maintained.
There is no power-on SPI register self-reset functionality
in the MAX2852, so the user must program all register
values after power-up. During the read mode, register
data selected by address bits is shifted out to the DOUT
pin at the falling edges of the clock.

MICROWIRE is a trademark of National Semiconductor Corp.

18 _____________________________________________________________________________________

5GHz Receiver

MAX2852

t

CSW

CS

SCLK

DIN

(SPI WRITE)

DIN

(SPI READ)

DOUT

(SPI READ)

t

CSO

t

CSS

t

t

DS

A0 D9 D0A4R/W

A4R/W A0 D9 D0 DON’T CARE

DON’T CARE D9

CH

t

DH

t

CL

t

D

t

CSH

t

CS1

DON’T CARE

D0 DON’T CARE

Figure 1. 4-Wire SPI Serial-Interface Timing Diagram

SPI Register Definition

(All values in the register summary table are typical numbers. The MAX2852 SPI does not have a power-on-default self­reset feature; the user must program all SPI addresses for normal operation. Prior to use of any untested settings, contact
the factory.)

Table 2. Register Summary

READ/WRITE AND ADDRESS DATA

REGISTER

Main0_

D0

Main0 0 00000

Main1 0 00001

Main2 0 00010

Main3 0 00011

WRITE (W)/

A4:A0

READ (R)

W/R RESERVED RESERVED RESERVED RESERVED RESERVED MODE<2:0> RFBW M/L_SEL

Default 0 1 0 0 0 0 0 0 1 0

W/R RESERVED RESERVED LNA_GAIN<2:0> RX_VGA<4:0>

Default 0 0 1 1 1 1 1 1 1 1

W/R RESERVED RESERVED RESERVED LNA_BAND<1:0> RESERVED RESERVED RESERVED RESERVED RESERVED

Default 0 1 1 0 1 0 0 0 0 0

W RESERVED RESERVED

R RESERVED RESERVED RESERVED TS_READ<4:0>

Default 0 0 0 0 0 0 0 0 0 0

______________________________________________________________________________________ 19

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TS_EN TS_TRIG

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

5GHz Receiver

Table 2. Register Summary (continued)

READ/WRITE AND ADDRESS DATA

REGISTER

MAX2852

Main10 0 01010 Reserved 0 0 0 0 0 0 0 0 0 0

Main11 0 01011

Main13 0 01101 Reserved 0 0 0 0 0 0 0 0 0 0

Main14 0 01110

Main15 0 01111

Main16 0 10000

Main17 0 10001

Main18 0 10010

Main19 0 10011

Main20 0 10100 Reserved 0 1 1 1 1 0 1 0 1 0

Main21 0 10101

Main22 0 10110 Reserved 0 1 1 0 1 1 1 0 0 0

Main23 0 10111 Reserved 0 0 0 1 1 0 0 1 0 1

Main24 0 11000 Reserved 1 0 0 1 0 0 1 1 1 1

Main25 0 11001 Reserved 1 1 1 0 1 0 1 0 0 0

Main26 0 11010 Reserved 0 0 0 0 0 1 0 1 0

Main27 0 11011

Main28 0 11100

Main0_

D0

Main4 0 00100 Reserved 1 1 0 0 0 1 1 1 0 0

Main5 0 00101

Main6 0 00110 Reserved 1 1 1 1 1 0 1 0 0 0

Main7 0 00111 Reserved 0 0 0 0 1 0 0 1 0 0

Main8 0 01000 W/R 0 0 0 0 0 0 0 0 0 0

Main9 0 01001

A4:A0

WRITE (W)/

READ (R)

W/R RESERVED RSSI_MUX_SEL<2:0> RESERVED RESERVED RESERVED RESERVED RXHP RESERVED

Default 0 0 0 0 0 0 0 0 0 0

W/R TX_GAIN<5:0> RESERVED RESERVED RESERVED RESERVED

Default 0 0 0 0 0 0 1 1 1 1

W/R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

Default 0 0 0 1 1 0 1 1 0 0

W/R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED DOUT_SEL RESERVED

Default 0 1 0 1 1 0 0 0 0 0

W/R

Default 1 0 0 1 0 0 0 0 1 0

W/R SYN_CONFIG_F<19:10>

Default 1 1 1 0 0 0 0 0 0 0

W/R SYN_CONFIG_F<9:0>

Default 0 0 0 0 0 0 0 0 0 0

W/R RESERVED RESERVED XTAL_TUNE<7:0>

Default 0 0 1 0 0 0 0 0 0 0

W/R

Read VAS_ADC<2:0> VCO_BAND<5:0>

Default 0 0 0 1 0 1 1 1 1 1

Read RESERVED RESERVED DIE_ID<2:0> RESERVED RESERVED RESERVED RESERVED RESERVED

Default 0 0 1 0 1 1 1 1 1 1

W/R

Default 0 1 1 0 0 0 0 0 0 0

W/R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

Default 0 0 0 1 1 0 0 0 1 1

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VAS_

TRIG_EN

RESERVED

DIE_ID_

READ

RESERVED SYN_CONFIG_N<6:0>

VAS_

RESERVED

RESERVED RESERVED RESERVED

RELOCK_

SEL

VAS_

MODE

VAS_VCO_

READ

RESERVED RESERVED RESERVED RESERVED RESERVED

VAS_SPI<5:0>

1

20 _____________________________________________________________________________________

5GHz Receiver

Table 2. Register Summary (continued)

READ/WRITE AND ADDRESS DATA

REGISTER

Main29 0 11101 Reserved 0 0 0 0 0 0 0 0 0 0

Main30 0 11110 Reserved 0 0 0 0 0 0 0 0 0 0

Main31 0 11111 Reserved 0 0 0 0 0 0 0 0 0 0

Local1 1 00001 Reserved 0 0 0 0 0 0 0 0 0 0

Local2 1 00010 Reserved 0 0 0 0 0 0 0 0 0 0

Local3 1 00011 Reserved 0 0 0 0 0 0 0 0 0 0

Local4 1 00100 Reserved 1 1 1 0 0 0 0 0 0 0

Local5 1 00101 Reserved 0 0 0 0 0 0 0 0 0 0

Local6 1 00110 Reserved 0 0 0 0 0 0 0 0 0 0

Local7 1 00111 Reserved 0 0 0 0 0 0 0 0 0 0

Local8 1 01000 Reserved 0 1 1 0 1 0 1 0 1 0

Local9 1 01001 Reserved 0 1 0 0 0 1 0 1 0 0

Local10 1 01010 Reserved 1 1 0 1 0 1 0 1 0 0

Local11 1 01011 Reserved 0 0 0 1 1 1 0 0 1 1

Local12 1 01100 Reserved 0 0 0 0 0 0 0 0 0 0

Local13 1 01101 Reserved 0 0 0 0 0 0 0 0 0 0

Local14 1 01110 Reserved 0 0 0 0 0 0 0 0 0 0

Local15 1 01111 Reserved 0 0 0 0 0 0 0 0 0 0

Local16 1 10000 Reserved 0 0 0 0 0 0 0 0 0 0

Local17 1 10001 Reserved 0 0 0 0 0 0 0 0 0 0

Local18 1 10010 Reserved 0 0 0 0 0 0 0 0 0 0

Local19 1 10011 Reserved 0 0 0 0 0 0 0 0 0 0

Local20 1 10100 Reserved 0 0 0 0 0 0 0 0 0 0

Local21 1 10101 Reserved 0 0 0 0 0 0 0 0 0 0

Local22 1 10110 Reserved 0 0 0 0 0 0 0 0 0 0

Local23 1 10111 Reserved 0 0 0 0 0 0 0 0 0 0

Local24 1 11000 Reserved 0 0 1 1 0 0 0 1 0 0

Local25 1 11001 Reserved

Local26 1 11010 Reserved 0 1 0 1 1 0 0 1 0 1

Local27 1 11011

Local28 1 11100 Reserved 0 0 0 0 0 0 0 1 0 0

Local31 1 11111 Reserved 0 0 0 0 0 0 0 0 0 0

Main0_

D0

A4:A0

WRITE (W)/

READ (R)

W/R RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

Default 0 0 0 0 0 0 0 0 0 0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 1 0 1 0 1 1

TX_AMD_

BB_GAIN

TX_AMD_RF_GAIN

<1:0>

MAX2852

______________________________________________________________________________________ 21

5GHz Receiver

Table 3. Main Address 0: (A4:A0 = 00000)

BIT NAME

RESERVED D9:D5 Reserved bits; set to default

MAX2852

MODE<2:0> D4:D2

RFBW D1

M/L_SEL D0

BIT LOCATION

(D0 = LSB)

DESCRIPTION

IC Operating Mode Select

000 = Clockout (default)
001 = Standby
010 = Rx
011 = Do not use
100 = Tx calibration
101 = RF loopback
11x = Baseband loopback

RF Bandwidth

0 = 20MHz
1 = 40MHz (default)

Main or Local Address Select

0 = Main registers (default)
1 = Local registers

Table 4. Main Address 1: (A4:A0 = 00001, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D8 Reserved bits; set to default

LNA_GAIN<2:0> D7:D5

BIT LOCATION

(D0 = LSB)

DESCRIPTION

LNA Gain Control

Active when Rx channel is selected by corresponding
RX_PATH_UNMASK<5:1> bits in Main address 6 D9:D5.
000 = Maximum - 40dB
001 = Maximum - 32dB
100 = Maximum - 24dB
101 = Maximum - 16dB
110 = Maximum - 8dB
111 = Maximum gain (default)

Rx VGA Gain Control

Active when Rx channel is selected by corresponding
RX_PATH_UNMASK<5:1> bits in Main address 6 D9:D5.
00000 = Minimum gain

VGA_GAIN<4:0> D4:D0

22 _____________________________________________________________________________________

00001 = Minimum + 2dB
…
01110 = Minimum + 28dB
01111 = Minimum + 30dB
…
1xxxx = Minimum + 30dB (default)

5GHz Receiver

Table 5. Main Address 2: (A4:A0 = 00010, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D7 Reserved bits; set to default

LNA_BAND<1:0> D6:D5

RESERVED D4:D0 Reserved bits; set to default

BIT LOCATION

(D0 = LSB)

DESCRIPTION

LNA Frequency Band Switch

00 = 4.9GHz~5.2GHz
01 = 5.2GHz~5.5GHz (default)
10 = 5.5GHz~5.8GHz
11 = 5.8GHz~5.9GHz

Table 6. Main Address 3: (A4:A0 = 00011, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D8 Reserved bits; set to default

TS_EN D7

TS_TRIG D6

RESERVED D5 Reserved bits; set to default

TS_READ<4:0> D4:D0

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Temperature Sensor Enable

0 = Disable (default)
1 = Enable except shutdown or clockout mode

Temperature Sensor Reading Trigger

0 = Not trigger (default)
1 = Trigger temperature reading

SPI readback only.
Temperature sensor reading.

MAX2852

Table 7. Main Address 5: (A4:A0 = 00101, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9 Reserved bits; set to default

RSSI_MUX_SEL<2:0> D8:D6

RESERVED D5:D2 Reserved bits, set to default

RXHP D1

RESERVED D0 Reserved bits; set to default

______________________________________________________________________________________ 23

BIT LOCATION

(D0 = LSB)

DESCRIPTION

RSSI Output Select

000 = Baseband RSSI (default)
001 = Do not use
010 = Do not use
011 = Do not use
100 = Rx RF detector
101 = Do not use
110 = Do not use
111 = Do not use

Rx VGA Highpass Corner Select after Rx Turn-On

RXHP starts at 1 during Rx gain adjustment, and set to 0 after gain is
adjusted.
0 = 10kHz highpass corner after Rx gain is adjusted (default)
1 = 600kHz highpass corner during Rx gain adjustment

5GHz Receiver

Table 8. Main Address 9: (A4:A0 = 01001, Main Address 0 D0 = 0)

BIT NAME

TX_GAIN<5:0> D9:D4

MAX2852

RESERVED D3:D0 Reserved bits; set to default

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Tx VGA Gain Control

Tx channel is selected by Main address 9 D3:D0.
000000 = Minimum gain (default)
…
111111 = Minimum gain + 31.5dB

Table 9. Main Address 14: (A4:A0 = 01110, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D2 Reserved bits; set to default

DOUT_SEL D1

RESERVED D0 Reserved bits; set to default

BIT LOCATION

(D0 = LSB)

DESCRIPTION

DOUT Pin Output Select

0 = PLL lock detect (default)
1 = SPI readback

Table 10. Main Address 15: (A4:A0 = 01111, Main Address 0 D0 = 0)

BIT NAME

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Enable VCO Sub-Band Acquisition Triggered by SYN_CONFIG_F<9:0>

VAS_TRIG_EN D9

RESERVED D8:D7 Reserved bits; set to default

SYN_CONFIG_N<6:0> D6:D0

(Main Address 17) Programming

0 = Disable for small frequency adjustment (i.e., ~100kHz)
1 = Enable for channel switching (default)

Integer Divide Ratio

1000010 = Default

Table 11. Main Address 16: (A4:A0 = 10000, Main Address 0 D0 = 0)

BIT NAME

SYN_CONFIG_F<19:10> D9:D0

24 _____________________________________________________________________________________

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Fractional Divide Ratio LSBs

0000000000 = Default

5GHz Receiver

Table 12. Main Address 17: (A4:A0 = 10001, Main Address 0 D0 = 0)

MAX2852

BIT NAME

SYN_CONFIG_F<19:10> D9:D0

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Fractional Divide Ratio LSBs

0000000000 = Default

Table 13. Main Address 18: (A4:A0 = 10010, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D8 Reserved bits; set to default

XTAL_TUNE<7:0> D7:D0

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Crystal Oscillator Frequency Tuning

00000000 = Minimum frequency
10000000 = Default
11111111 = Maximum frequency

Table 14. Main Address 19: (A4:A0 = 10011, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D8 Reserved bits; set to default

VAS_RELOCK_SEL D7

VAS_MODE D6

VAS_SPI<5:0> D5:D0

VAS_ADC<2:0>

(Readback Only)

VCO_BAND<5:0>

(Readback Only)

BIT LOCATION

(D0 = LSB)

D8:D6

D5:D0

DESCRIPTION

VAS Relock Select

0 = Start at sub-band selected by VAS_SPI<5:0> (Main address 19 D5:D0)
(default)
1 = Start at current sub-band

VCO Sub-Band Select

0 = By VAS_SPI<5:0> (Main address 19 D5:D0)
1 = By on-chip VCO autoselect (VAS) (default)

VCO Autoselect Sub-Band Input

Select VCO sub-band when VAS_MODE (Main address 19 D6) = 0.
Select initial VCO sub-band for autoacquisition when VAS_MODE = 1.
000000 = Minimum frequency sub-band
…
011111 = Default
…
111111 = Maximum frequency sub-band

Read VCO Autoselect Tune Voltage ADC Output

Active when VCO_VAS_RB (Main address 27 D5) = 1.
000 = Lower than lock range and at risk of unlock
001 = Lower than acquisition range and maintain lock
010 or 101 = Within acquisition range and maintain lock
110 = Higher than acquisition range and maintain lock
111 = Higher than lock range and at risk of unlock

Read the Current Acquired VCO Sub-Band by VCO Autoselect

Active when VCO_VAS_RB (Main address 27 D5) = 1.

______________________________________________________________________________________ 25

5GHz Receiver

Table 15. Main Address 21: (A4:A0 = 10101, Main Address 0 D0 = 0)

BIT NAME

RESERVED D9:D0 Reserved bits; set to default

DIE_ID<2:0>

MAX2852

(Readback Only)

BIT LOCATION

(D0 = LSB)

D7:D5

DESCRIPTION

Read Revision ID at Main Address 21 D7:D5

Active when DIE_ID_READ (Main address 27 D9) = 1.
000 = Pass1
001 = Pass2
…

Table 16. Main Address 27: (A4:A0 = 11011, Main Address 0 D0 = 0)

BIT NAME

DIE_ID_READ D9

RESERVED D8:D6 Reserved bits, set to default

VAS_VCO_READ D5

RESERVED D4:D0 Reserved bits; set to default

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Die ID Readback Select

0 = Main address 21 D9:D0 reads its own values (default)
1 = Main address 21 D7:D5 reads revision ID

VAS ADC and VCO Sub-Band Readback Select

0 = Main address 19 D9:D0 reads its own values (default)
1 = Main address 19 D8:D6 reads VAS_ADC<2:0>; Main address 19 D5:D0
reads VCO_BAND<5:0>

Table 17. Local Address 27: (A4:A0 = 11011, Main Address 0 D0 = 1)

BIT NAME

RESERVED D9:D3 Reserved bits, set to default

TX_AMD_BB_GAIN D2

TX_AMD_RF_GAIN D1:D0

Chip Information

PROCESS: BiCMOS

BIT LOCATION

(D0 = LSB)

DESCRIPTION

Tx Calibration AM Detector Baseband Gain

0 = Minimum gain (default)
1 = Minimum gain + 5dB

Tx Calibration AM Detector RF Gain

00 = Minimum gain (default)
01 = Minimum gain + 14dB rise at output
1x = Minimum gain + 28dB rise at output

Package Information

For the latest package outline information and land pat­terns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suf­fix character, but the drawing pertains to the package
regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

68 TQFN-EP T6800+2

26 _____________________________________________________________________________________

21-0142

5GHz Receiver

Typical Operating Circuit

MAX2852

0.1µF

1nF

1nF

N.C.

VCCVCCN.C.

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

V

CC

V

CC_UCX

1

V

CC

2

N.C

3

GND

4

V

CC

5

V

CC

6

GND

7

N.C.

8

V

CC

9

V

CC

10

N.C.

11

V

CC

12

V

CC

13

N.C.

14

GND

15

V

CC

16

17

AMD+/-

AM

DETECTOR

TXRF+/-

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

N.C.

GND

TXRF+

1nF

1nF

1nF

1nF

1nF

1nF

1nF

1nF

1nF

N.C.

N.C.

N.C.

MAX2852

0˚

90˚

TXRF+/-

N.C.

TXRF-

RXRF-

CC_LNA

V

1nF 10nF 100nF

10nF

CC_BB1

N.C

V

N.C.

N.C.

N.C.

N.C.

ENABLE

CRYSTAL OSCILLATOR/BUFFER

TXBBQ+

BB

RSSI

AMD+/-

TXBBQ-

INTERFACE

RF

RSSI

RXRF+

CC_BB2

CC_MXR

V

V

TXBBI+

0˚90˚

TXBBI-

N.C.

XTAL

PHASE-LOCKED LOOP

DOUT

SERIAL

CS

SCLK

RSSI
MUX

100pF

CC_XTAL

V

DIN

1µF

CLKOUT

51

DOUT

50

V

CC_DIG

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

CPOUT-

CPOUT+

GND_VCO

BYP_VCO

V

CC_VCO

RSSI

RXBBQ-

RXBBQ+

RXBBI-

RXBBI+

N.C.

N.C.

N.C.

N.C.

390

I

33pF

I

390

1nF

10nF

PLL LOOP FILTER

2.2nF

1µF

4.3nH

1.0pF 1.0nF

CC_UCX

V

TXRF

OUTPUT

2.4nH

1.0pF 20pF

1.3nH

RXRF

OUTPUT

______________________________________________________________________________________ 27

5GHz Receiver

Revision History

REVISION

NUMBER

0 10/09 Initial release —
1 3/10 Modified EC table to support single-pass room test flow 2, 3, 5, 8

REVISION

DATE

MAX2852

DESCRIPTION

PAGES

CHANGED

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.

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©

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