The MAX2851 is a single-chip, 5-channel RF receiver IC
designed for 5GHz wireless HDMI™ applications. The
IC includes all circuitry required to implement the complete 5-channel MIMO RF receiver function and crystal
oscillator, providing a fully integrated receive path, VCO,
frequency synthesis, and baseband/control interface. It
includes a fast-settling sigma-delta RF fractional synthesizer with 76Hz frequency programming step size. The
IC also integrates on-chip I/Q amplitude and phase-error
calibration circuits. The receiver includes both an inchannel RSSI and also an RF RSSI.
On-chip monolithic filters are included for receiver I/Q
baseband signal channel selection, for supporting both
20MHz and 40MHz RF channels. The baseband filtering and Rx signal paths are optimized to meet stringent
WHDI requirements. The downconverter local oscillator
is coherent among all the receiver channels.
The reverse-link control channel uses an on-chip 5GHz
OFDM transmitter. It shares the RF synthesizer and LO
generation circuit with the MIMO receivers. Dynamic
on/off control of the external PA is implemented with
programmable precision voltage. An analog mux routes
external PA power-detect voltage to the RSSI pin.
The MIMO receiver chip is housed in a small 68-pin
TQFN leadless plastic package with exposed paddle.
Applications
5GHz Wireless HDMI (WHDI™)
5GHz FDD Backhaul and WiMAX™
5GHz MIMO Receiver Up to Five Spatial Streams
5GHz Beam Steering Receiver
Features
S 5GHz, 5x MIMO Downlink Receivers, Single-Uplink
IEEE 802.11a Transmitter
S 4900MHz to 5900MHz Frequency Range
S Coherent LO Among Receivers
S 4.5dB Rx Noise Figure
S 70dB Rx Gain Control Range with 2dB Step Size,
Digitally Controlled
S 60dB Dynamic Range Receiver RSSI
S RF Wideband Receiver RSSI
S Programmable 20MHz/40MHz Rx I/Q Lowpass
Channel Filters
S -5dBm Transmit Power (54Mbps OFDM)
S 31dB Tx Gain Control Range with 0.5dB Step Size,
Digitally Controlled
S Tx/Rx I/Q Error and LO Leakage Detection and
Adjustment
S Programmable 20MHz/40MHz Tx I/Q Lowpass
Anti-Aliasing Filter
S Analog Mux for PA Power Detect
S PA On/Off Control
S Sigma-Delta Fractional-N PLL with 76Hz
Resolution
S Monolithic Low-Noise VCO with -35dBc Integrated
Phase Noise
S 4-Wire SPIK
S I/Q Analog Baseband Interface
S Digital Tx/Rx Mode Control
S On-Chip Digital Temperature Sensor Readout
S Complete Baseband Interface
S Digital Tx/Rx Mode Control
S +2.7V to +3.6V Supply Voltage
S Small 68-Pin TQFN Package (10mm x 10mm)
Digital Interface
MAX2851
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
HDMI is a trademark of HDMI Licensing, LLC.
WHDI is a trademark of WHDI Special Interest Group.
WiMAX is a trademark of the WiMAX Forum.
SPI is a trademark of Motorola, Inc.
GND ...................................................................-0.3V to +3.9V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Operating conditions unless otherwise specified: V
mode, CS = high, SCLK = DIN = low, transmitter in maximum gain. Power matching and termination for the differential RF output
pins using the Typical Operating Circuit; 100mV
in transmit mode. Typical values measured at V
PA control pins open circuit, V
PARAMETERCONDITIONSMINTYPMAXUNITS
Supply Voltage 2.73.6V
Supply Current
Rx I/Q Output Common-Mode
Voltage
Tx Baseband Input CommonMode Voltage Operating Range
Tx Baseband Input Bias CurrentSource current1020
CC_PA_BIAS
Shutdown mode
Clockout only mode
with load = 10pF at
CLKOUT pin
Standby mode60
Transmit mode183212
Receive mode
Receive calibration
mode
Transmit calibration mode256
CC
is disconnected.) (Note 1)
= 2.7V to 3.6V, T
CC
differential I and Q signals applied to I and Q baseband inputs of transmitters
RMS
= 2.85V, TA = +25NC, LO freq = 5.35GHz. Channel bandwidth is set to 40MHz.
T
A
XTAL oscillator, CLKOUT2 is off3.7
XTAL oscillator, CLKOUT2 is on4.6
TCXO input, CLKOUT2 is off4.87.0
TCXO input, CLKOUT2 is on6.1
One receiver is on144184
Five receivers are on367458
One receiver is on248
Five receivers are on435517
Digital Inputs: ENABLE, CS, SCLK,
DIN to GND ........................................................-0.3V to +3.9V
Digital Outputs: DOUT, CLKOUT to GND ............-0.3V to +3.9V
Short-Circuit Duration
Analog Outputs ................................................................. 10s
Digital Outputs ................................................................... 10s
RF Input Power .............................................................. +10dBm
(Operating conditions unless otherwise specified: V
mode, CS = high, SCLK = DIN = low, transmitter in maximum gain. Power matching and termination for the differential RF output
pins using the Typical Operating Circuit; 100mV
in transmit mode. Typical values measured at V
PA control pins open circuit, V
PARAMETERCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS: ENABLE, SCLK, DIN, CS
Digital Input-Voltage High, V
Digital Input-Voltage Low, V
Digital Input-Current High, I
Digital Input-Current Low, I
LOGIC OUTPUTS: DOUT, CLKOUT
Digital Output-Voltage High, V
Digital Output-Voltage Low, V
Digital Output Voltage in
Shutdown Mode
CC_PA_BIAS
IH
IL
IH
IL
OH
OL
(Note 2)0.3V
Sourcing 1mA
Sinking 1mA0.4V
Sinking 1mAV
CC
is disconnected.) (Note 1)
= 2.7V to 3.6V, T
CC
differential I and Q signals applied to I and Q baseband inputs of transmitters
RMS
= 2.85V, TA = +25NC, LO freq = 5.35GHz. Channel bandwidth is set to 40MHz.
= -25NC to +85NC, ENABLE set according to operating
A
VCC -
0.4
-1+1
-1+1
-
V
CC
0.4
OL
V
FA
FA
V
V
MAX2851
AC ELECTRICAL CHARACTERISTICS—Rx MODE
(Operating conditions unless otherwise specified: VCC = 2.7V to 3.6V, TA = -25NC to +85NC, RF freq = 5.351GHz, LO freq = 5.35GHz.
Reference freq = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF_+ and RXRF_- differential
ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
load capacitance. RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
channel bandwidths of 40MHz.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
RECEIVER SECTION: RF INPUT TO I/Q BASEBAND LOADED OUTPUT
Includes 50I to 100I RF Balun and Matching
RF Input Frequency Range4.95.9GHz
Peak-to-Peak Gain Variation
Over RF Frequency Range at
One Temperature
RF Input Return LossAll LNA settings-6dB
Total Voltage Gain
RF Gain Steps Relative to
Maximum Gain
Baseband Gain Range
Baseband Gain Step2dB
RF Gain Change Settling Time
4.9GHz to 5.9GHz1.84.2dB
Maximum gain, Main address 1 D[7:0] = 1111111161.868
Minimum gain, Main address 1 D[7:0] = 00000000-2+6.9
Main address 1 D[7:5] = 110-8
Main address 1 D[7:5] = 101-16
Main address 1 D[7:5] = 001-32
Main address 1 D[7:5] = 000-40
From maximum baseband gain (Main address 1 D[3:0]
= 1111) to minimum baseband gain (Main address 1
D[3:0] = 0000)
Gain settling to within Q0.5dB of steady state, RXHP = 1
loaded with 10kI differential load resistance and 10pF
(Operating conditions unless otherwise specified: VCC = 2.7V to 3.6V, TA = -25NC to +85NC, RF freq = 5.351GHz, LO freq = 5.35GHz.
Reference freq = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF_+ and RXRF_- differential
ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
load capacitance. RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
channel bandwidths of 40MHz.) (Note 1)
PARAMETERCONDITIONSMINTYPMAXUNITS
Baseband Gain Change Settling
MAX2851
Time
DSB Noise Figure
Out-of-Band Input IP3
1dB Gain Desensitization by
Alternate Channel Blocker
Input 1dB Gain Compression
Gain settling to within Q0.5dB of steady state, RXHP = 1
Balun input referred,
integrated from 10kHz
to 9.5MHz at I/Q baseband output for 20MHz
RF bandwidth
Balun input referred,
integrated from 10kHz
to 19MHz at I/Q baseband output for 40MHz
RF bandwidth
20MHz RF channel,
two-tone jammers at
+25MHz and +48MHz
frequency offset with
-39dBm/tone
40MHz RF channel,
two-tone jammers at
+50MHz and +96MHz
frequency offset with
-39dBm/tone
Blocker at Q40MHz offset frequency for 20MHz RF
channel
Blocker at Q80MHz offset frequency for 40MHz RF
channel
Max RF gain (Main address 1 D[7:5] = 111)-34
Max RF gain - 8dB (Main address 1 D[7:5] = 110)-25
Max RF gain - 16dB (Main address 1 D[7:5] = 101)-18
Max RF gain - 32dB (Main address 1 D[7:5] = 001)-1
Maximum RF gain (Main
address 1 D[7:5] = 111)
Maximum RF gain - 16dB
(Main address 1 D[7:5] =
101)
Maximum RF gain (Main
address 1 D[7:5] = 111)
Maximum RF gain - 16dB
(Main address 1 D[7:5] =
101)
-65dBm wanted signal, RF
gain = max (Main address 1
D[7:0] = 11101001)
-49dBm wanted signal, RF
gain = max - 16dB (Main
address 1 D[7:0] = 10101001)
-45dBm wanted signal, RF
gain = max - 32dB (Main
address 1 D[7:0] = 00111111)
-65dBm wanted signal, RF
gain = max (Main address 1
D[7:0] = 11101001)
-49dBm wanted signal, RF
gain = max - 16dB (Main
address 1 D[7:0] = 10101001)
-45dBm wanted signal, RF
gain = max - 32dB (Main
address 1 D[7:0] = 00101001)
loaded with 10kI differential load resistance and 10pF
(Operating conditions unless otherwise specified: VCC = 2.7V to 3.6V, TA = -25NC to +85NC, RF freq = 5.351GHz, LO freq = 5.35GHz.
Reference freq = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF_+ and RXRF_- differential
ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
load capacitance. RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
channel bandwidths of 40MHz.) (Note 1)
Over passband frequency range, at any gain setting,
1dB compression point
Main address 0 D1 = 09.5
Main address 0 D1 = 119
Rejection at 30MHz offset frequency for 20MHz channel74
Rejection at 60MHz offset frequency for 40MHz channel69
Main address 5 D1 = 1600
Main address 5 D1 = 0, Main address 4 D3 = 0 (Note 3)0.1
50Fs after enabling receive mode and togging RXHP
from 1 to 0, averaged over many measurements if I/Q
noise voltage exceeds 1mV
ting, no input signal, 1-sigma value
LO frequency-75
2O LO frequency
3O LO frequency
4O LO frequency
Tx VGA gain at max (Main address 9 D[9:4] = 111111), Rx
VGA gain at max - 24dB (Main address 1 D[3:0] = 0101)
RMS
loaded with 10kI differential load resistance and 10pF
(Operating conditions unless otherwise specified: VCC = 2.7V to 3.6V, TA = -25NC to +85NC, RF freq = 5.351GHz, LO freq = 5.35GHz.
Reference freq = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at TXRF+ and TXRF- differential ports
using the Typical Operating Circuit; 100mV
DC-coupled). Typical values measured at V
PARAMETERCONDITIONSMINTYPMAXUNITS
TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS
Includes Matching and Balun Loss
MAX2851
RF Output Frequency Range4.95.9GHz
Peak-to-Peak Gain Variation
Over RF Band
Maximum Output Power
Output 1dB Gain Compression
Input 1dB Gain Compression
Gain Control Range2431.534dB
Gain Control Step0.5dB
RF Output Return Loss-3dB
Unwanted Sideband
Carrier Leakage
Tx I/Q Input Impedance (R || C)
Baseband Filter Stopband
Rejection
Tx Calibration Ftone Level
Tx Calibration RF Gain Step
Relative to Maximum Gain
Tx Calibration Baseband Gain
Step Relative to Maximum Gain
At one temperature0.71.55dB
20MHz OFDM signal conforming to spectral emission
mask and -34dB EVM
40MHz OFDM signal confirming to spectral emission
mask and -34dB EVM
Relative to typical maximum output power at 9.5MHz
input frequency
At 19MHz input frequency, over input common-mode
voltage between 0.5V and 1.1V
Over RF channel, RF frequency, baseband frequency,
and gain settings (Note 4)
Over RF channel, RF frequency, and gain settings
(Note 4)
Minimum differential resistance60kI
Maximum differential capacitance2pF
At 30MHz frequency offset for 20MHz RF channel86
At 60MHz frequency offset for 40MHz RF channel67
At Tx gain code (Main address 9 D[9:4]) = 100010 and
-15dBc carrier leakage (Local address 27 D[2:0] = 110
and Main address 1 D[3:0] = 0000)
Local address 27 D[1:0] = 01-14
Local address 27 D[1:0] = 00-28
Local address 27 D2 = 0-5dB
sine and cosine signal applied to I/Q baseband inputs of transmitter (differential
RMS
= 2.85V, TA = +25NC, channel bandwidths of 40MHz.) (Note 1)
(Operating conditions unless otherwise specified: VCC = 2.7V to 3.6V, TA = -25NC to +85NC, freq = 5.35GHz. Reference freq =
40MHz, ENABLE = high, CS = high, SCLK = DIN = low. Typical values measured at V
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
4-WIRE SERIAL INTERFACE TIMING (Figure 1)
SCLK Rising Edge to CS Falling
Edge Wait Time
Falling Edge of CS to Rising
Edge of First SCLK Time
DIN to SCLK Setup Timet
DIN to SCLK Hold Timet
SCLK Pulse-Width Hight
SCLK Pulse-Width Lowt
Last Rising Edge of SCLK to
Rising Edge of CS or Clock to
Load Enable Setup Time
CS High Pulse Width
Time Between Rising Edge of
CS and the Next Rising Edge of
SCLK
SCLK Frequencyf
Rise Timet
Fall Timet
Note 1: The MAX2851 is production tested at TA = +25NC, minimum/maximum limits at TA = +25NC are guaranteed by test unless
otherwise specified. Minimum/maximum limits at TA = -25NC and +85NC are guaranteed by design and characterization. There
is no power-on register settings self-reset; recommended register settings must be loaded after VCC is applied.
Note 2: Minimum/maximum limit is guaranteed by design and characterization.
Note 3: It is currently not recommended and not tested. For test coverage support, contact manufacturer.
Note 4: For optimal Rx and Tx quadrature accuracy over temperature, the user can utilize the Rx calibration and Tx calibration circuit
18V
19V
20RXRF521RXRF5+
23V
24RXBBI5+
25RXBBI526RXBBQ5+
27RXBBQ528TXBBI+
29TXBBI30TXBBQ+
31TXBBQ32RXBBI4+
33RXBBI434RXBBQ4+
35RXBBQ436
37SCLKSerial-Clock Logic Input of 4-Wire Serial Interface
38DINData Logic Input of 4-Wire Serial Interface
39RXBBI3+
40RXBBI341RXBBQ3+
42RXBBQ3-
CC_LNA2
CC_MXR1
CC_LNA3
CC_MXR2
CC_LNA4
V
CC_PA_
BIAS
CC_UCX
CC_LNA5
CC_BB2
CS
Receiver 2 LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver 2 LNA Differential Input. Input is DC-coupled and biased internally at 1.2V.
Receiver Downconverter Supply Voltage 1. Bypass with a capacitor as close as possible to the pin.
Receiver 3 LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver 3 LNA Differential Input. Input is DC-coupled and biased internally at 1.2V.
Receiver Downconverter Supply Voltage 2. Bypass with a capacitor as close as possible to the pin.
Receiver 4 LNA Differential Input. Input is DC-coupled and biased internally at 1.2V.
Receiver 4 LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmitter Differential Output. These pins are in open-collector configuration. These pins should
be biased at the supply voltage with differential impedance terminated at 300I.
External Power-Amplifier Voltage Bias and Detector Mux Supply Voltage. Bypass with a capacitor
as close as possible to the pin.
Transmitter Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver 5 LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver 5 LNA Differential Input. Input is DC-coupled and biased internally at 1.2V.
Receiver Baseband Supply Voltage 2. Bypass with a capacitor as close as possible to the pin.
Receiver 5 Baseband I-Channel Differential Output
Receiver 5 Baseband Q-Channel Differential Output
Transmitter Baseband I-Channel Differential Input
Transmitter Baseband Q-Channel Differential Input
Receiver 4 Baseband I-Channel Differential Output
Receiver 4 Baseband Q-Channel Differential Output
Active-Low Chip-Select Logic Input of 4-Wire Serial Interface
46CPOUT+
47CPOUT48V
49DOUTData Logic Output of 4-Wire Serial Interface
50CLKOUT2Reference Clock Buffer Output 2
51CLKOUTReference Clock Buffer Output
52V
53XTALCrystal Oscillator Base Input. AC-couple crystal unit to this pin.
54XTAL_CAPCrystal Oscillator Emitter Node
55RSSIReceiver Signal Strength Indicator Output
56RXBBI2+
57RXBBI258RXBBQ2+
59RXBBQ260V
61RXBBI1+
62RXBBI163RXBBQ1+
64RXBBQ165V
66RXRF1+
67RXRF168ENABLEEnable Logic Input
—EP
CC_VCO
CC_DIG
CC_XTAL
CC_BB1
CC_LNA1
VCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.
On-Chip VCO Regulator Output Bypass. Bypass with an external 1FF capacitor to GND_VCO with
minimum PCB trace. Do not connect other circuitry to this pin.
Differential Charge-Pump Output. Connect the frequency synthesizer’s loop filter between
CPOUT+ and CPOUT- (see the Typical Operating Circuit).
Digital Block Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Crystal Oscillator Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver 2 Baseband I-Channel Differential Output
Receiver 2 Baseband Q-Channel Differential Output
Receiver Baseband Supply Voltage 1. Bypass with a capacitor as close as possible to the pin.
Receiver 1 Baseband I-Channel Differential Output
Receiver 1 Baseband Q-Channel Differential Output
Receiver 1 LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver 1 LNA Differential Input. Input is DC-coupled and biased internally at 1.2V.
Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat
dissipation. Do not share with any other pin grounds and bypass capacitors’ ground.
Note 1: PA_BIAS pin can be kept active in nontransmit mode(s) by SPI programming.
Note 2: CLKOUT signal is active independent of SPI, and is only dependent on the ENABLE pin.
Note 3: CLKOUT2 signal can be enabled/disabled through SPI in all operating modes except shutdown mode.
The MAX2851 modes of operation are shutdown, clockout, standby, receive, transmit, transmitter calibration,
RF loopback, and baseband loopback. See Table 1 for
a summary of the modes of operation. The logic input pin
ENABLE (pin 68) and SPI Main address 0 D[4:2] control
the various modes.
Shutdown Mode
The MAX2851 features a low-power shutdown mode. All
circuit blocks are powered down, except the 4-wire serial
bus and its internal programmable registers.
Clockout Mode
In clockout mode, only the crystal oscillator signal is
active at the CLKOUT pin. The rest of the transceiver is
powered down.
Standby Mode
In standby mode, PLL, VCO, and LO generation are on.
Tx or Rx modes can be quickly enabled from this mode.
Other blocks can be selectively enabled in this mode
Receive (Rx) Mode
In receive mode, all Rx circuit blocks are powered on
and active. The antenna signal is applied; RF is downconverted, filtered, and buffered at the RXBB I and Q
outputs.
Transmit (Tx) Mode
In transmit mode, all Tx circuit blocks are powered on
and active. The external PA can be powered on through
the PA_BIAS pin after a programmable delay.
Transmit Calibration Mode
In transmit calibration mode, all Tx circuit blocks are
powered on and active. The AM detector and receiver
I/Q channel buffers are also on. Output signals are
routed to RXBB I and Q outputs.
The AM detector multiplies the Tx RF output signal with
itself. The self-mixing product of the wanted sideband
becomes DC voltage and is filtered on-chip. The mixing
product between wanted sideband and the carrier leakage forms Ftone at the Rx baseband output. The mixing
product between the wanted sideband and the unwanted sideband forms 2Ftone at the Rx baseband output.
As the Tx RF output is self-mixed at the AM detector,
the AM detector output responds differently to different
gain settings and power levels. When the Tx RF output
power changes by 1dB through Tx gain control, the AM
detector output changes by 2dB as both the wanted
sideband and carrier leakage (or unwanted sideband)
change by 1dB. When Tx RF output carrier leakage (or
unwanted sideband) changes by 1dB while the wanted
sideband output power is constant, the AM detector output changes by 1dB only.
In RF loopback mode, part of the Rx and Tx circuit
blocks except the LNA are powered on and active. The
transmitter I/Q input signal is upconverted to RF, and the
output of the transmitter is fed to the receiver downconverter input. Output signals are delivered to all receiver
baseband I/Q outputs. The I/Q lowpass filters in the
transmitter signal path are bypassed.
MAX2851
Baseband Loopback Mode
In baseband loopback mode, part of the Rx and Tx
baseband circuit blocks are powered and active. The
transmitter I/Q input signal is routed to the receiver lowpass filter input. Output signals are delivered to receiver 5
baseband I/Q outputs.
Power-On Sequence
Set the ENABLE pin to V
for 2ms to start the crystal
CC
oscillator. Program all SPI addresses according to recommended values. Set SPI Main address 0 D[4:2] from
000 to 001 to engage standby mode. To lock the LO
frequency, the user can set SPI in order of Main address
15, Main address 16, and then Main address 17 to trigger VCO sub-band autoacquisition; the acquisition takes
2ms. After the LO frequency is locked, set SPI Main
address 0 D[4:2] = 010 and 011 for Rx and Tx operating
modes, respectively. Before engaging to Rx mode, set
Main address 5 D1 = 1 to allow fast DC-offset settling.
After engaging to Rx mode and the Rx baseband DC
offset settles, the user can set Main address 5 D1 = 0 to
complete Rx DC-offset cancellation.
Programmable Registers and
4-Wire SPI Interface
The MAX2851 includes 60 programmable 16-bit registers. The most significant bit (MSB) is the read/write
selection bit (R/W in Figure 1). The next 5 bits are register
address (A[4:0] in Figure 1). The 10 least significant bits
(LSBs) are register data (D[9:0] in Figure 1). Register
data is loaded through the 4-wire SPI/MICROWIREKcompatible serial interface. MSB of data at the DIN pin
is shifted in first and is framed by CS. When CS is low,
the clock is active and input data is shifted at the rising
edge of the clock at the SCLK pin. At CS rising edge,
the 10-bit data bits are latched into the register selected
by the address bits. See Figure 1. To support more than
a 32-register address using a 5-bit-wide address word,
the bit 0 of address 0 is used to select whether the 5-bit
address word is applied to the main address or local
address. There is no power-on SPI register self-reset
functionality in the MAX2851; the user must program all
register values after power-up. During the read mode,
register data selected by address bits is shifted out to
the DOUT pin at the falling edges of the clock.
MICROWIRE is a trademark of National Semiconductor Corp.
All values in the register definition table are typical
numbers. The MAX2851 SPI does not have a power-
on-default self-reset feature; the user must program all
SPI addresses for normal operation. Prior to use of any
untested settings, contact the factory.
Main or local address select.
0 = Main registers (default)
1 = Local registers
DESCRIPTION
LNA gain control. Active when Rx channel is selected by corresponding RX_GAIN_PROG_SEL[5:1] bits in Main address 6 D[9:5].
000 = Max - 40dB
001 = Max - 32dB
100 = Max - 24dB (not tested, contact factory for coverage)
101 = Max - 16dB
110 = Max - 8dB
111 = Max gain (default)
Rx VGA gain control. Active when Rx channel is selected by corresponding RX_GAIN_PROG_SEL[5:1] bits in Main address 6 D[9:5].
00000 = Min gain
00001 = Min + 2dB
RSSI output select.
000 = Baseband RSSI (default)
001 = Do not use
010 = Do not use
011 = Do not use
100 = Rx RF detector
101 = Do not use
110 = PA power-detector mux output
111 = Do not use
5GHz, 5-Channel MIMO Receiver
Table 7. Main Address 5 (A[4:0] = 00101, Main Address 0 D0 = 0) (continued)
BIT NAME
MAX2851
RSSI_RX_SEL[2:0]D[5:3]
RXHPD1
Table 8. Main Address 6 (A[4:0] = 00110, Main Address 0 D0 = 0)
BIT NAME
RX_GAIN_PROG_SEL
[5:1]
BIT LOCATION
(D0 = LSB)
BIT LOCATION
(D0 = LSB)
D[9:5]
DESCRIPTION
Baseband RSSI Rx channel select.
000 = Not select (default)
001 = Rx1
010 = Rx2
011 = Rx3
100 = Rx4
101 = Rx5
110 = Do not use
111 = Do not use
Rx VGA highpass corner select after Rx turn-on. RXHP starts at 1 during Rx gain adjustment and set 0 after gain is adjusted.
0 = 10kHz highpass corner after Rx gain is adjusted (default)
1 = 600kHz highpass corner during Rx gain adjustment
DESCRIPTION
Rx channel gain programming select. Select which Rx channels are to be
changed; gain is then determined by programming Main address 1 D[7:0].
D9 selects Rx5, D8 selects Rx4, etc.
0 = Not selected
1 = Selected
1111 = Default
Rx MIMO channel select. Enable Rx channels independently.
D4 selects Rx5, D3 selects Rx4, etc.
E_RX[5:1]D[4:0]
0 = Not selected
1 = Select in Rx, RF loopback, or Tx calibration mode
11111 = Default
Table 9. Main Address 9 (A[4:0] = 01001, Main Address 0 D0 = 0)
Table 15. Main Address 19 (A[4:0] = 10011, Main Address 0 D0 = 0)
BIT NAME
RESERVEDD[9:8]Reserved bits—set to default.
VAS_RELOCK_SELD7
MAX2851
VAS_MODED6
VAS_SPI[5:0]D[5:0]
VAS_ADC[2:0]
(Readback Only)
VCO_BAND[5:0]
(Readback Only)
BIT LOCATION
(D0 = LSB)
D[8:6]
D[5:0]
DESCRIPTION
VAS relock select.
0 = Start at sub-band selected by VAS_SPI[5:0] (Main address 19
D5:D0) (default)
1 = Start at current sub-band
VCO sub-band select.
0 = By VAS_SPI[5:0] (Main address 19 D[5:0])
1 = By on-chip VCO autoselect (VAS) (default)
VCO autoselect sub-band input. Select VCO subband when VAS_
MODE (Main address 19 D6) = 0. Select initial VCO sub-band for autoacquisition when VAS_MODE = 1.
000000 = Min frequency sub-band
…
011111 = Default
…
111111 = Max frequency sub-band
Read VCO autoselect tune voltage ADC output. Active when VAS_
VCO_READ (Main address 27 D5) = 1.
000 = Lower than lock range and at risk of unlock
001 = Lower than acquisition range and maintain lock
010 or 101 = Within acquisition range and maintain lock
110 = Higher than acquisition range and maintain lock
111 = Higher than lock range and at risk of unlock
Read the current acquired VCO sub-band by VCO autoselect. Active
when VAS_VCO_READ (Main address 27 D5) = 1.
Table 16. Main Address 21 (A[4:0] = 10101, Main Address 0 D0 = 0)
BIT NAME
RESERVEDD[9:8], D[4:0]Reserved bits—set to default.
Read revision ID at Main address 21 D[7:5].
Active when DIE_ID_READ (Main address 27 D9) = 1.
000 = Pass1
001 = Pass2
…
5GHz, 5-Channel MIMO Receiver
Table 17. Main Address 27 (A[4:0] = 11011, Main Address 0 D0 = 0)
BIT NAME
DIE_ID_READD9
RESERVEDD[8:6], D[4:0]Reserved bits—set to default.
VAS_VCO_READD5
Table 18. Main Address 28 (A[4:0] = 11100, Main Address 0 D0 = 0)
BIT NAME
RESERVEDD[9:4]Reserved bits—set to default.
PA_BIAS_DLY[3:0]
BIT LOCATION
(D0 = LSB)
BIT LOCATION
(D0 = LSB)
D[3:0]
DESCRIPTION
Die ID readback select.
0 = Main address 21 D[9:0] reads its own values (default)
1 = Main address 21 D[7:5] reads revision ID
VAS ADC and VCO sub-band readback select.
0 = Main address 19 D[9:0] reads its own values (default)
1 = Main address 19 D[8:6] reads VAS_ADC[2:0]; Main address 19
D[5:0] reads VCO_BAND[5:0]
DESCRIPTION
PA_BIAS turn-on delay.
0000 = 0Fs
0001 = 0Fs
0010 = 0.5Fs
0011 = 1.0Fs (default)
…
1111 = 7.0Fs
Only default is tested; contact factory for test coverage.
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
01/10Initial release—
13/10Modified EC table to support single-pass room test flow2, 3, 5, 6–9
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
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