The MAX2850 is a single-chip, 4-channel RF transmitter
IC designed for 5GHz wireless HDMI applications. The
IC includes all circuitry required to implement the complete 4-channel MIMO RF transmitter function and crystal oscillator, providing a fully integrated transmit path,
VCO, frequency synthesis, and baseband/control interface. It includes a fast-settling, sigma-delta RF fractional
synthesizer with 76Hz frequency programming step
size. The IC also integrates on-chip I/Q amplitude and
phase-error calibration circuits. Dynamic on/off control
of four external PAs is implemented with programmable
precision voltages. A 4-to-1 analog mux routes external
PA power-detect voltages to the RSSI pin.
On-chip monolithic filters are included for transmitter I/Q
baseband signal reconstruction to support both 20MHz
and 40MHz RF channels. The baseband filtering and
Tx signal paths are optimized to meet stringent WHDI
requirements. The upconverter local oscillator is coherent among all the transmitter channels.
The reverse-link control channel uses an on-chip 5GHz
OFDM receiver. It shares the RF synthesizer and LO generation circuit with the MIMO transmitters. The receiver
includes both an in-channel RSSI and an RF RSSI.
The MIMO transmitter chip is housed in a small, 68-pin
thin QFN leadless plastic package with exposed pad.
Applications
5GHz Wireless HDMI (WHDI)
5GHz FDD Backhaul and WiMax™
5GHz MIMO Transmitter Up to Four Spatial
Streams
5GHz Beam Steering Transmitter
Features
S5GHz 4x MIMO Downlink Transmitters, Single
Uplink IEEE 802.11a Receiver
4900MHz to 5900MHz Frequency Range
-5dBm Transmit Power (54Mbps OFDM)Coherent LO Among Transmitters31dB Tx Gain-Control Range with 0.5dB Step
Size, Digitally Controlled
Tx/Rx I/Q Error and LO Leakage Detection and
Adjustment
Programmable 20MHz/40MHz Tx I/Q Lowpass
Anti-Aliasing Filter
4-to-1 Analog Mux for PA Power Detect4-Channel PA On/Off Control
4.5dB Rx Noise Figure70dB Rx Gain-Control Range with 2dB Step
4-Wire SPI™I/Q Analog Baseband InterfaceDigital Tx/Rx Mode ControlOn-Chip Digital Temperature Sensor ReadoutComplete Baseband InterfaceDigital Tx/Rx Mode Control
S
+2.7V to +3.6V Supply Voltage
S
Small, 68-Pin Thin QFN Package (10mm x 10mm)
Digital Interface
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX2850ITK+
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
-25NC to +85NC
68 Thin QFN-EP*
MAX2850
WiMax is a trademark of WiMax Forum.
SPI is a trademark of Motorola, Inc.
XTAL_CAP to GND ...........................................-0.3V to +3.9V
Analog Outputs: RXBBI+, RXBBI-, RXBBQ+,
RXBBQ-, RSSI, CLKOUT2, VCOBYP, CPOUT+,
CPOUT-, PA_BIAS1, PA_BIAS2,
PA_BIAS3, PA_BIAS4 to GND ..........................-0.3V to +3.9V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, ENABLE set according to operating mode, CS = high, SCLK
= DIN = low, transmitter in maximum gain, T
using the Typical Operating Circuit. 100mV
mode. Typical values measured at V
40MHz. PA control pins open circuit, V
PARAMETERSCONDITIONSMINTYPMAXUNITS
Supply Voltage, V
Supply Current
Rx I/Q Output Common-Mode
Voltage
Tx Baseband Input CommonMode Voltage Operating Range
Tx Baseband Input Bias CurrentSource current 1020
CC
CC
Shutdown mode
Clock-out only mode
Standby mode6089
Transmit mode
Receive mode135174
Transmit calibration mode
Receive calibration mode268327
= -25NC to +85NC. Power matching and termination for the differential RF output pins
A
differential I and Q signals applied to I/Q baseband inputs of transmitters in transmit
RMS
= 2.85V, TA = +25NC, LO frequency = 5.35GHz, TA = +25NC. Channel bandwidth is set to
CC_PA_BIAS
is disconnected.) (Note 1)
Digital Inputs: ENABLE, CS, SCLK, DIN to GND ... -0.3V to +3.9V
Digital Outputs: DOUT, CLKOUT to GND ............ -0.3V to +3.9V
Short-Circuit Duration
Analog Outputs ................................................................. 10s
Digital Outputs ................................................................... 10s
RF Input Power .............................................................. +10dBm
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, ENABLE set according to operating mode, CS = high, SCLK
= DIN = low, transmitter in maximum gain, T
using the Typical Operating Circuit. 100mV
mode. Typical values measured at V
40MHz. PA control pins open circuit, V
PARAMETERSCONDITIONSMINTYPMAXUNITS
LOGIC INPUTS: ENABLE, SCLK, DIN, CS
Digital Input-Voltage High, V
Digital Input-Voltage Low, V
Digital Input-Current High, I
Digital Input-Current Low, I
LOGIC OUTPUTS: DOUT, CLKOUT
Digital Output-Voltage High, V
Digital Output-Voltage Low, V
Digital Output Voltage in
Shutdown Mode
IL
IH
IL
CC
IH
Sourcing 1mA
OH
Sinking 1mA0.4V
OL
Sinking 1mAV
AC ELECTRICAL CHARACTERISTICS—Rx MODE
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF+ and
RXRF- differential ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
resistance and 10pF load capacitance. The RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
= 2.85V, channel bandwidths of 40MHz, T
PARAMETERCONDITIONSMINTYPMAXUNITS
RECEIVER SECTION: RF INPUT TO I/Q BASEBAND LOADED OUTPUT (Includes 50I to 100I RF Balun and Matching)
RF Input Frequency Range4.95.9GHz
Peak-to-Peak Gain Variation
over RF Frequency Range at
One Temperature
RF Input Return LossAll LNA settings-6dB
Total Voltage Gain
RF Gain Steps Relative to
Maximum Gain
Baseband Gain Range
Baseband Gain Step2dB
RF Gain Change Settling Time
4.9GHz to 5.35GHz0.32.6
5.35GHz to 5.9GHz 2.25.3
Maximum gain; Main address 1 D7:0 = 111111116168
Minimum gain; Main address 1 D7:0 = 00000000 -2+5
Main address 1 D7:D5 = 110-8
Main address 1 D7:D5 = 101-16
Main address 1 D7:D5 = 001-32
Main address 1 D7:D5 = 000-40
From maximum baseband gain (Main address 1 D3:D0
= 1111) to minimum baseband gain (Main address 1
D3:D0 = 0000)
Gain settling to within Q0.5dB of steady state; RXHP = 1
= -25NC to +85NC. Power matching and termination for the differential RF output pins
A
differential I and Q signals applied to I/Q baseband inputs of transmitters in transmit
RMS
= 2.85V, TA = +25NC, LO frequency = 5.35GHz, TA = +25NC. Channel bandwidth is set to
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF+ and
RXRF- differential ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
resistance and 10pF load capacitance. The RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
= 2.85V, channel bandwidths of 40MHz, T
PARAMETERCONDITIONSMINTYPMAXUNITS
Baseband Gain-Change Settling
MAX2850
Time
DSB Noise Figure
Out-of-Band Input IP3
1dB Gain Desensitization by
Alternate Channel Blocker
Input 1dB Gain Compression
Output 1dB Gain Compression
= +25NC.) (Note 1)
A
Gain settling to within Q0.5dB of steady state; RXHP = 1
Balun input referred,
integrated from 10kHz
to 9.5MHz at I/Q baseband output for 20MHz
RF bandwidth
Balun input referred,
integrated from 10kHz
to 19MHz at I/Q baseband output for 40MHz
RF bandwidth
20MHz RF channel;
two tone jammers at
+25MHz and +48MHz
frequency offset with
-39dBm/tone
40MHz RF channel;
two tone jammers at
+50MHz and +96MHz
frequency offset with
-39dBm/tone
Blocker at Q40MHz offset frequency for 20MHz RF
channel
Blocker at Q80MHz offset frequency for 40MHz RF
channel
Max RF gain (Main address 1 D7:D5 = 111)-32
Max RF gain - 8dB (Main address 1 D7:D5 = 110)-24
Max RF gain - 16dB (Main address 1 D7:D5 = 101)-16
Max RF gain - 32dB (Main address 1 D7:D5 = 001)0
Over passband frequency range; at any gain setting;
1dB compression point
Maximum RF gain (Main
address 1 D7:D5 = 111)
Maximum RF gain - 16dB
(Main address 1 D7:D5 = 101)
Maximum RF gain (Main
address 1 D7:D5 = 111)
Maximum RF gain - 16dB
(Main address 1 D7:D5 = 101)
-65dBm wanted signal; RF
gain = max (Main address 1
D7:D0 = 11101001)
-49dBm wanted signal; RF
gain = max - 16dB (Main
address 1 D7:D0 = 10101001)
-45dBm wanted signal; RF
gain = max - 32dB (Main
address 1 D7:D0 = 00111111)
-65dBm wanted signal; RF
gain = max (Main address 1
D7:D0 = 11101001)
-49dBm wanted signal; RF
gain = max - 16dB (Main
address 1 D7:D0 = 10101001)
-45dBm wanted signal; RF
gain = max - 32dB (Main
address 1 D7:D0 = 00101001)
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at RXRF+ and
RXRF- differential ports using the Typical Operating Circuit. Receiver I/Q output at 100mV
resistance and 10pF load capacitance. The RSSI pin is loaded with 10kI load resistance to ground. Typical values measured at V
= 2.85V, channel bandwidths of 40MHz, T
Main address 0 D1 = 09.5
Main address 0 D1 = 119
Rejection at 30MHz offset frequency for 20MHz channel5770
Rejection at 60MHz offset frequency for 40MHz channel5770
Main address 5 D1 = 1600
Main address 5 D1 = 010
50Fs after enabling receive mode and toggling RxHP
from 1 to 0, averaged over many measurements if I/Q
noise voltage exceeds 1mV
ting, no input signal, 1-sigma value
LO frequency-75
2 x LO frequency-62
3 x LO frequency-75
4 x LO frequency-60
Tx VGA gain at maximum (Main address 9 D9:D4
= 111111); Rx VGA gain at maximum - 24dB (Main
address 1 D3:D0 = 0101)
, at any given gain set-
RMS
loaded with 10kI differential load
RMS
2mV
2.3V
0.5V
-6+2+10dB
CC
MHz
dB
kHz
dBm/
MHz
MAX2850
AC ELECTRICAL CHARACTERISTICS—Tx MODE
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at TXRF+ and
TXRF- differential ports using the Typical Operating Circuit. 100mV
transmitter (differential DC-coupled). Typical values measured at V
PARAMETERCONDITIONSMINTYPMAXUNITS
TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS (Includes Matching and Balun Loss)
sine and cosine signal applied to I/Q baseband inputs of
RMS
= 2.85V, channel bandwidths of 40MHz, TA = +25NC.) (Note 1)
CC
5GHz, 4-Channel MIMO Transmitter
AC ELECTRICAL CHARACTERISTICS—Tx MODE (continued)
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, RF frequency = 5.351GHz, TA = -25NC to +85NC. LO frequency
= 5.35GHz. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, with power matching at TXRF+ and
TXRF- differential ports using the Typical Operating Circuit. 100mV
transmitter (differential DC-coupled). Typical values measured at V
Tx Calibration Gain RangeAdjust Local address 27 D2:D035dB
mask and -34dB EVM
40MHz OFDM signal conforming to spectral emission
mask and -34dB EVM
Relative to typical maximum output power at 9.5MHz
input frequency
At 19MHz input frequency, over input common-mode
voltage between 0.5V and 1.1V
Over RF channel, RF frequency, baseband frequency,
and gain settings (Note 2)
Over RF channel, RF frequency, and gain settings
(Note 2)
Minimum differential resistance60
Maximum differential capacitance2pF
At 30MHz frequency offset for 20MHz RF channel86
At 60MHz frequency offset for 40MHz RF channel67
At Tx gain code (Main address 9 D9:D4) = 100010 and
-15dBc carrier leakage (Local address 27 D2:D0 = 110
and Main address 1 D3:D0 = 0000)
sine and cosine signal applied to I/Q baseband inputs of
RMS
= 2.85V, channel bandwidths of 40MHz, TA = +25NC.) (Note 1)
CC
-4
-4
11dBc
380mV
-40dBc
-29-15dBc
-28dBV
dBm
RMS
kI
dB
RMS
AC ELECTRICAL CHARACTERISTICS—FREQUENCY SYNTHESIS
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, frequency = 5.35GHz, TA = -25NC to +85NC. Reference
frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low. Typical values measured at V
(Operating conditions, unless otherwise specified: VCC = 2.7V~3.6V, frequency = 5.35GHz, TA = -25NC to +85NC,. Reference frequency = 40MHz, ENABLE = high, CS = high, SCLK = DIN = low, typical values measured at V
T
= +25NC.) (Note 1)
A
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Rx to Tx mode, Tx gain settles
MAX2850
Rx/Tx Turnaround Time
Tx Turn-On Time (from
Standby Mode)
Tx Turn-Off Time (to Standby
Mode)
Rx Turn-On Time (from
Standby Mode)
Rx Turn-Off Time (to Standby
Mode)
4-WIRE SERIAL-INTERFACE TIMING (See Figure 1)
SCLK Rising Edge to CS
Falling Edge Wait Time
Falling Edge of CS to Rising
Edge of First SCLK Time
DIN to SCLK Setup Timet
DIN to SCLK Hold Timet
SCLK Pulse-Width Hight
SCLK Pulse-Width Lowt
Last Rising Edge of SCLK to
Rising Edge of CS or Clock to
Load Enable Setup Time
CS High Pulse Width
Time Between Rising Edge of
CS and the Next Rising Edge
of SCLK
SCLK Frequencyf
Rise Timet
Fall Timet
SCLK Falling Edge to Valid
DOUT
Note 1: The MAX2850 is production tested at T
specified otherwise. Minimum/maximum limits at TA = -25NC and +85NC are guaranteed by design and characterization.
There is no power-on register settings self-reset; recommended register settings must be loaded after VCC is applied.
Note 2: For optimal Rx and Tx quadrature accuracy over temperature, the user can utilize the Rx calibration and Tx calibration
circuit to assist quadrature calibration.
t
CSO
t
CSS
DS
DH
CH
CL
t
CSH
t
CSW
t
CS1
CLK
t
Measured
from CS rising edge
Measured from CS rising edge, Tx gain settles
to within 0.2dB of steady state
From CS rising edge
Measured from CS rising edge, Rx gain settles
to within 0.5dB of steady state
From CS rising edge
6ns
R
F
D
= +25NC; minimum/maximum limits at TA = +25NC are guaranteed by test, unless
A
to within 0.2dB of steady state
Tx to Rx mode with RXHP = 1,
Rx gain settles to within 0.5dB
of steady state
Transmitter 1 Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmitter 2 Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmitter 2 Differential Output. These pins are in open-collector configuration. These pins should
be biased at the supply voltage with differential impedance terminated at 300I.
External Power-Amplifier Voltage Bias and Detector Mux Supply Voltage. Bypass with a capacitor as
close as possible to the pin.
LO Generation Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmitter 3 Differential Output. These pins are in open-collector configuration. These pins should
be biased at the supply voltage with differential impedance terminated at 300I.
5GHz, 4-Channel MIMO Transmitter
Pin Description (continued)
PINNAMEFUNCTION
15GNDGround
16V
17V
18GNDGround
19PA_BIAS4External Power-Amplifier Voltage Bias Output 4
20TXRF4+
21TXRF422PA_DET4External Power-Amplifier Detector Mux Input 4
23V
24RXRF25RXRF+
26V
27V
28TXBBI4+
29TXBBI430TXBBQ4+
31TXBBQ432
33SCLKSerial-Clock Logic Input of 4-Wire Serial Interface
34DINData Logic Input of 4-Wire Serial Interface
35TXBBI3+
36TXBBI337TXBBQ3+
38TXBBQ339RXBBI+
40RXBBI41RXBBQ+
42RXBBQ43RSSIReceiver Signal-Strength Indicator Output
44V
45BYP_VCO
46GND_VCOVCO Ground
47CPOUT+
48CPOUT49V
50DOUTData Logic Output of 4-Wire Serial Interface
51CLKOUTReference Clock Buffer Output
52V
53XTALCrystal Oscillator Base Input. AC-couple crystal unit to this pin.
54XTAL_CAPCrystal Oscillator Emitter Node
55ENABLEEnable Logic Input
CC_UCX3
CC_UCX4
CC_LNA
CC_MXR
CC_BB2
CS
CC_VCO
CC_DIG
CC_XTAL
Transmitter 3 Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmitter 4 Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmitter 4 Differential Output. These pins are in open-collector configuration. These pins should
be biased at the supply voltage with differential impedance terminated at 300I.
Receiver LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver LNA Differential Input. Input is DC-coupled and biased internally at 1.2V.
Receiver Downconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Receiver Baseband Supply Voltage 2. Bypass with a capacitor as close as possible to the pin.
VCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.
On-Chip VCO Regulator Output Bypass. Bypass with an external 1FF capacitor to GND_VCO with
minimum PCB trace. Do not connect other circuitry to this pin.
Differential Charge-Pump Output. Connect the frequency synthesizer’s loop filter between CPOUT+
and CPOUT- (see the Typical Operating Circuit).
Digital Block Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Crystal Oscillator Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Note 4: PA_BIAS pins may be kept active in nontransmit mode(s) by SPI programming.
Note 5: CLKOUT signal is active independent of SPI, and is only dependent on the ENABLE pin.
Transmitter 1 Differential Output. These pins are in open-collector configuration. These pins should
be biased at the supply voltage with differential impedance terminated at 300I.
Exposed Pad. Connect to the ground plane with multiple vias for proper operation and heat dissipation. Do not share with any other pin grounds and bypass capacitors’ ground.
pin ENABLE (pin 55) and SPI Main address 0 D4:D2
control the various modes.
Modes of Operation
The modes of operation for the MAX2850 are shutdown,
clockout, standby, receive, transmit, transmitter calibration, RF loopback, and baseband loopback. See Table 1
for a summary of the modes of operation. The logic input
The MAX2850 features a low-power shutdown mode. All
circuit blocks are powered down, except the 4-wire serial
bus and its internal programmable registers.
Shutdown Mode
5GHz, 4-Channel MIMO Transmitter
Clockout Mode
In clockout mode, only the crystal oscillator signal is
active at the CLKOUT pin. The rest of the transceiver is
powered down.
Standby Mode
In standby mode, PLL, VCO, and LO generation are on.
Tx or Rx modes can be quickly enabled from this mode.
Other blocks may be selectively enabled in this mode.
Receive (Rx) Mode
In receive mode, all Rx circuit blocks are powered on
and active. Antenna signal is applied; RF is downconverted, filtered, and buffered at Rx baseband I and Q
outputs.
Transmit (Tx) Mode
In transmit mode, all Tx circuit blocks are powered on
and active. The external PA can be powered on through
the PA_BIAS pins after a programmable delay.
Transmit Calibration
In transmit calibration mode, all Tx circuit blocks are
powered on and active. The AM detector and receiver
I/Q channel buffers are also on. Output signals are
routed to Rx baseband I and Q outputs.
The AM detector multiplies the Tx RF output signal with
itself. The self-mixing product of the wanted sideband
becomes DC voltage and is filtered on-chip. The mixing product between wanted sideband and the carrier
leakage forms Ftone at Rx baseband output. The mixing
product between the wanted sideband and the unwanted sideband forms 2Ftone at Rx baseband output.
As Tx RF output is self-mixed at the AM detector, the
AM detector output responds differently to different gain
settings and power levels. When Tx RF output power
changes by 1dB through Tx gain control, the AM detector
output changes by 2dB as both the wanted sideband and
carrier leakage (or unwanted sideband) change by 1dB.
When Tx RF output carrier leakage (or unwanted sideband) changes by 1dB while the wanted sideband output
power is constant, the AM detector output changes by
1dB only.
RF Loopback
In RF loopback mode, part of the Rx and Tx circuit
blocks except the LNA are powered on and active. The
transmitter 4 I/Q input signal is upconverted to RF, and
the output of the transmitter is fed to the receiver downconverter input. Output signals are delivered to receiver
4 baseband I/Q outputs. The I/Q lowpass filters in the
transmitter signal path are bypassed.
Baseband Loopback
In baseband loopback mode, part of the Rx and Tx
baseband circuit blocks are powered and active. The
transmitter 4 I/Q input signal is routed to receiver lowpass filter input. Output signals are delivered to receiver
4 baseband I/Q outputs.
Power-On Sequence
Set the ENABLE pin to V
oscillator. Program all SPI addresses according to recommended values. Set SPI Main address 0 D4:D2 from
000 to 001 to engage standby mode. To lock the LO
frequency, the user can set SPI in order of Main address
15, Main address 16, and then Main address 17 to trigger VCO sub-band autoacquisition; the acquisition will
take 2ms. After the LO frequency is locked, set SPI Main
address 0 D4:D2 = 010 and 011 for Rx and Tx operating modes, respectively. Before engaging Rx mode, set
Main address 5 D1 = 1 to allow fast DC offset settling.
After engaging Rx mode and Rx baseband DC offset
settles, the user can set Main address 5 D1 = 0 to complete Rx DC offset cancellation.
for 2ms to start the crystal
CC
Programmable Registers and
4-Wire SPI Interface
The MAX2850 includes 60 programmable 16-bit registers. The most significant bit (MSB) is the read/write
selection bit (R/W in Figure 1). The next 5 bits are register
address (A4:A0 in Figure 1). The 10 least significant bits
(LSBs) are register data (D9:D0 in Figure 1). Register
data is loaded through the 4-wire SPI/MICROWIRE™compatible serial interface. MSB of data at the DIN pin
is shifted in first and is framed by CS. When CS is low,
the clock is active, and input data is shifted at the rising
edge of the clock at SCLK pin. At the CS rising edge,
the 10-bit data bits are latched into the register selected
by address bits. See Figure 1. To support more than a
32-register address using a 5-bit wide address word,
the bit 0 of address 0 is used to select whether the 5-bit
address word is applied to the main address or local
address. The register values are preserved in shutdown
mode as long as the power-supply voltage is maintained.
There is no power-on SPI register self-reset functionality
in the MAX2850, so the user must program all register
values after power-up. During the read mode, register
data selected by address bits is shifted out to the DOUT
pin at the falling edges of the clock.
MAX2850
MICROWIRE is a trademark of National Semiconductor Corp.
(All values in the register summary table are typical numbers. The MAX2850 SPI does not have a power-on-default selfreset feature; the user must program all SPI addresses for normal operation. Prior to use of any untested settings, contact
the factory.)
Table 4. Main Address 1: (A4:A0 = 00001, Main Address 0 D0 = 0)
BIT NAME
RESERVEDD9:D8Reserved bits; set to default
LNA_GAIN<2:0>D7:D5
VGA_GAIN<4:0>D4:D0
BIT LOCATION
(D0 = LSB)
LNA Gain Control
Active when Rx channel is selected by corresponding
RX_PATH_UNMASK<5:1> bits in Main address 6 D9:D5.
000 = Maximum - 40dB
001 = Maximum - 32dB
100 = Maximum - 24dB
101 = Maximum - 16dB
110 = Maximum - 8dB
111 = Maximum gain (default)
Rx VGA Gain Control
Active when Rx channel is selected by corresponding
RX_PATH_UNMASK<5:1> bits in Main address 6 D9:D5.
00000 = Minimum gain
00001 = Minimum + 2dB
000 = Baseband RSSI (default)
001 = Do not use
010 = Do not use
011 = Do not use
100 = Rx RF detector
101 = Do not use
110 = PA power-detector mux output
111 = Do not use
Rx VGA Highpass Corner Select after Rx Turn-On
RXHP starts at 1 during Rx gain adjustment, and set to 0 after gain is
adjusted.
0 = 10kHz highpass corner after Rx gain is adjusted (default)
1 = 600kHz highpass corner during Rx gain adjustment
5GHz, 4-Channel MIMO Transmitter
Table 8. Main Address 9: (A4:A0 = 01001, Main Address 0 D0 = 0)
BIT NAME
TX_GAIN<5:0>D9:D4
BIT LOCATION
(D0 = LSB)
DESCRIPTION
Tx VGA Gain Control
Tx channel is selected by Main address 9 D3:D0.
000000 = Minimum gain (default)
…
111111 = Minimum gain + 31.5dB
Tx Channel Gain Programming Select
Gain is determined by Main address 9 D9:D4.
TX_GAIN_PROG_SEL<4:1>D3:D0
0 = Not selected
1 = Selected
1111 = Default
Table 9. Main Address 11: (A4:A0 = 01011, Main Address 0 D0 = 0)
BIT NAME
RESERVEDD9:D4Reserved bits; set to default
E_TX_AMD<1:0>D3:D2
BIT LOCATION
(D0 = LSB)
DESCRIPTION
Tx Calibration AM Detector Channel Select
Only active in Tx calibration mode.
00 = Select TX1 (default)
01 = Select TX2
10 = Select TX3
11 = Select TX4
0 = Start at sub-band selected by VAS_SPI<5:0> (Main address 19 D5:D0)
(default)
1 = Start at current sub-band
VCO Subband Select
0 = By VAS_SPI<5:0> (Main address 19 D5:D0)
1 = By on-chip VCO autoselect (VAS) (default)
5GHz, 4-Channel MIMO Transmitter
Table 15. Main Address 19: (A4:A0 = 10011, Main Address 0 D0 = 0) (continued)
MAX2850
BIT NAME
VAS_SPI<5:0>D5:D0
BIT LOCATION
(D0 = LSB)
DESCRIPTION
VCO Autoselect Sub-Band Input
Select VCO sub-band when VAS_MODE (Main address 19 D6) = 0.
Select initial VCO sub-band for autoacquisition when VAS_MODE = 1.
000000 = Minimum frequency sub-band
…
011111 = Default
…
111111 = Maximum frequency sub-band
Read VCO Autoselect Tune Voltage ADC Output
Active when VCO_VAS_RB (Main address 27 D5) = 1.
VAS_ADC<2:0>
(Readback Only)
VCO_BAND<5:0>
(Readback Only)
D8:D6
D5:D0
000 = Lower than lock range and at risk of unlock
001 = Lower than acquisition range and maintain lock
010 or 101 = Within acquisition range and maintain lock
110 = Higher than acquisition range and maintain lock
111 = Higher than lock range and at risk of unlock
Read the Current Acquired VCO Sub-Band by VCO Autoselect
Active when VCO_VAS_RB (Main address 27 D5) = 1.
Table 16. Main Address 21: (A4:A0 = 10101, Main Address 0 D0 = 0)
BIT NAME
RESERVEDD9:D0Reserved bits; set to default
DIE_ID<2:0>
(Readback Only)
BIT LOCATION
(D0 = LSB)
D7:D5
DESCRIPTION
Read Revision ID at Main Address 21 D7:D5
Active when DIE_ID_READ (Main address 27 D9) = 1.
000 = Pass1
001 = Pass2
…
Table 17. Main Address 27: (A4:A0 = 11011, Main Address 0 D0 = 0)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suffix character, but the drawing pertains to the package
regardless of RoHS status.
010/09Initial release—
13/10Modified EC table to support single-pass room test flow2, 3, 5, 6, 8
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
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